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authorMaciej W. Rozycki <macro@linux-mips.org>2013-08-23 14:12:59 +0000
committerMaciej W. Rozycki <macro@linux-mips.org>2013-08-23 14:12:59 +0000
commitfb6f389526a8e5c282dbf144ccdbe4cc2fc6707d (patch)
treebfaa16f905f6253488688447fa9bec2bf4412502 /opcodes
parent021f8a30f40d55a623d34ce6779e30ed3037ca2d (diff)
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opcodes/
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", replacing NODS. gas/testsuite/ * gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay slot scheduling of ALNV.PS. * gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise. * gas/testsuite/gas/mips/micromips-trap.d: Likewise. * gas/testsuite/gas/mips/micromips.d: Likewise. * gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/micromips-opc.c4
2 files changed, 6 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7427f14..ce6aebe 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
+ replacing NODS.
+
2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
PR binutils/15834
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index da1f708..fa6efb5 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -309,9 +309,7 @@ const struct mips_opcode micromips_opcodes[] =
{"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 },
-/* We have no flag to mark the read from "y", so we use NODS to disable
- delay slot scheduling of ALNV.PS altogether. */
-{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|NODS|FP_D, 0, I1, 0, 0 },
+{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
{"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
{"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },