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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-08-01 20:25:30 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-08-01 20:25:30 +0000 |
| commit | 344c74a665f2f76ce61b1306fa983d7862ab66dc (patch) | |
| tree | 99c9efb0052b8f1c171a996fc6bf73eada4af16c /opcodes | |
| parent | 41989114b803bc1da171c59f941adf2064504473 (diff) | |
| download | gdb-344c74a665f2f76ce61b1306fa983d7862ab66dc.zip gdb-344c74a665f2f76ce61b1306fa983d7862ab66dc.tar.gz gdb-344c74a665f2f76ce61b1306fa983d7862ab66dc.tar.bz2 | |
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
for the single-operand forms of JALR and JALR.HB.
* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
and JALRS.HB.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 8 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
3 files changed, 13 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b021f90..081c924 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> + * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d + for the single-operand forms of JALR and JALR.HB. + * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB + and JALRS.HB. + +2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> + * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector instructions. Fix them to use WR_MACC instead of WR_CC and add missing RD_MACCs. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index d8e4c72..30dec8f 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -707,15 +707,15 @@ const struct mips_opcode micromips_opcodes[] = {"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 }, {"jalr", "mj", 0x45c0, 0xffe0, UBD|WR_31, RD_mj|BD32, I1, 0, 0 }, {"jalr", "my,mj", 0x45c0, 0xffe0, UBD|WR_31, RD_mj|BD32, I1, 0, 0 }, -{"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1, 0, 0 }, +{"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_31, BD32, I1, 0, 0 }, {"jalr", "t,s", 0x00000f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1, 0, 0 }, -{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1, 0, 0 }, +{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_31, BD32, I1, 0, 0 }, {"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1, 0, 0 }, {"jalrs", "mj", 0x45e0, 0xffe0, UBD|WR_31, RD_mj|BD16, I1, 0, 0 }, {"jalrs", "my,mj", 0x45e0, 0xffe0, UBD|WR_31, RD_mj|BD16, I1, 0, 0 }, -{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1, 0, 0 }, +{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_31, BD16, I1, 0, 0 }, {"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1, 0, 0 }, -{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1, 0, 0 }, +{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_31, BD16, I1, 0, 0 }, {"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1, 0, 0 }, /* SVR4 PIC code requires special handling for jal, so it must be a macro. */ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 80b555b..ba817f5 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -942,11 +942,11 @@ const struct mips_opcode mips_builtin_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 }, -{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1, 0, 0 }, +{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_31, 0, I1, 0, 0 }, {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1, 0, 0 }, /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr with the same hazard barrier effect. */ -{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32, 0, 0 }, +{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_31, 0, I32, 0, 0 }, {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32, 0, 0 }, /* SVR4 PIC code requires special handling for jal, so it must be a macro. */ |