bfd:

	* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
	(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
	(BFD32_BACKENDS): Add elf32-epiphany.lo .
	(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
	* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
	* archures.c (bfd_arch_epiphany): Add.
	(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
	(bfd_epiphany_arch): Declare.
	(bfd_archures_list): Add &bfd_epiphany_arch.
	* config.bfd (epiphany-*-elf): New target case.
	* configure.in (bfd_elf32_epiphany_vec): New target vector case.
	* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
	(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
	(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
	(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
	* targets.c (bfd_elf32_epiphany_vec): Declare.
	(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
	* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
	* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
	* readelf.c (include "elf/epiphany.h")
	(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
	(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
	(is_16bit_abs_reloc, is_none_reloc): Likewise.
	* po/binutils.pot: Regenerate.
cpu:
	* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
	* NEWS: Mention addition of Adapteva Epiphany support.
	* config/tc-epiphany.c, config/tc-epiphany.h: New files.
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
	(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
	* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
	* configure.in: Also set using_cgen for epiphany.
	* configure.tgt: Handle epiphany.
	* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
	* doc/all.texi: Set EPIPHANY.
	* doc/as.texinfo: Add EPIPHANY-specific text.
	* doc/c-epiphany.texi: New file.
	* po/gas.pot: Regenerate.
gas/testsuite:
	* gas/epiphany: New directory.
include:
	* dis-asm.h (print_insn_epiphany): Declare.
	* elf/epiphany.h: New file.
	* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
	* NEWS: Mention addition of Adapteva Epiphany support.
	* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
	(eelf32epiphany.c): New rule.
	* Makefile.in: Regenerate.
	* configure.tgt: Handle epiphany-*-elf.
	* po/ld.pot: Regenerate.
	* testsuite/ld-srec/srec.exp: xfail epiphany.
	* emulparams/elf32epiphany.sh: New file.
opcodes:
	* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
	(TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
	epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
	(CLEANFILES): Add stamp-epiphany.
	(EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
	(stamp-epiphany): New rule.
	* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
	* configure.in: Handle bfd_epiphany_arch.
	* disassemble.c (ARCH_epiphany): Define.
	(disassembler): Handle bfd_arch_epiphany.
	* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
	* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
	* epiphany-opc.h: Likewise.

15 files changed, 10492 insertions, 141 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0158cf1..6ad9cf3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,26 @@
+2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+	* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
+	(TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
+	epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
+	(CLEANFILES): Add stamp-epiphany.
+	(EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
+	(stamp-epiphany): New rule.
+	* configure.in: Handle bfd_epiphany_arch.
+	* disassemble.c (ARCH_epiphany): Define.
+	(disassembler): Handle bfd_arch_epiphany.
+	* epiphany-asm.c: New file.
+	* epiphany-desc.c: New file.
+	* epiphany-desc.h: New file.
+	* epiphany-dis.c: New file.
+	* epiphany-ibld.c: New file.
+	* epiphany-opc.c: New file.
+	* epiphany-opc.h: New file.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
 2011-10-24  Julian Brown  <julian@codesourcery.com>
 
 	* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index ec7fa3e..cae73c2 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -41,6 +41,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
 
 # Header files.
 HFILES = \
+	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
 	frv-desc.h frv-opc.h \
 	h8500-opc.h \
@@ -95,6 +96,11 @@ TARGET_LIBOPCODES_CFILES = \
 	d30v-dis.c \
 	d30v-opc.c \
 	dlx-dis.c \
+	epiphany-asm.c \
+	epiphany-desc.c \
+	epiphany-dis.c \
+	epiphany-ibld.c \
+	epiphany-opc.c \
 	fr30-asm.c \
 	fr30-desc.c \
 	fr30-dis.c \
@@ -311,7 +317,7 @@ po/POTFILES.in: @MAINT@ Makefile
 	  && mv tmp $(srcdir)/po/POTFILES.in
 
 CLEANFILES = \
-	stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
+	stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
 	stamp-m32c stamp-m32r stamp-mep stamp-mt \
 	stamp-openrisc stamp-xc16x stamp-xstormy16 \
 	libopcodes.a stamp-lib
@@ -329,9 +335,10 @@ CGENDEPS = \
 	$(CGENDIR)/opc-opinst.scm \
 	cgen-asm.in cgen-dis.in cgen-ibld.in
 
-CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
 
 if CGEN_MAINT
+EPIPHANY_DEPS = stamp-epiphany
 FR30_DEPS = stamp-fr30
 FRV_DEPS = stamp-frv
 IP2K_DEPS = stamp-ip2k
@@ -345,6 +352,7 @@ OPENRISC_DEPS = stamp-openrisc
 XC16X_DEPS = stamp-xc16x
 XSTORMY16_DEPS = stamp-xstormy16
 else
+EPIPHANY_DEPS =
 FR30_DEPS =
 FRV_DEPS =
 IP2K_DEPS =
@@ -376,6 +384,16 @@ run-cgen-all:
 
 # For now, require developers to configure with --enable-cgen-maint.
 
+$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
+		$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
+		$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
+		$(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
+	@true
+
+stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
+	$(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
+		archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
+
 $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
 	@true
 stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 7d260a7..6c2815d 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -310,6 +310,7 @@ BFD_H = ../bfd/bfd.h
 
 # Header files.
 HFILES = \
+	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
 	frv-desc.h frv-opc.h \
 	h8500-opc.h \
@@ -365,6 +366,11 @@ TARGET_LIBOPCODES_CFILES = \
 	d30v-dis.c \
 	d30v-opc.c \
 	dlx-dis.c \
+	epiphany-asm.c \
+	epiphany-desc.c \
+	epiphany-dis.c \
+	epiphany-ibld.c \
+	epiphany-opc.c \
 	fr30-asm.c \
 	fr30-desc.c \
 	fr30-dis.c \
@@ -550,7 +556,7 @@ noinst_LIBRARIES = libopcodes.a
 libopcodes_a_SOURCES = 
 POTFILES = $(HFILES) $(CFILES)
 CLEANFILES = \
-	stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
+	stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
 	stamp-m32c stamp-m32r stamp-mep stamp-mt \
 	stamp-openrisc stamp-xc16x stamp-xstormy16 \
 	libopcodes.a stamp-lib
@@ -566,7 +572,9 @@ CGENDEPS = \
 	$(CGENDIR)/opc-opinst.scm \
 	cgen-asm.in cgen-dis.in cgen-ibld.in
 
-CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+@CGEN_MAINT_FALSE@EPIPHANY_DEPS = 
+@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
 @CGEN_MAINT_FALSE@FR30_DEPS = 
 @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
 @CGEN_MAINT_FALSE@FRV_DEPS = 
@@ -741,6 +749,11 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dis-init.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/disassemble.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlx-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-desc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-ibld.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-opc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-asm.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-desc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-dis.Plo@am__quote@
@@ -1229,6 +1242,16 @@ run-cgen-all:
 
 # For now, require developers to configure with --enable-cgen-maint.
 
+$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
+		$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
+		$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
+		$(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
+	@true
+
+stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
+	$(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
+		archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
+
 $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
 	@true
 stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
diff --git a/opcodes/configure b/opcodes/configure
index 746070e..d89ed6a 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12429,6 +12429,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
 	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_ip2k_arch)		ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
+	bfd_epiphany_arch)		ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
         bfd_iq2000_arch)        ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
 	bfd_lm32_arch)          ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
 	bfd_m32c_arch)		ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 3776be3..fc87735 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -243,6 +243,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
 	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_ip2k_arch)		ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
+	bfd_epiphany_arch)		ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
         bfd_iq2000_arch)        ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
 	bfd_lm32_arch)          ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
 	bfd_m32c_arch)		ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 2919271..a9c65f3 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -26,6 +26,7 @@
 #define ARCH_alpha
 #define ARCH_arc
 #define ARCH_arm
+#define ARCH_epiphany
 #define ARCH_avr
 #define ARCH_bfin
 #define ARCH_cr16
@@ -224,6 +225,11 @@ disassembler (abfd)
       disassemble = print_insn_ip2k;
       break;
 #endif
+#ifdef ARCH_epiphany
+    case bfd_arch_epiphany:
+      disassemble = print_insn_epiphany;
+      break;
+#endif
 #ifdef ARCH_fr30
     case bfd_arch_fr30:
       disassemble = print_insn_fr30;
diff --git a/opcodes/epiphany-asm.c b/opcodes/epiphany-asm.c
new file mode 100644
index 0000000..31ceb3e
--- /dev/null
+++ b/opcodes/epiphany-asm.c
@@ -0,0 +1,863 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+
+/* -- assembler routines inserted here.  */
+
+/* -- asm.c */
+const char *
+parse_shortregs (CGEN_CPU_DESC cd,
+		 const char ** strp,
+		 CGEN_KEYWORD * keywords,
+		 long * regno)
+{
+  const char * errmsg;
+
+  /* Parse register.  */
+  errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
+
+  if (errmsg)
+    return errmsg;
+
+  if (*regno > 7)
+    errmsg = _("register unavailable for short instructions");
+
+  return errmsg;
+}
+
+static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
+					long *);
+
+static const char *
+parse_uimm_not_reg (CGEN_CPU_DESC cd,
+		    const char ** strp,
+		    int opindex,
+		    unsigned long * valuep)
+{
+  long * svalp = (void *) valuep;
+  return parse_simm_not_reg (cd, strp, opindex, svalp);
+}
+
+/* Handle simm3/simm11/imm3/imm12.  */
+
+static const char *
+parse_simm_not_reg (CGEN_CPU_DESC cd,
+		   const char ** strp,
+		   int opindex,
+		   long * valuep)
+{
+  const char * errmsg;
+
+  int   sign = 0;
+  int   bits = 0;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_SIMM3:
+      sign = 1; bits = 3; break;
+    case EPIPHANY_OPERAND_SIMM11:
+      sign = 1; bits = 11; break;
+    case EPIPHANY_OPERAND_DISP3:
+      sign = 0; bits = 3; break;
+    case EPIPHANY_OPERAND_DISP11:
+      /* Load/store displacement is a sign-magnitude 12 bit value.  */
+      sign = 0; bits = 11; break;
+    }
+
+  /* First try to parse as a register name and reject the operand.  */
+  errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
+  if (!errmsg)
+    return _("register name used as immediate value");
+
+  errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
+	    : cgen_parse_unsigned_integer (cd, strp, opindex,
+					  (unsigned long *) valuep));
+  if (errmsg)
+    return errmsg;
+
+  if (sign)
+    errmsg = cgen_validate_signed_integer (*valuep,
+					  -((1L << bits) - 1), (1 << (bits - 1)) - 1);
+  else
+    errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
+
+  return errmsg;
+}
+
+static const char *
+parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		 const char ** strp,
+		 int opindex ATTRIBUTE_UNUSED,
+		 bfd_vma * valuep)
+{
+  if (**strp == '#')
+    ++*strp;			/* Skip leading hashes.  */
+
+  if (**strp == '-')
+    {
+      *valuep = 1;
+      ++*strp;
+    }
+  else if (**strp == '+')
+    {
+      *valuep = 0;
+      ++*strp;
+    }
+  else
+    *valuep = 0;
+
+  return NULL;
+}
+
+static const char *
+parse_imm8 (CGEN_CPU_DESC cd,
+	    const char ** strp,
+	    int opindex,
+	    bfd_reloc_code_real_type code,
+	    enum cgen_parse_operand_result * result_type,
+	    bfd_vma * valuep)
+{
+  const char * errmsg;
+  enum cgen_parse_operand_result rt;
+  long dummyval;
+
+  if (!result_type)
+    result_type = &rt;
+
+  code = BFD_RELOC_NONE;
+
+  if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
+      || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+			      &dummyval))
+    /* Don't treat "mov ip,ip" as a move-immediate.  */
+    return _("register source in immediate move");
+
+  errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
+  if (errmsg)
+    return errmsg;
+
+  if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+    errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
+  else
+    errmsg = _("byte relocation unsupported");
+
+  *valuep &= 0xff;
+  return errmsg;
+}
+
+static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
+
+static const char *
+parse_imm16 (CGEN_CPU_DESC cd,
+	     const char ** strp,
+	     int opindex,
+	     bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
+	     enum cgen_parse_operand_result * result_type,
+	     bfd_vma * valuep)
+{
+  const char * errmsg;
+  enum cgen_parse_operand_result rt;
+  long dummyval;
+
+  if (!result_type)
+    result_type = &rt;
+
+  if (strncasecmp (*strp, "%high(", 6) == 0)
+    {
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
+				   result_type, valuep);
+      if (**strp != ')')
+	return MISSING_CLOSE_PARENTHESIS;
+      ++*strp;
+      *valuep >>= 16;
+    }
+  else if (strncasecmp (*strp, "%low(", 5) == 0)
+    {
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
+				   result_type, valuep);
+      if (**strp != ')')
+	return MISSING_CLOSE_PARENTHESIS;
+      ++*strp;
+    }
+  else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
+				&dummyval)
+	   || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
+				   &dummyval))
+    /* Don't treat "mov ip,ip" as a move-immediate.  */
+    return _("register source in immediate move");
+  else
+    errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+				 result_type, valuep);
+
+  if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+    errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
+
+  *valuep &= 0xffff;
+  return errmsg;
+}
+
+const char *
+parse_branch_addr (CGEN_CPU_DESC cd,
+		   const char ** strp,
+		   int opindex,
+		   int opinfo ATTRIBUTE_UNUSED,
+		   enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
+		   unsigned long * valuep ATTRIBUTE_UNUSED)
+{
+  const char * errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_SIMM24:
+      code = BFD_RELOC_EPIPHANY_SIMM24;
+      break;
+
+    case EPIPHANY_OPERAND_SIMM8:
+      code = BFD_RELOC_EPIPHANY_SIMM8;
+      break;
+
+    default:
+      errmsg = _("ABORT: unknown operand");
+      return errmsg;
+    }
+
+  errmsg = cgen_parse_address (cd, strp, opindex, code,
+			       &result_type, &value);
+  if (errmsg == NULL)
+    {
+      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  /* Act as if we had done a PC-relative branch, ala .+num.  */
+	  char buf[20];
+	  const char * bufp = (const char *) buf;
+
+	  sprintf (buf, ".+%ld", value);
+	  errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
+				       &value);
+	}
+
+      if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
+	{
+	  /* This will happen for things like (s2-s1) where s2 and s1
+	     are labels.  */
+	  /* Nothing further to be done.  */
+	}
+      else
+	errmsg = _("Not a pc-relative address.");
+    }
+  return errmsg;
+}
+
+/* -- dis.c */
+
+const char * epiphany_cgen_parse_operand
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  */
+
+const char *
+epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
+{
+  const char * errmsg = NULL;
+  /* Used by scalar operands that still need to be parsed.  */
+  long junk ATTRIBUTE_UNUSED;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DIRECTION, (unsigned long *) (& fields->f_addsubx));
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_DISP11, (unsigned long *) (& fields->f_disp11));
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_DISP3, (unsigned long *) (& fields->f_disp3));
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DPMI, (unsigned long *) (& fields->f_subd));
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      {
+        bfd_vma value = 0;
+        errmsg = parse_imm16 (cd, strp, EPIPHANY_OPERAND_IMM16, 0, NULL,  & value);
+        fields->f_imm16 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      {
+        bfd_vma value = 0;
+        errmsg = parse_imm8 (cd, strp, EPIPHANY_OPERAND_IMM8, 0, NULL,  & value);
+        fields->f_imm8 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_RD :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
+      break;
+    case EPIPHANY_OPERAND_RM :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
+      break;
+    case EPIPHANY_OPERAND_RN :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
+      break;
+    case EPIPHANY_OPERAND_SD :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd);
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd6);
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sd6);
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sd6);
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sd6);
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift));
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM11, (long *) (& fields->f_sdisp11));
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      {
+        bfd_vma value = 0;
+        errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM24, 0, NULL,  & value);
+        fields->f_simm24 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM3, (long *) (& fields->f_sdisp3));
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      {
+        bfd_vma value = 0;
+        errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM8, 0, NULL,  & value);
+        fields->f_simm8 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_SN :
+      errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn);
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn6);
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sn6);
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sn6);
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sn6);
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_SWI_NUM, (unsigned long *) (& fields->f_trap_num));
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_TRAPNUM6, (unsigned long *) (& fields->f_trap_num));
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * const epiphany_cgen_parse_handlers[] = 
+{
+  parse_insn_normal,
+};
+
+void
+epiphany_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+  epiphany_cgen_init_opcode_table (cd);
+  epiphany_cgen_init_ibld_table (cd);
+  cd->parse_handlers = & epiphany_cgen_parse_handlers[0];
+  cd->parse_operand = epiphany_cgen_parse_operand;
+#ifdef CGEN_ASM_INIT_HOOK
+CGEN_ASM_INIT_HOOK
+#endif
+}
+
+
+
+/* Regex construction routine.
+
+   This translates an opcode syntax string into a regex string,
+   by replacing any non-character syntax element (such as an
+   opcode) with the pattern '.*'
+
+   It then compiles the regex and stores it in the opcode, for
+   later use by epiphany_cgen_assemble_insn
+
+   Returns NULL for success, an error message for failure.  */
+
+char * 
+epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
+{  
+  CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+  const char *mnem = CGEN_INSN_MNEMONIC (insn);
+  char rxbuf[CGEN_MAX_RX_ELEMENTS];
+  char *rx = rxbuf;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+  int reg_err;
+
+  syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+  /* Mnemonics come first in the syntax string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    return _("missing mnemonic in syntax string");
+  ++syn;
+
+  /* Generate a case sensitive regular expression that emulates case
+     insensitive matching in the "C" locale.  We cannot generate a case
+     insensitive regular expression because in Turkish locales, 'i' and 'I'
+     are not equal modulo case conversion.  */
+
+  /* Copy the literal mnemonic out of the insn.  */
+  for (; *mnem; mnem++)
+    {
+      char c = *mnem;
+
+      if (ISALPHA (c))
+	{
+	  *rx++ = '[';
+	  *rx++ = TOLOWER (c);
+	  *rx++ = TOUPPER (c);
+	  *rx++ = ']';
+	}
+      else
+	*rx++ = c;
+    }
+
+  /* Copy any remaining literals from the syntax string into the rx.  */
+  for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+    {
+      if (CGEN_SYNTAX_CHAR_P (* syn)) 
+	{
+	  char c = CGEN_SYNTAX_CHAR (* syn);
+
+	  switch (c) 
+	    {
+	      /* Escape any regex metacharacters in the syntax.  */
+	    case '.': case '[': case '\\': 
+	    case '*': case '^': case '$': 
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+	    case '?': case '{': case '}': 
+	    case '(': case ')': case '*':
+	    case '|': case '+': case ']':
+#endif
+	      *rx++ = '\\';
+	      *rx++ = c;
+	      break;
+
+	    default:
+	      if (ISALPHA (c))
+		{
+		  *rx++ = '[';
+		  *rx++ = TOLOWER (c);
+		  *rx++ = TOUPPER (c);
+		  *rx++ = ']';
+		}
+	      else
+		*rx++ = c;
+	      break;
+	    }
+	}
+      else
+	{
+	  /* Replace non-syntax fields with globs.  */
+	  *rx++ = '.';
+	  *rx++ = '*';
+	}
+    }
+
+  /* Trailing whitespace ok.  */
+  * rx++ = '['; 
+  * rx++ = ' '; 
+  * rx++ = '\t'; 
+  * rx++ = ']'; 
+  * rx++ = '*'; 
+
+  /* But anchor it after that.  */
+  * rx++ = '$'; 
+  * rx = '\0';
+
+  CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+  reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+  if (reg_err == 0) 
+    return NULL;
+  else
+    {
+      static char msg[80];
+
+      regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+      regfree ((regex_t *) CGEN_INSN_RX (insn));
+      free (CGEN_INSN_RX (insn));
+      (CGEN_INSN_RX (insn)) = NULL;
+      return msg;
+    }
+}
+
+
+/* Default insn parser.
+
+   The syntax string is scanned and operands are parsed and stored in FIELDS.
+   Relocs are queued as we go via other callbacks.
+
+   ??? Note that this is currently an all-or-nothing parser.  If we fail to
+   parse the instruction, we return 0 and the caller will start over from
+   the beginning.  Backtracking will be necessary in parsing subexpressions,
+   but that can be handled there.  Not handling backtracking here may get
+   expensive in the case of the m68k.  Deal with later.
+
+   Returns NULL for success, an error message for failure.  */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
+{
+  /* ??? Runtime added insns not handled yet.  */
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const char *str = *strp;
+  const char *errmsg;
+  const char *p;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+  /* FIXME: wip */
+  int past_opcode_p;
+#endif
+
+  /* For now we assume the mnemonic is first (there are no leading operands).
+     We can parse it without needing to set up operand parsing.
+     GAS's input scrubber will ensure mnemonics are lowercase, but we may
+     not be called from GAS.  */
+  p = CGEN_INSN_MNEMONIC (insn);
+  while (*p && TOLOWER (*p) == TOLOWER (*str))
+    ++p, ++str;
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && ! ISSPACE (* str))
+    return _("unrecognized instruction");
+#endif
+
+  CGEN_INIT_PARSE (cd);
+  cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+  past_opcode_p = 0;
+#endif
+
+  /* We don't check for (*str != '\0') here because we want to parse
+     any trailing fake arguments in the syntax string.  */
+  syn = CGEN_SYNTAX_STRING (syntax);
+
+  /* Mnemonics come first for now, ensure valid string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    abort ();
+
+  ++syn;
+
+  while (* syn != 0)
+    {
+      /* Non operand chars must match exactly.  */
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
+	  if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+	    {
+#ifdef CGEN_MNEMONIC_OPERANDS
+	      if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+		past_opcode_p = 1;
+#endif
+	      ++ syn;
+	      ++ str;
+	    }
+	  else if (*str)
+	    {
+	      /* Syntax char didn't match.  Can't be this insn.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+		       CGEN_SYNTAX_CHAR(*syn), *str);
+	      return msg;
+	    }
+	  else
+	    {
+	      /* Ran out of input.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+		       CGEN_SYNTAX_CHAR(*syn));
+	      return msg;
+	    }
+	  continue;
+	}
+
+#ifdef CGEN_MNEMONIC_OPERANDS
+      (void) past_opcode_p;
+#endif
+      /* We have an operand of some sort.  */
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
+      if (errmsg)
+	return errmsg;
+
+      /* Done with this operand, continue with next one.  */
+      ++ syn;
+    }
+
+  /* If we're at the end of the syntax string, we're done.  */
+  if (* syn == 0)
+    {
+      /* FIXME: For the moment we assume a valid `str' can only contain
+	 blanks now.  IE: We needn't try again with a longer version of
+	 the insn and it is assumed that longer versions of insns appear
+	 before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+      while (ISSPACE (* str))
+	++ str;
+
+      if (* str != '\0')
+	return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+      return NULL;
+    }
+
+  /* We couldn't parse it.  */
+  return _("unrecognized instruction");
+}
+
+/* Main entry point.
+   This routine is called for each instruction to be assembled.
+   STR points to the insn to be assembled.
+   We assume all necessary tables have been initialized.
+   The assembled instruction, less any fixups, is stored in BUF.
+   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+   still needs to be converted to target byte order, otherwise BUF is an array
+   of bytes in target byte order.
+   The result is a pointer to the insn's entry in the opcode table,
+   or NULL if an error occured (an error message will have already been
+   printed).
+
+   Note that when processing (non-alias) macro-insns,
+   this function recurses.
+
+   ??? It's possible to make this cpu-independent.
+   One would have to deal with a few minor things.
+   At this point in time doing so would be more of a curiosity than useful
+   [for example this file isn't _that_ big], but keeping the possibility in
+   mind helps keep the design clean.  */
+
+const CGEN_INSN *
+epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *parse_errmsg = NULL;
+  const char *insert_errmsg = NULL;
+  int recognized_mnemonic = 0;
+
+  /* Skip leading white space.  */
+  while (ISSPACE (* str))
+    ++ str;
+
+  /* The instructions are stored in hashed lists.
+     Get the first in the list.  */
+  ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+  /* Keep looking until we find a match.  */
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not usually needed as unsupported opcodes
+	 shouldn't be in the hash lists.  */
+      /* Is this insn supported by the selected cpu?  */
+      if (! epiphany_cgen_insn_supported (cd, insn))
+	continue;
+#endif
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
+	 chosen immediately.  Instead, it is used during assembler/linker
+	 relaxation if possible.  */
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+	continue;
+
+      str = start;
+
+      /* Skip this insn if str doesn't look right lexically.  */
+      if (CGEN_INSN_RX (insn) != NULL &&
+	  regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	continue;
+
+      /* Allow parse/insert handlers to obtain length of insn.  */
+      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+      parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+      if (parse_errmsg != NULL)
+	continue;
+
+      /* ??? 0 is passed for `pc'.  */
+      insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+						 (bfd_vma) 0);
+      if (insert_errmsg != NULL)
+        continue;
+
+      /* It is up to the caller to actually output the insn and any
+         queued relocs.  */
+      return insn;
+    }
+
+  {
+    static char errbuf[150];
+    const char *tmp_errmsg;
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+#define be_verbose 1
+#else
+#define be_verbose 0
+#endif
+
+    if (be_verbose)
+      {
+	/* If requesting verbose error messages, use insert_errmsg.
+	   Failing that, use parse_errmsg.  */
+	tmp_errmsg = (insert_errmsg ? insert_errmsg :
+		      parse_errmsg ? parse_errmsg :
+		      recognized_mnemonic ?
+		      _("unrecognized form of instruction") :
+		      _("unrecognized instruction"));
+
+	if (strlen (start) > 50)
+	  /* xgettext:c-format */
+	  sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+	else 
+	  /* xgettext:c-format */
+	  sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+      }
+    else
+      {
+	if (strlen (start) > 50)
+	  /* xgettext:c-format */
+	  sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+	else 
+	  /* xgettext:c-format */
+	  sprintf (errbuf, _("bad instruction `%.50s'"), start);
+      }
+      
+    *errmsg = errbuf;
+    return NULL;
+  }
+}
diff --git a/opcodes/epiphany-desc.c b/opcodes/epiphany-desc.c
new file mode 100644
index 0000000..271f8a7
--- /dev/null
+++ b/opcodes/epiphany-desc.c
@@ -0,0 +1,2271 @@
+/* CPU data for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+  { "#f", 0 },
+  { "#t", 1 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+  { "base", MACH_BASE },
+  { "epiphany32", MACH_EPIPHANY32 },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+  { "epiphany", ISA_EPIPHANY },
+  { "max", ISA_MAX },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "RESERVED", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "RELOC", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "PC", &bool_attr[0], &bool_attr[0] },
+  { "PROFILE", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+  { "RELOC", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "ALIAS", &bool_attr[0], &bool_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
+  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+  { "PBB", &bool_attr[0], &bool_attr[0] },
+  { "SHORT-INSN", &bool_attr[0], &bool_attr[0] },
+  { "IMM3", &bool_attr[0], &bool_attr[0] },
+  { "IMM8", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+/* Instruction set variants.  */
+
+static const CGEN_ISA epiphany_cgen_isa_table[] = {
+  { "epiphany", 32, 32, 16, 32 },
+  { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants.  */
+
+static const CGEN_MACH epiphany_cgen_mach_table[] = {
+  { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 },
+  { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
+{
+  { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "ip", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "r60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "r61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "r62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "r63", 63, {0, {{{0, 0}}}}, 0, 0 },
+  { "a1", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "a2", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "a3", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "a4", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "v1", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "v2", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "v3", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "v4", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "v8", 11, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_gr_names =
+{
+  & epiphany_cgen_opval_gr_names_entries[0],
+  82,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] =
+{
+  { "config", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "status", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "pc", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "debug", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "iab", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "lc", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "ls", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "iret", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "imask", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_cr_names =
+{
+  & epiphany_cgen_opval_cr_names_entries[0],
+  17,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] =
+{
+  { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crdma_names =
+{
+  & epiphany_cgen_opval_crdma_names_entries[0],
+  16,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] =
+{
+  { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crmem_names =
+{
+  & epiphany_cgen_opval_crmem_names_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] =
+{
+  { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD epiphany_cgen_opval_crmesh_names =
+{
+  & epiphany_cgen_opval_crmesh_names_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+
+/* The hardware table.  */
+
+#define A(a) (1 << CGEN_HW_##a)
+
+const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
+{
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table.  */
+
+#define A(a) (1 << CGEN_IFLD_##a)
+
+const CGEN_IFLD epiphany_cgen_ifld_table[] =
+{
+  { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
+    { 0, { (const PTR) 0 } }
+};
+
+/* The operand table.  */
+
+#define A(a) (1 << CGEN_OPERAND_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+
+const CGEN_OPERAND epiphany_cgen_operand_table[] =
+{
+/* pc: program counter */
+  { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* zbit: integer zero bit */
+  { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* nbit: integer neg bit */
+  { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* cbit: integer carry bit */
+  { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* vbit: integer overflow bit */
+  { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bzbit: floating point zero bit */
+  { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bnbit: floating point neg bit */
+  { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bvbit: floating point ovfl bit */
+  { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bcbit: floating point carry bit */
+  { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bubit: floating point underfl bit */
+  { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bibit: floating point invalid bit */
+  { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* vsbit: integer overflow sticky */
+  { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bvsbit: floating point overflow sticky */
+  { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bisbit: floating point invalid sticky */
+  { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* busbit: floating point underflow sticky */
+  { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* expcause0bit: exceprion cause bit0 */
+  { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* expcause1bit: exceprion cause bit1 */
+  { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* expcause2bit: external load stalled bit */
+  { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* extFstallbit: external fetch stalled bit */
+  { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* trmbit: 0=round to nearest, 1=trunacte selct bit */
+  { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* invExcEnbit: invalid exception enable bit */
+  { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* ovfExcEnbit: overflow exception enable bit */
+  { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* unExcEnbit: underflow exception enable bit */
+  { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer0bit0: timer 0 mode selection 0 */
+  { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer0bit1: timer 0 mode selection 1 */
+  { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer0bit2: timer 0 mode selection 2 */
+  { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer0bit3: timer 0 mode selection 3 */
+  { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer1bit0: timer 1 mode selection 0 */
+  { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer1bit1: timer 1 mode selection 1 */
+  { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer1bit2: timer 1 mode selection 2 */
+  { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* timer1bit3: timer 1 mode selection 3 */
+  { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* mbkptEnbit: multicore bkpt enable */
+  { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* clockGateEnbit: clock gate enable enable */
+  { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* arithmetic-modebit0: arithmetic mode bit0 */
+  { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* arithmetic-modebit1: arithmetic mode bit1 */
+  { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* arithmetic-modebit2: arithmetic mode bit2 */
+  { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit12: core config bit 12 */
+  { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit13: core config bit 13 */
+  { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit14: core config bit 14 */
+  { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit15: core config bit 15 */
+  { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit16: core config bit 16 */
+  { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit20: core config bit 20 */
+  { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit21: core config bit 21 */
+  { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit24: core config bit 24 */
+  { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit25: core config bit 25 */
+  { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit26: core config bit 26 */
+  { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit27: core config bit 27 */
+  { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit28: core config bit 28 */
+  { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit29: core config bit 29 */
+  { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit30: core config bit 30 */
+  { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* coreCfgResBit31: core config bit 31 */
+  { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* gidisablebit: global interrupt disable bit */
+  { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* kmbit: kernel mode bit */
+  { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* caibit: core actibe indicator bit */
+  { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sflagbit: sflag bit */
+  { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* memaddr: memory effective address */
+  { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* simm24: branch address pc-relative */
+  { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } }, 
+    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* simm8: branch address pc-relative */
+  { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } }, 
+    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* rd: destination register */
+  { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* rn: source register */
+  { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* rm: source register */
+  { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* frd: fp destination register */
+  { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* frn: fp source register */
+  { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* frm: fp source register */
+  { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* rd6: destination register */
+  { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* rn6: source register */
+  { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* rm6: source register */
+  { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* frd6: fp destination register */
+  { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* frn6: fp source register */
+  { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* frm6: fp source register */
+  { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
+    { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sd: special destination */
+  { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sn: special source */
+  { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sd6: special destination register */
+  { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sn6: special source register */
+  { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sddma: dma register */
+  { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sndma: dma register */
+  { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sdmem: mem register */
+  { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* snmem: mem register */
+  { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sdmesh: mesh register */
+  { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* snmesh: mesh register */
+  { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
+    { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* simm3: signed 3-bit literal */
+  { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } }, 
+    { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* simm11: signed 11-bit literal */
+  { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
+    { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } }, 
+    { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* disp3: short data displacement */
+  { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* trapnum6: parameter for swi or trap */
+  { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* swi_num: unsigned 6-bit swi# */
+  { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* disp11: sign-magnitude data displacement */
+  { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
+    { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* shift: immediate shift amount */
+  { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* imm16: 16-bit unsigned literal */
+  { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
+    { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } }, 
+    { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* imm8: 8-bit unsigned literal */
+  { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } }, 
+    { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* direction: +/- indexing */
+  { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* dpmi: +/- magnitude immediate displacement */
+  { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
+    { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sentinel */
+  { 0, 0, 0, 0, 0,
+    { 0, { (const PTR) 0 } },
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction table.  */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#define A(a) (1 << CGEN_INSN_##a)
+
+static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+/* beq.s $simm8 */
+  {
+    EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* beq.l $simm24 */
+  {
+    EPIPHANY_INSN_BEQ, "beq", "beq.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bne.s $simm8 */
+  {
+    EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bne.l $simm24 */
+  {
+    EPIPHANY_INSN_BNE, "bne", "bne.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgtu.s $simm8 */
+  {
+    EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgtu.l $simm24 */
+  {
+    EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgteu.s $simm8 */
+  {
+    EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgteu.l $simm24 */
+  {
+    EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blteu.s $simm8 */
+  {
+    EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blteu.l $simm24 */
+  {
+    EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bltu.s $simm8 */
+  {
+    EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bltu.l $simm24 */
+  {
+    EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgt.s $simm8 */
+  {
+    EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgt.l $simm24 */
+  {
+    EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgte.s $simm8 */
+  {
+    EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgte.l $simm24 */
+  {
+    EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blt.s $simm8 */
+  {
+    EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blt.l $simm24 */
+  {
+    EPIPHANY_INSN_BLT, "blt", "blt.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blte.s $simm8 */
+  {
+    EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blte.l $simm24 */
+  {
+    EPIPHANY_INSN_BLTE, "blte", "blte.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbeq.s $simm8 */
+  {
+    EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbeq.l $simm24 */
+  {
+    EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbne.s $simm8 */
+  {
+    EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbne.l $simm24 */
+  {
+    EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblt.s $simm8 */
+  {
+    EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblt.l $simm24 */
+  {
+    EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblte.s $simm8 */
+  {
+    EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblte.l $simm24 */
+  {
+    EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* b.s $simm8 */
+  {
+    EPIPHANY_INSN_B16, "b16", "b.s", 16,
+    { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* b.l $simm24 */
+  {
+    EPIPHANY_INSN_B, "b", "b.l", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bl.s $simm8 */
+  {
+    EPIPHANY_INSN_BL16, "bl16", "bl.s", 16,
+    { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bl.l $simm24 */
+  {
+    EPIPHANY_INSN_BL, "bl", "bl.l", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* jr $rn */
+  {
+    EPIPHANY_INSN_JR16, "jr16", "jr", 16,
+    { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* rts */
+  {
+    -1, "rts", "rts", 32,
+    { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* jr $rn6 */
+  {
+    EPIPHANY_INSN_JR, "jr", "jr", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* jalr $rn */
+  {
+    EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16,
+    { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* jalr $rn6 */
+  {
+    EPIPHANY_INSN_JALR, "jalr", "jalr", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testsetb $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testseth $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testset $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_STRBX, "strbx", "strb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_STRBP, "strbp", "strb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_STRBD, "strbd", "strb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_STRHX, "strhx", "strh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_STRHP, "strhp", "strh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_STRHD, "strhd", "strh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_STRX16, "strx16", "str", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_STRX, "strx", "str", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_STRP16, "strp16", "str", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_STRP, "strp", "str", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_STRD16, "strd16", "str", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_STRD, "strd", "str", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_STRDPM, "strdpm", "str", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd,[$rn,$rm] */
+  {
+    EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd6,[$rn6,$direction$rm6] */
+  {
+    EPIPHANY_INSN_STRDX, "strdx", "strd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd,[$rn],$rm */
+  {
+    EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd6,[$rn6],$direction$rm6 */
+  {
+    EPIPHANY_INSN_STRDP, "strdp", "strd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd,[$rn,$disp3] */
+  {
+    EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd6,[$rn6,$dpmi$disp11] */
+  {
+    EPIPHANY_INSN_STRDD, "strdd", "strd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd6,[$rn6],$dpmi$disp11 */
+  {
+    EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* moveq $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* moveq $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movne $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movne $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgtu $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgtu $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgteu $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgteu $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlteu $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlteu $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movltu $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movltu $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgt $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgt $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgte $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgte $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlt $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlt $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlte $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlte $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbeq $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbeq $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbne $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbne $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblt $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblt $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblte $rd,$rn */
+  {
+    EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblte $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts $sn,$rd */
+  {
+    EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts $sn6,$rd6 */
+  {
+    EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts $sndma,$rd6 */
+  {
+    EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts $snmem,$rd6 */
+  {
+    EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts $snmesh,$rd6 */
+  {
+    EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs $rd,$sn */
+  {
+    EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs $rd6,$sn6 */
+  {
+    EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs $rd6,$sndma */
+  {
+    EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs $rd6,$snmem */
+  {
+    EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs $rd6,$snmesh */
+  {
+    EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* nop */
+  {
+    EPIPHANY_INSN_NOP, "nop", "nop", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* snop */
+  {
+    EPIPHANY_INSN_SNOP, "snop", "snop", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* unimpl */
+  {
+    EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* idle */
+  {
+    EPIPHANY_INSN_IDLE, "idle", "idle", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bkpt */
+  {
+    EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16,
+    { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mbkpt */
+  {
+    EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16,
+    { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* rti */
+  {
+    EPIPHANY_INSN_RTI, "rti", "rti", 16,
+    { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* wand */
+  {
+    EPIPHANY_INSN_WAND, "wand", "wand", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sync */
+  {
+    EPIPHANY_INSN_SYNC, "sync", "sync", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* gie */
+  {
+    EPIPHANY_INSN_GIEN, "gien", "gie", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* gid */
+  {
+    EPIPHANY_INSN_GIDIS, "gidis", "gid", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* swi $swi_num */
+  {
+    EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16,
+    { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* swi */
+  {
+    -1, "swi", "swi", 16,
+    { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* trap $trapnum6 */
+  {
+    EPIPHANY_INSN_TRAP16, "trap16", "trap", 16,
+    { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_ADD16, "add16", "add", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_ADD, "add", "add", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_SUB16, "sub16", "sub", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_SUB, "sub", "sub", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* and $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_AND16, "and16", "and", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* and $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_AND, "and", "and", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* orr $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_ORR16, "orr16", "orr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* orr $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_ORR, "orr", "orr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* eor $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_EOR16, "eor16", "eor", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* eor $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_EOR, "eor", "eor", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add.s $rd,$rn,$simm3 */
+  {
+    EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add.l $rd6,$rn6,$simm11 */
+  {
+    EPIPHANY_INSN_ADDI, "addi", "add.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub.s $rd,$rn,$simm3 */
+  {
+    EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub.l $rd6,$rn6,$simm11 */
+  {
+    EPIPHANY_INSN_SUBI, "subi", "sub.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_ASR16, "asr16", "asr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_ASR, "asr", "asr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_LSR, "lsr", "lsr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_LSL, "lsl", "lsl", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr $rd,$rn,$shift */
+  {
+    EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr $rd6,$rn6,$shift */
+  {
+    EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl $rd,$rn,$shift */
+  {
+    EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl $rd6,$rn6,$shift */
+  {
+    EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr $rd,$rn,$shift */
+  {
+    EPIPHANY_INSN_ASRI16, "asri16", "asr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr $rd6,$rn6,$shift */
+  {
+    EPIPHANY_INSN_ASRI32, "asri32", "asr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bitr $rd,$rn */
+  {
+    EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bitr $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_BITR, "bitr", "bitr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fext $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_FEXT, "fext", "fext", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fdep $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_FDEP, "fdep", "fdep", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lfsr $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov.b $rd,$imm8 */
+  {
+    EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov.l $rd6,$imm16 */
+  {
+    EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movt $rd6,$imm16 */
+  {
+    EPIPHANY_INSN_MOVT, "movt", "movt", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fadd $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fadd $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fsub $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fsub $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmul $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmul $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmadd $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmadd $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmsub $rd,$rn,$rm */
+  {
+    EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmsub $rd6,$rn6,$rm6 */
+  {
+    EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fabs rd,rn */
+  {
+    EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fabs $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* float $rd,$rn */
+  {
+    EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* float $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fix $rd,$rn */
+  {
+    EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16,
+    { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fix $rd6,$rn6 */
+  {
+    EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* frecip $frd6,$frn6 */
+  {
+    EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fsqrt $frd6,$frn6 */
+  {
+    EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
+  },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call.  */
+
+static void
+init_tables (void)
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name.  */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+  while (table->name)
+    {
+      if (strcmp (name, table->bfd_name) == 0)
+	return table;
+      ++table;
+    }
+  abort ();
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0];
+  /* MAX_HW is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_HW_ENTRY **selected =
+    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+  cd->hw_table.init_entries = init;
+  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+  /* ??? For now we just use machs to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->hw_table.entries = selected;
+  cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+  cd->ifld_table = & epiphany_cgen_ifld_table[0];
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0];
+  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+  cd->operand_table.init_entries = init;
+  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  /* ??? For now we just use mach to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->operand_table.entries = selected;
+  cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.
+   ??? This could leave out insns not supported by the specified mach/isa,
+   but that would cause errors like "foo only supported by bar" to become
+   "unknown insn", so for now we include all insns and require the app to
+   do the checking later.
+   ??? On the other hand, parsing of such insns may require their hardware or
+   operand elements to be in the table [which they mightn't be].  */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0];
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+  for (i = 0; i < MAX_INSNS; ++i)
+    insns[i].base = &ib[i];
+  cd->insn_table.init_entries = insns;
+  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of epiphany_cgen_cpu_open to rebuild the tables.  */
+
+static void
+epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  CGEN_BITSET *isas = cd->isas;
+  unsigned int machs = cd->machs;
+
+  cd->int_insn_p = CGEN_INT_INSN_P;
+
+  /* Data derived from the isa spec.  */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+  cd->default_insn_bitsize = UNSET;
+  cd->base_insn_bitsize = UNSET;
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
+  cd->max_insn_bitsize = 0;
+  for (i = 0; i < MAX_ISAS; ++i)
+    if (cgen_bitset_contains (isas, i))
+      {
+	const CGEN_ISA *isa = & epiphany_cgen_isa_table[i];
+
+	/* Default insn sizes of all selected isas must be
+	   equal or we set the result to 0, meaning "unknown".  */
+	if (cd->default_insn_bitsize == UNSET)
+	  cd->default_insn_bitsize = isa->default_insn_bitsize;
+	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Base insn sizes of all selected isas must be equal
+	   or we set the result to 0, meaning "unknown".  */
+	if (cd->base_insn_bitsize == UNSET)
+	  cd->base_insn_bitsize = isa->base_insn_bitsize;
+	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Set min,max insn sizes.  */
+	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+	  cd->min_insn_bitsize = isa->min_insn_bitsize;
+	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+	  cd->max_insn_bitsize = isa->max_insn_bitsize;
+      }
+
+  /* Data derived from the mach spec.  */
+  for (i = 0; i < MAX_MACHS; ++i)
+    if (((1 << i) & machs) != 0)
+      {
+	const CGEN_MACH *mach = & epiphany_cgen_mach_table[i];
+
+	if (mach->insn_chunk_bitsize != 0)
+	{
+	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+	    {
+	      fprintf (stderr, "epiphany_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      abort ();
+	    }
+
+ 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+	}
+      }
+
+  /* Determine which hw elements are used by MACH.  */
+  build_hw_table (cd);
+
+  /* Build the ifield table.  */
+  build_ifield_table (cd);
+
+  /* Determine which operands are used by MACH/ISA.  */
+  build_operand_table (cd);
+
+  /* Build the instruction table.  */
+  build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+   It's much like opening a file, and must be the first function called.
+   The arguments are a set of (type/value) pairs, terminated with
+   CGEN_CPU_OPEN_END.
+
+   Currently supported values:
+   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
+   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
+   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
+   CGEN_CPU_OPEN_END:     terminates arguments
+
+   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+   precluded.  */
+
+CGEN_CPU_DESC
+epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+  static int init_p;
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
+  unsigned int machs = 0; /* 0 = "unspecified" */
+  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+  va_list ap;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (cd, 0, sizeof (*cd));
+
+  va_start (ap, arg_type);
+  while (arg_type != CGEN_CPU_OPEN_END)
+    {
+      switch (arg_type)
+	{
+	case CGEN_CPU_OPEN_ISAS :
+	  isas = va_arg (ap, CGEN_BITSET *);
+	  break;
+	case CGEN_CPU_OPEN_MACHS :
+	  machs = va_arg (ap, unsigned int);
+	  break;
+	case CGEN_CPU_OPEN_BFDMACH :
+	  {
+	    const char *name = va_arg (ap, const char *);
+	    const CGEN_MACH *mach =
+	      lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name);
+
+	    machs |= 1 << mach->num;
+	    break;
+	  }
+	case CGEN_CPU_OPEN_ENDIAN :
+	  endian = va_arg (ap, enum cgen_endian);
+	  break;
+	default :
+	  fprintf (stderr, "epiphany_cgen_cpu_open: unsupported argument `%d'\n",
+		   arg_type);
+	  abort (); /* ??? return NULL? */
+	}
+      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+    }
+  va_end (ap);
+
+  /* Mach unspecified means "all".  */
+  if (machs == 0)
+    machs = (1 << MAX_MACHS) - 1;
+  /* Base mach is always selected.  */
+  machs |= 1;
+  if (endian == CGEN_ENDIAN_UNKNOWN)
+    {
+      /* ??? If target has only one, could have a default.  */
+      fprintf (stderr, "epiphany_cgen_cpu_open: no endianness specified\n");
+      abort ();
+    }
+
+  cd->isas = cgen_bitset_copy (isas);
+  cd->machs = machs;
+  cd->endian = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  cd->insn_endian = endian;
+
+  /* Table (re)builder.  */
+  cd->rebuild_tables = epiphany_cgen_rebuild_tables;
+  epiphany_cgen_rebuild_tables (cd);
+
+  /* Default to not allowing signed overflow.  */
+  cd->signed_overflow_ok_p = 0;
+  
+  return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+   MACH_NAME is the bfd name of the mach.  */
+
+CGEN_CPU_DESC
+epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+  return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+			       CGEN_CPU_OPEN_ENDIAN, endian,
+			       CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+   ??? This can live in a machine independent file, but there's currently
+   no place to put this file (there's no libcgen).  libopcodes is the wrong
+   place as some simulator ports use this but they don't use libopcodes.  */
+
+void
+epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+  unsigned int i;
+  const CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+  if (cd->insn_table.init_entries)
+    free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+  if (cd->hw_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+  free (cd);
+}
+
diff --git a/opcodes/epiphany-desc.h b/opcodes/epiphany-desc.h
new file mode 100644
index 0000000..430210e
--- /dev/null
+++ b/opcodes/epiphany-desc.h
@@ -0,0 +1,402 @@
+/* CPU data header for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef EPIPHANY_CPU_H
+#define EPIPHANY_CPU_H
+
+#define CGEN_ARCH epiphany
+
+/* Given symbol S, return epiphany_cgen_<S>.  */
+#define CGEN_SYM(s) epiphany##_cgen_##s
+
+
+/* Selected cpu families.  */
+#define HAVE_CPU_EPIPHANYBF
+#define HAVE_CPU_EPIPHANYMF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes).  */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes).  */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction.  */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
+
+/* Enums.  */
+
+/* Enum declaration for opc enums.  */
+typedef enum insn_opc {
+  OP4_BRANCH16, OP4_LDSTR16X, OP4_FLOW16, OP4_IMM16
+ , OP4_LDSTR16D, OP4_LDSTR16P, OP4_LSHIFT16, OP4_DSP16
+ , OP4_BRANCH, OP4_LDSTRX, OP4_ALU16, OP4_IMM32
+ , OP4_LDSTRD, OP4_LDSTRP, OP4_ASHIFT16, OP4_MISC
+} INSN_OPC;
+
+/* Enum declaration for memory access width.  */
+typedef enum insn_wordsize {
+  OPW_BYTE, OPW_SHORT, OPW_WORD, OPW_DOUBLE
+} INSN_WORDSIZE;
+
+/* Enum declaration for memory access direction.  */
+typedef enum insn_memory_access {
+  OP_LOAD, OP_STORE
+} INSN_MEMORY_ACCESS;
+
+/* Enum declaration for trap instruction dispatch code.  */
+typedef enum trap_codes {
+  TRAP_WRITE, TRAP_READ, TRAP_OPEN, TRAP_EXIT
+ , TRAP_PASS, TRAP_FAIL, TRAP_CLOSE, TRAP_OTHER
+} TRAP_CODES;
+
+/* Enum declaration for branch conditions.  */
+typedef enum insn_cond {
+  OPC_EQ, OPC_NE, OPC_GTU, OPC_GTEU
+ , OPC_LTEU, OPC_LTU, OPC_GT, OPC_GTE
+ , OPC_LT, OPC_LTE, OPC_BEQ, OPC_BNE
+ , OPC_BLT, OPC_BLTE, OPC_B, OPC_BL
+} INSN_COND;
+
+/* Enum declaration for binary operator subcodes.  */
+typedef enum insn_bop {
+  OPB_EOR, OPB_ADD, OPB_LSL, OPB_SUB
+ , OPB_LSR, OPB_AND, OPB_ASR, OPB_ORR
+} INSN_BOP;
+
+/* Enum declaration for binary operator subcodes.  */
+typedef enum insn_bopext {
+  OPBE_FEXT, OPBE_FDEP, OPBE_LFSR
+} INSN_BOPEXT;
+
+/* Enum declaration for floating operators.  */
+typedef enum insn_fop {
+  OPF_ADD, OPF_SUB, OPF_MUL, OPF_MADD
+ , OPF_MSUB, OPF_FLOAT, OPF_FIX, OPF_FABS
+} INSN_FOP;
+
+/* Enum declaration for extended floating operators.  */
+typedef enum insn_fopexn {
+  OPF_FRECIP, OPF_FSQRT
+} INSN_FOPEXN;
+
+/* Enum declaration for immediate operators.  */
+typedef enum insn_immop {
+  OPI_ADD = 1, OPI_SUB = 3, OPI_TRAP = 7
+} INSN_IMMOP;
+
+/* Enum declaration for don't cares.  */
+typedef enum insn_dc_25_2 {
+  OPI_25_2_MBZ
+} INSN_DC_25_2;
+
+/* Enum declaration for .  */
+typedef enum gr_names {
+  H_REGISTERS_SB = 9, H_REGISTERS_SL = 10, H_REGISTERS_FP = 11, H_REGISTERS_IP = 12
+ , H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0, H_REGISTERS_R1 = 1
+ , H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4, H_REGISTERS_R5 = 5
+ , H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8, H_REGISTERS_R9 = 9
+ , H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12, H_REGISTERS_R13 = 13
+ , H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16, H_REGISTERS_R17 = 17
+ , H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20, H_REGISTERS_R21 = 21
+ , H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24, H_REGISTERS_R25 = 25
+ , H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28, H_REGISTERS_R29 = 29
+ , H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32, H_REGISTERS_R33 = 33
+ , H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36, H_REGISTERS_R37 = 37
+ , H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40, H_REGISTERS_R41 = 41
+ , H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44, H_REGISTERS_R45 = 45
+ , H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48, H_REGISTERS_R49 = 49
+ , H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52, H_REGISTERS_R53 = 53
+ , H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56, H_REGISTERS_R57 = 57
+ , H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60, H_REGISTERS_R61 = 61
+ , H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0, H_REGISTERS_A2 = 1
+ , H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4, H_REGISTERS_V2 = 5
+ , H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8, H_REGISTERS_V6 = 9
+ , H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11
+} GR_NAMES;
+
+/* Enum declaration for +/- index register.  */
+typedef enum post_index {
+  DIR_POSTINC, DIR_POSTDEC
+} POST_INDEX;
+
+/* Enum declaration for postmodify displacement.  */
+typedef enum disp_post_modify {
+  PMOD_DISP, PMOD_POST
+} DISP_POST_MODIFY;
+
+/* Enum declaration for .  */
+typedef enum cr_names {
+  H_CORE_REGISTERS_CONFIG, H_CORE_REGISTERS_STATUS, H_CORE_REGISTERS_PC, H_CORE_REGISTERS_DEBUG
+ , H_CORE_REGISTERS_IAB, H_CORE_REGISTERS_LC, H_CORE_REGISTERS_LS, H_CORE_REGISTERS_LE
+ , H_CORE_REGISTERS_IRET, H_CORE_REGISTERS_IMASK, H_CORE_REGISTERS_ILAT, H_CORE_REGISTERS_ILATST
+ , H_CORE_REGISTERS_ILATCL, H_CORE_REGISTERS_IPEND, H_CORE_REGISTERS_CTIMER0, H_CORE_REGISTERS_CTIMER1
+ , H_CORE_REGISTERS_HSTATUS
+} CR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum crdma_names {
+  H_COREDMA_REGISTERS_DMA0CONFIG, H_COREDMA_REGISTERS_DMA0STRIDE, H_COREDMA_REGISTERS_DMA0COUNT, H_COREDMA_REGISTERS_DMA0SRCADDR
+ , H_COREDMA_REGISTERS_DMA0DSTADDR, H_COREDMA_REGISTERS_DMA0AUTO0, H_COREDMA_REGISTERS_DMA0AUTO1, H_COREDMA_REGISTERS_DMA0STATUS
+ , H_COREDMA_REGISTERS_DMA1CONFIG, H_COREDMA_REGISTERS_DMA1STRIDE, H_COREDMA_REGISTERS_DMA1COUNT, H_COREDMA_REGISTERS_DMA1SRCADDR
+ , H_COREDMA_REGISTERS_DMA1DSTADDR, H_COREDMA_REGISTERS_DMA1AUTO0, H_COREDMA_REGISTERS_DMA1AUTO1, H_COREDMA_REGISTERS_DMA1STATUS
+} CRDMA_NAMES;
+
+/* Enum declaration for .  */
+typedef enum crmem_names {
+  H_COREMEM_REGISTERS_MEMCONFIG, H_COREMEM_REGISTERS_MEMSTATUS, H_COREMEM_REGISTERS_MEMPROTECT, H_COREMEM_REGISTERS_MEMRESERVE
+} CRMEM_NAMES;
+
+/* Enum declaration for .  */
+typedef enum crmesh_names {
+  H_COREMESH_REGISTERS_MESHCONFIG, H_COREMESH_REGISTERS_COREID, H_COREMESH_REGISTERS_MESHMULTICAST, H_COREMESH_REGISTERS_SWRESET
+} CRMESH_NAMES;
+
+/* Attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_EPIPHANY32, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection.  */
+typedef enum isa_attr {
+  ISA_EPIPHANY, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_ISAS  1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support.  */
+
+/* Ifield attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
+ , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr.  */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0)
+
+/* Enum declaration for epiphany ifield types.  */
+typedef enum ifield_type {
+  EPIPHANY_F_NIL, EPIPHANY_F_ANYOF, EPIPHANY_F_OPC, EPIPHANY_F_OPC_4_1
+ , EPIPHANY_F_OPC_6_3, EPIPHANY_F_OPC_8_5, EPIPHANY_F_OPC_19_4, EPIPHANY_F_CONDCODE
+ , EPIPHANY_F_SECONDARY_CCS, EPIPHANY_F_SHIFT, EPIPHANY_F_WORDSIZE, EPIPHANY_F_STORE
+ , EPIPHANY_F_OPC_8_1, EPIPHANY_F_OPC_31_32, EPIPHANY_F_SIMM8, EPIPHANY_F_SIMM24
+ , EPIPHANY_F_SDISP3, EPIPHANY_F_DISP3, EPIPHANY_F_DISP8, EPIPHANY_F_IMM8
+ , EPIPHANY_F_IMM_27_8, EPIPHANY_F_ADDSUBX, EPIPHANY_F_SUBD, EPIPHANY_F_PM
+ , EPIPHANY_F_RM, EPIPHANY_F_RN, EPIPHANY_F_RD, EPIPHANY_F_RM_X
+ , EPIPHANY_F_RN_X, EPIPHANY_F_RD_X, EPIPHANY_F_DC_9_1, EPIPHANY_F_SN
+ , EPIPHANY_F_SD, EPIPHANY_F_SN_X, EPIPHANY_F_SD_X, EPIPHANY_F_DC_7_4
+ , EPIPHANY_F_TRAP_SWI_9_1, EPIPHANY_F_GIEN_GIDIS_9_1, EPIPHANY_F_DC_15_3, EPIPHANY_F_DC_15_7
+ , EPIPHANY_F_DC_15_6, EPIPHANY_F_TRAP_NUM, EPIPHANY_F_DC_20_1, EPIPHANY_F_DC_21_1
+ , EPIPHANY_F_DC_21_2, EPIPHANY_F_DC_22_3, EPIPHANY_F_DC_22_2, EPIPHANY_F_DC_22_1
+ , EPIPHANY_F_DC_25_6, EPIPHANY_F_DC_25_4, EPIPHANY_F_DC_25_2, EPIPHANY_F_DC_25_1
+ , EPIPHANY_F_DC_28_1, EPIPHANY_F_DC_31_3, EPIPHANY_F_DISP11, EPIPHANY_F_SDISP11
+ , EPIPHANY_F_IMM16, EPIPHANY_F_RD6, EPIPHANY_F_RN6, EPIPHANY_F_RM6
+ , EPIPHANY_F_SD6, EPIPHANY_F_SN6, EPIPHANY_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) EPIPHANY_F_MAX)
+
+/* Hardware attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr.  */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for epiphany hardware types.  */
+typedef enum cgen_hw_type {
+  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_REGISTERS, HW_H_FPREGISTERS, HW_H_ZBIT
+ , HW_H_NBIT, HW_H_CBIT, HW_H_VBIT, HW_H_VSBIT
+ , HW_H_BZBIT, HW_H_BNBIT, HW_H_BVBIT, HW_H_BUBIT
+ , HW_H_BIBIT, HW_H_BCBIT, HW_H_BVSBIT, HW_H_BISBIT
+ , HW_H_BUSBIT, HW_H_EXPCAUSE0BIT, HW_H_EXPCAUSE1BIT, HW_H_EXPCAUSE2BIT
+ , HW_H_EXTFSTALLBIT, HW_H_TRMBIT, HW_H_INVEXCENBIT, HW_H_OVFEXCENBIT
+ , HW_H_UNEXCENBIT, HW_H_TIMER0BIT0, HW_H_TIMER0BIT1, HW_H_TIMER0BIT2
+ , HW_H_TIMER0BIT3, HW_H_TIMER1BIT0, HW_H_TIMER1BIT1, HW_H_TIMER1BIT2
+ , HW_H_TIMER1BIT3, HW_H_MBKPTENBIT, HW_H_CLOCKGATEENBIT, HW_H_CORECFGRESBIT12
+ , HW_H_CORECFGRESBIT13, HW_H_CORECFGRESBIT14, HW_H_CORECFGRESBIT15, HW_H_CORECFGRESBIT16
+ , HW_H_CORECFGRESBIT20, HW_H_CORECFGRESBIT21, HW_H_CORECFGRESBIT24, HW_H_CORECFGRESBIT25
+ , HW_H_CORECFGRESBIT26, HW_H_CORECFGRESBIT27, HW_H_CORECFGRESBIT28, HW_H_CORECFGRESBIT29
+ , HW_H_CORECFGRESBIT30, HW_H_CORECFGRESBIT31, HW_H_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT1
+ , HW_H_ARITHMETIC_MODEBIT2, HW_H_GIDISABLEBIT, HW_H_KMBIT, HW_H_CAIBIT
+ , HW_H_SFLAGBIT, HW_H_PC, HW_H_MEMADDR, HW_H_CORE_REGISTERS
+ , HW_H_COREDMA_REGISTERS, HW_H_COREMEM_REGISTERS, HW_H_COREMESH_REGISTERS, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices.  */
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr.  */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0)
+
+/* Enum declaration for epiphany operand types.  */
+typedef enum cgen_operand_type {
+  EPIPHANY_OPERAND_PC, EPIPHANY_OPERAND_ZBIT, EPIPHANY_OPERAND_NBIT, EPIPHANY_OPERAND_CBIT
+ , EPIPHANY_OPERAND_VBIT, EPIPHANY_OPERAND_BZBIT, EPIPHANY_OPERAND_BNBIT, EPIPHANY_OPERAND_BVBIT
+ , EPIPHANY_OPERAND_BCBIT, EPIPHANY_OPERAND_BUBIT, EPIPHANY_OPERAND_BIBIT, EPIPHANY_OPERAND_VSBIT
+ , EPIPHANY_OPERAND_BVSBIT, EPIPHANY_OPERAND_BISBIT, EPIPHANY_OPERAND_BUSBIT, EPIPHANY_OPERAND_EXPCAUSE0BIT
+ , EPIPHANY_OPERAND_EXPCAUSE1BIT, EPIPHANY_OPERAND_EXPCAUSE2BIT, EPIPHANY_OPERAND_EXTFSTALLBIT, EPIPHANY_OPERAND_TRMBIT
+ , EPIPHANY_OPERAND_INVEXCENBIT, EPIPHANY_OPERAND_OVFEXCENBIT, EPIPHANY_OPERAND_UNEXCENBIT, EPIPHANY_OPERAND_TIMER0BIT0
+ , EPIPHANY_OPERAND_TIMER0BIT1, EPIPHANY_OPERAND_TIMER0BIT2, EPIPHANY_OPERAND_TIMER0BIT3, EPIPHANY_OPERAND_TIMER1BIT0
+ , EPIPHANY_OPERAND_TIMER1BIT1, EPIPHANY_OPERAND_TIMER1BIT2, EPIPHANY_OPERAND_TIMER1BIT3, EPIPHANY_OPERAND_MBKPTENBIT
+ , EPIPHANY_OPERAND_CLOCKGATEENBIT, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2
+ , EPIPHANY_OPERAND_CORECFGRESBIT12, EPIPHANY_OPERAND_CORECFGRESBIT13, EPIPHANY_OPERAND_CORECFGRESBIT14, EPIPHANY_OPERAND_CORECFGRESBIT15
+ , EPIPHANY_OPERAND_CORECFGRESBIT16, EPIPHANY_OPERAND_CORECFGRESBIT20, EPIPHANY_OPERAND_CORECFGRESBIT21, EPIPHANY_OPERAND_CORECFGRESBIT24
+ , EPIPHANY_OPERAND_CORECFGRESBIT25, EPIPHANY_OPERAND_CORECFGRESBIT26, EPIPHANY_OPERAND_CORECFGRESBIT27, EPIPHANY_OPERAND_CORECFGRESBIT28
+ , EPIPHANY_OPERAND_CORECFGRESBIT29, EPIPHANY_OPERAND_CORECFGRESBIT30, EPIPHANY_OPERAND_CORECFGRESBIT31, EPIPHANY_OPERAND_GIDISABLEBIT
+ , EPIPHANY_OPERAND_KMBIT, EPIPHANY_OPERAND_CAIBIT, EPIPHANY_OPERAND_SFLAGBIT, EPIPHANY_OPERAND_MEMADDR
+ , EPIPHANY_OPERAND_SIMM24, EPIPHANY_OPERAND_SIMM8, EPIPHANY_OPERAND_RD, EPIPHANY_OPERAND_RN
+ , EPIPHANY_OPERAND_RM, EPIPHANY_OPERAND_FRD, EPIPHANY_OPERAND_FRN, EPIPHANY_OPERAND_FRM
+ , EPIPHANY_OPERAND_RD6, EPIPHANY_OPERAND_RN6, EPIPHANY_OPERAND_RM6, EPIPHANY_OPERAND_FRD6
+ , EPIPHANY_OPERAND_FRN6, EPIPHANY_OPERAND_FRM6, EPIPHANY_OPERAND_SD, EPIPHANY_OPERAND_SN
+ , EPIPHANY_OPERAND_SD6, EPIPHANY_OPERAND_SN6, EPIPHANY_OPERAND_SDDMA, EPIPHANY_OPERAND_SNDMA
+ , EPIPHANY_OPERAND_SDMEM, EPIPHANY_OPERAND_SNMEM, EPIPHANY_OPERAND_SDMESH, EPIPHANY_OPERAND_SNMESH
+ , EPIPHANY_OPERAND_SIMM3, EPIPHANY_OPERAND_SIMM11, EPIPHANY_OPERAND_DISP3, EPIPHANY_OPERAND_TRAPNUM6
+ , EPIPHANY_OPERAND_SWI_NUM, EPIPHANY_OPERAND_DISP11, EPIPHANY_OPERAND_SHIFT, EPIPHANY_OPERAND_IMM16
+ , EPIPHANY_OPERAND_IMM8, EPIPHANY_OPERAND_DIRECTION, EPIPHANY_OPERAND_DPMI, EPIPHANY_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types.  */
+#define MAX_OPERANDS 91
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices.  */
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_INSN, CGEN_INSN_IMM3
+ , CGEN_INSN_IMM8, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
+ , CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr.  */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SHORT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SHORT_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_IMM3_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM3)) != 0)
+#define CGEN_ATTR_CGEN_INSN_IMM8_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM8)) != 0)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld epiphany_cgen_ifld_table[];
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[];
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_cr_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crdma_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crmem_names;
+extern CGEN_KEYWORD epiphany_cgen_opval_crmesh_names;
+
+extern const CGEN_HW_ENTRY epiphany_cgen_hw_table[];
+
+
+
+#endif /* EPIPHANY_CPU_H */
diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c
new file mode 100644
index 0000000..bd86f46
--- /dev/null
+++ b/opcodes/epiphany-dis.c
@@ -0,0 +1,698 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
+   2008, 2010  Free Software Foundation, Inc.
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized.  */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
+
+/* -- disassembler routines inserted here.  */
+
+/* -- dis.c */
+
+#define CGEN_PRINT_INSN epiphany_print_insn
+
+static int
+epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  int buflen;
+  int status;
+
+  info->bytes_per_chunk = 2;
+
+  /* Attempt to read the base part of the insn.  */
+  info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
+  status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  /* Try again with the minimum part, if min < base.  */
+  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+    {
+      info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
+      status = (*info->read_memory_func) (pc, buf, buflen, info);
+    }
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  return print_insn (cd, pc, info, buf, buflen);
+}
+
+
+static void
+print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		 void * dis_info,
+		 long value,
+		 unsigned int attrs ATTRIBUTE_UNUSED,
+		 bfd_vma pc ATTRIBUTE_UNUSED,
+		 int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  (*info->fprintf_func) (info->stream, value ? "-" : "+");
+}
+
+static void
+print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    void * dis_info,
+		    long value,
+		    unsigned int attrs ATTRIBUTE_UNUSED,
+		    bfd_vma pc ATTRIBUTE_UNUSED,
+		    int length ATTRIBUTE_UNUSED)
+{
+  print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+static void
+print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    void * dis_info,
+		    unsigned long value,
+		    unsigned int attrs ATTRIBUTE_UNUSED,
+		    bfd_vma pc ATTRIBUTE_UNUSED,
+		    int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *)dis_info;
+
+  if (value & 0x800)
+    (*info->fprintf_func) (info->stream, "-");
+
+  value &= 0x7ff;
+  print_address (cd, dis_info, value, attrs, pc, length);
+}
+
+
+/* -- */
+
+void epiphany_cgen_print_operand
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+   of dis-asm.h on cgen.h.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+void
+epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
+{
+  disassemble_info *info = (disassemble_info *) xinfo;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      print_postindex (cd, info, fields->f_addsubx, 0, pc, length);
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      print_uimm_not_reg (cd, info, fields->f_disp11, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      print_normal (cd, info, fields->f_disp3, 0, pc, length);
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      print_postindex (cd, info, fields->f_subd, 0, pc, length);
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      print_address (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      print_address (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_RELAX), pc, length);
+      break;
+    case EPIPHANY_OPERAND_RD :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_RM :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_RN :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SD :
+      print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd, 0);
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      print_normal (cd, info, fields->f_shift, 0, pc, length);
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      print_simm_not_reg (cd, info, fields->f_sdisp11, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      print_address (cd, info, fields->f_simm24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      print_simm_not_reg (cd, info, fields->f_sdisp3, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX), pc, length);
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      print_address (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case EPIPHANY_OPERAND_SN :
+      print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn, 0);
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      print_uimm_not_reg (cd, info, fields->f_trap_num, 0, pc, length);
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      print_normal (cd, info, fields->f_trap_num, 0, pc, length);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+	       opindex);
+    abort ();
+  }
+}
+
+cgen_print_fn * const epiphany_cgen_print_handlers[] = 
+{
+  print_insn_normal,
+};
+
+
+void
+epiphany_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+  epiphany_cgen_init_opcode_table (cd);
+  epiphany_cgen_init_ibld_table (cd);
+  cd->print_handlers = & epiphany_cgen_print_handlers[0];
+  cd->print_operand = epiphany_cgen_print_operand;
+}
+
+
+/* Default print handler.  */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler.  */
+
+static void
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* Nothing to do.  */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", (long) value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler.  */
+
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
+
+  ke = cgen_keyword_lookup_value (keyword_table, value);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
+   about disassemble_info.  */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_INIT_PRINT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+	  continue;
+	}
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+	  continue;
+	}
+
+      /* We have an operand.  */
+      epiphany_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+				 fields, CGEN_INSN_ATTRS (insn), pc, length);
+    }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+   the extract info.
+   Returns 0 if all is well, non-zero otherwise.  */
+
+static int
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   bfd_byte *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
+{
+  int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  ex_info->dis_info = info;
+  ex_info->valid = (1 << buflen) - 1;
+  ex_info->insn_bytes = buf;
+
+  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+  return 0;
+}
+
+/* Utility to print an insn.
+   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    bfd_byte *buf,
+	    unsigned int buflen)
+{
+  CGEN_INSN_INT insn_value;
+  const CGEN_INSN_LIST *insn_list;
+  CGEN_EXTRACT_INFO ex_info;
+  int basesize;
+
+  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+  basesize = cd->base_insn_bitsize < buflen * 8 ?
+                                     cd->base_insn_bitsize : buflen * 8;
+  insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+  /* Fill in ex_info fields like read_insn would.  Don't actually call
+     read_insn, since the incoming buffer is already read (and possibly
+     modified a la m32r).  */
+  ex_info.valid = (1 << buflen) - 1;
+  ex_info.dis_info = info;
+  ex_info.insn_bytes = buf;
+
+  /* The instructions are stored in hash lists.
+     Pick the first one and keep trying until we find the right one.  */
+
+  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+  while (insn_list != NULL)
+    {
+      const CGEN_INSN *insn = insn_list->insn;
+      CGEN_FIELDS fields;
+      int length;
+      unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not needed as insn shouldn't be in hash lists if not supported.  */
+      /* Supported by this cpu?  */
+      if (! epiphany_cgen_insn_supported (cd, insn))
+        {
+          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+	  continue;
+        }
+#endif
+
+      /* Basic bit mask must be correct.  */
+      /* ??? May wish to allow target to defer this check until the extract
+	 handler.  */
+
+      /* Base size may exceed this instruction's size.  Extract the
+         relevant part from the buffer. */
+      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
+					   info->endian == BFD_ENDIAN_BIG);
+      else
+	insn_value_cropped = insn_value;
+
+      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+	  == CGEN_INSN_BASE_VALUE (insn))
+	{
+	  /* Printing is handled in two passes.  The first pass parses the
+	     machine insn and extracts the fields.  The second pass prints
+	     them.  */
+
+	  /* Make sure the entire insn is loaded into insn_value, if it
+	     can fit.  */
+	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	    {
+	      unsigned long full_insn_value;
+	      int rc = read_insn (cd, pc, info, buf,
+				  CGEN_INSN_BITSIZE (insn) / 8,
+				  & ex_info, & full_insn_value);
+	      if (rc != 0)
+		return rc;
+	      length = CGEN_EXTRACT_FN (cd, insn)
+		(cd, insn, &ex_info, full_insn_value, &fields, pc);
+	    }
+	  else
+	    length = CGEN_EXTRACT_FN (cd, insn)
+	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+	  /* Length < 0 -> error.  */
+	  if (length < 0)
+	    return length;
+	  if (length > 0)
+	    {
+	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+	      /* Length is in bits, result is in bytes.  */
+	      return length / 8;
+	    }
+	}
+
+      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+    }
+
+  return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occured fetching bytes.  */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  int buflen;
+  int status;
+
+  /* Attempt to read the base part of the insn.  */
+  buflen = cd->base_insn_bitsize / 8;
+  status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  /* Try again with the minimum part, if min < base.  */
+  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+    {
+      buflen = cd->min_insn_bitsize / 8;
+      status = (*info->read_memory_func) (pc, buf, buflen, info);
+    }
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+   Print one instruction from PC on INFO->STREAM.
+   Return the size of the instruction (in bytes).  */
+
+typedef struct cpu_desc_list
+{
+  struct cpu_desc_list *next;
+  CGEN_BITSET *isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_epiphany (bfd_vma pc, disassemble_info *info)
+{
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
+  static CGEN_CPU_DESC cd = 0;
+  static CGEN_BITSET *prev_isa;
+  static int prev_mach;
+  static int prev_endian;
+  int length;
+  CGEN_BITSET *isa;
+  int mach;
+  int endian = (info->endian == BFD_ENDIAN_BIG
+		? CGEN_ENDIAN_BIG
+		: CGEN_ENDIAN_LITTLE);
+  enum bfd_architecture arch;
+
+  /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_epiphany
+#endif
+  arch = info->arch;
+  if (arch == bfd_arch_unknown)
+    arch = CGEN_BFD_ARCH;
+   
+  /* There's no standard way to compute the machine or isa number
+     so we leave it to the target.  */
+#ifdef CGEN_COMPUTE_MACH
+  mach = CGEN_COMPUTE_MACH (info);
+#else
+  mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
+#else
+  isa = info->insn_sets;
+#endif
+
+  /* If we've switched cpu's, try to find a handle we've used before */
+  if (cd
+      && (cgen_bitset_compare (isa, prev_isa) != 0
+	  || mach != prev_mach
+	  || endian != prev_endian))
+    {
+      cd = 0;
+      for (cl = cd_list; cl; cl = cl->next)
+	{
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
+	      cl->mach == mach &&
+	      cl->endian == endian)
+	    {
+	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
+	      break;
+	    }
+	}
+    } 
+
+  /* If we haven't initialized yet, initialize the opcode table.  */
+  if (! cd)
+    {
+      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+      const char *mach_name;
+
+      if (!arch_type)
+	abort ();
+      mach_name = arch_type->printable_name;
+
+      prev_isa = cgen_bitset_copy (isa);
+      prev_mach = mach;
+      prev_endian = endian;
+      cd = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+				 CGEN_CPU_OPEN_BFDMACH, mach_name,
+				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
+				 CGEN_CPU_OPEN_END);
+      if (!cd)
+	abort ();
+
+      /* Save this away for future reference.  */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = prev_isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
+      epiphany_cgen_init_dis (cd);
+    }
+
+  /* We try to have as much common code as possible.
+     But at this point some targets need to take over.  */
+  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
+     but if not possible try to move this hook elsewhere rather than
+     have two hooks.  */
+  length = CGEN_PRINT_INSN (cd, pc, info);
+  if (length > 0)
+    return length;
+  if (length < 0)
+    return -1;
+
+  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+  return cd->default_insn_bitsize / 8;
+}
diff --git a/opcodes/epiphany-ibld.c b/opcodes/epiphany-ibld.c
new file mode 100644
index 0000000..7b332d5
--- /dev/null
+++ b/opcodes/epiphany-ibld.c
@@ -0,0 +1,1709 @@
+/* Instruction building/extraction support for epiphany. -*- C -*-
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
+   2008, 2010  Free Software Foundation, Inc.
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "cgen/basic-modes.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
+static const char * insert_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+static int extract_normal
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
+static int extract_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
+static CGEN_INLINE int fill_cache
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
+static CGEN_INLINE long extract_1
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
+#endif
+
+/* Operand insertion.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal.  */
+
+static CGEN_INLINE void
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
+{
+  unsigned long x,mask;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+  cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+   ATTRS is a mask of the boolean attributes.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   The result is an error message or NULL if success.  */
+
+/* ??? This duplicates functionality with bfd's howto table and
+   bfd_install_relocation.  */
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static const char *
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
+{
+  static char errbuf[100];
+  /* Written this way to avoid undefined behaviour.  */
+  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
+  if (length == 0)
+    return NULL;
+
+  if (word_length > 8 * sizeof (CGEN_INSN_INT))
+    abort ();
+
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset == 0
+	  && word_length > total_length)
+	word_length = total_length;
+    }
+
+  /* Ensure VALUE will fit.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+    {
+      long minval = - (1L << (length - 1));
+      unsigned long maxval = mask;
+      
+      if ((value > 0 && (unsigned long) value > maxval)
+	  || value < minval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%ld not between %ld and %lu)"),
+		   value, minval, maxval);
+	  return errbuf;
+	}
+    }
+  else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+    {
+      unsigned long maxval = mask;
+      unsigned long val = (unsigned long) value;
+
+      /* For hosts with a word size > 32 check to see if value has been sign
+	 extended beyond 32 bits.  If so then ignore these higher sign bits
+	 as the user is attempting to store a 32-bit signed value into an
+	 unsigned 32-bit field which is allowed.  */
+      if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
+	val &= 0xFFFFFFFF;
+
+      if (val > maxval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (0x%lx not between 0 and 0x%lx)"),
+		   val, maxval);
+	  return errbuf;
+	}
+    }
+  else
+    {
+      if (! cgen_signed_overflow_ok_p (cd))
+	{
+	  long minval = - (1L << (length - 1));
+	  long maxval =   (1L << (length - 1)) - 1;
+	  
+	  if (value < minval || value > maxval)
+	    {
+	      sprintf
+		/* xgettext:c-format */
+		(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+		 value, minval, maxval);
+	      return errbuf;
+	    }
+	}
+    }
+
+#if CGEN_INT_INSN_P
+
+  {
+    int shift;
+
+    if (CGEN_INSN_LSB0_P)
+      shift = (word_offset + start + 1) - length;
+    else
+      shift = total_length - (word_offset + start + length);
+    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+  }
+
+#else /* ! CGEN_INT_INSN_P */
+
+  {
+    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+    insert_1 (cd, value, start, length, word_length, bufp);
+  }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  return NULL;
+}
+
+/* Default insn builder (insert handler).
+   The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+   that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+   recorded in host byte order, otherwise BUFFER is an array of bytes
+   and the value is recorded in target byte order).
+   The result is an error message or NULL if success.  */
+
+static const char *
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  unsigned long value;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+  CGEN_INIT_INSERT (cd);
+  value = CGEN_INSN_BASE_VALUE (insn);
+
+  /* If we're recording insns as numbers (rather than a string of bytes),
+     target byte order handling is deferred until later.  */
+
+#if CGEN_INT_INSN_P
+
+  put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+		      CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+  cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+					(unsigned) CGEN_FIELDS_BITSIZE (fields)),
+		       value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* ??? It would be better to scan the format's fields.
+     Still need to be able to insert a value based on the operand though;
+     e.g. storing a branch displacement that got resolved later.
+     Needs more thought first.  */
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+    {
+      const char *errmsg;
+
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	continue;
+
+      errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+				       fields, buffer, pc);
+      if (errmsg)
+	return errmsg;
+    }
+
+  return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn.  Must go here
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+
+static void
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
+{
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     length may be too big.  */
+  if (length > insn_length)
+    *buf = value;
+  else
+    {
+      int shift = insn_length - length;
+      /* Written this way to avoid undefined behaviour.  */
+      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+      *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+    }
+}
+#endif
+
+/* Operand extraction.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+   Ensure sufficient bytes are cached in EX_INFO.
+   OFFSET is the offset in bytes from the start of the insn of the value.
+   BYTES is the length of the needed value.
+   Returns 1 for success, 0 for failure.  */
+
+static CGEN_INLINE int
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
+{
+  /* It's doubtful that the middle part has already been fetched so
+     we don't optimize that case.  kiss.  */
+  unsigned int mask;
+  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+  /* First do a quick check.  */
+  mask = (1 << bytes) - 1;
+  if (((ex_info->valid >> offset) & mask) == mask)
+    return 1;
+
+  /* Search for the first byte we need to read.  */
+  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+    if (! (mask & ex_info->valid))
+      break;
+
+  if (bytes)
+    {
+      int status;
+
+      pc += offset;
+      status = (*info->read_memory_func)
+	(pc, ex_info->insn_bytes + offset, bytes, info);
+
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, pc, info);
+	  return 0;
+	}
+
+      ex_info->valid |= ((1 << bytes) - 1) << offset;
+    }
+
+  return 1;
+}
+
+/* Subroutine of extract_normal.  */
+
+static CGEN_INLINE long
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  unsigned long x;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+   INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+   or sometimes less for cases like the m32r where the base insn size is 32
+   but some insns are 16 bits.
+   ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
+   but for generality we take a bitmask of all of them.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   Returns 1 for success, 0 for failure.  */
+
+/* ??? The return code isn't properly used.  wip.  */
+
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static int
+extract_normal (CGEN_CPU_DESC cd,
+#if ! CGEN_INT_INSN_P
+		CGEN_EXTRACT_INFO *ex_info,
+#else
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+#endif
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
+#if ! CGEN_INT_INSN_P
+		bfd_vma pc,
+#else
+		bfd_vma pc ATTRIBUTE_UNUSED,
+#endif
+		long *valuep)
+{
+  long value, mask;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value
+     so give it a standard value of zero.  */
+  if (length == 0)
+    {
+      *valuep = 0;
+      return 1;
+    }
+
+  if (word_length > 8 * sizeof (CGEN_INSN_INT))
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset + word_length > total_length)
+	word_length = total_length - word_offset;
+    }
+
+  /* Does the value reside in INSN_VALUE, and at the right alignment?  */
+
+  if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+    {
+      if (CGEN_INSN_LSB0_P)
+	value = insn_value >> ((word_offset + start + 1) - length);
+      else
+	value = insn_value >> (total_length - ( word_offset + start + length));
+    }
+
+#if ! CGEN_INT_INSN_P
+
+  else
+    {
+      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+      if (word_length > 8 * sizeof (CGEN_INSN_INT))
+	abort ();
+
+      if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+	return 0;
+
+      value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+    }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  value &= mask;
+  /* sign extend? */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+      && (value & (1L << (length - 1))))
+    value |= ~mask;
+
+  *valuep = value;
+
+  return 1;
+}
+
+/* Default insn extractor.
+
+   INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+   The extracted fields are stored in FIELDS.
+   EX_INFO is used to handle reading variable length insns.
+   Return the length of the insn in bits, or 0 if no match,
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+  CGEN_INIT_EXTRACT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      int length;
+
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	continue;
+
+      length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+					ex_info, insn_value, fields, pc);
+      if (length <= 0)
+	return length;
+    }
+
+  /* We recognized and successfully extracted this insn.  */
+  return CGEN_INSN_BITSIZE (insn);
+}
+
+/* Machine generated code added here.  */
+
+const char * epiphany_cgen_insert_operand
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.  */
+
+const char *
+epiphany_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  const char * errmsg = NULL;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      {
+{
+  FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255));
+  FLD (f_disp3) = ((FLD (f_disp11)) & (7));
+}
+        errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      {
+{
+  FLD (f_rd) = ((FLD (f_rd6)) & (7));
+  FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      {
+{
+  FLD (f_rm) = ((FLD (f_rm6)) & (7));
+  FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      {
+{
+  FLD (f_rn) = ((FLD (f_rn6)) & (7));
+  FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      {
+{
+  FLD (f_imm8) = ((FLD (f_imm16)) & (255));
+  FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8));
+}
+        errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_RD :
+      errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      {
+{
+  FLD (f_rd) = ((FLD (f_rd6)) & (7));
+  FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_RM :
+      errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      {
+{
+  FLD (f_rm) = ((FLD (f_rm6)) & (7));
+  FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_RN :
+      errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      {
+{
+  FLD (f_rn) = ((FLD (f_rn6)) & (7));
+  FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SD :
+      errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      {
+{
+  FLD (f_sd) = ((FLD (f_sd6)) & (7));
+  FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      {
+{
+  FLD (f_sd) = ((FLD (f_sd6)) & (7));
+  FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      {
+{
+  FLD (f_sd) = ((FLD (f_sd6)) & (7));
+  FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      {
+{
+  FLD (f_sd) = ((FLD (f_sd6)) & (7));
+  FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      {
+{
+  FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3))));
+  FLD (f_disp3) = ((FLD (f_sdisp11)) & (7));
+}
+        errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      {
+        long value = fields->f_simm24;
+        value = ((SI) (((value) - (pc))) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer);
+      }
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      {
+        long value = fields->f_simm8;
+        value = ((SI) (((value) - (pc))) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer);
+      }
+      break;
+    case EPIPHANY_OPERAND_SN :
+      errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      {
+{
+  FLD (f_sn) = ((FLD (f_sn6)) & (7));
+  FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      {
+{
+  FLD (f_sn) = ((FLD (f_sn6)) & (7));
+  FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      {
+{
+  FLD (f_sn) = ((FLD (f_sn6)) & (7));
+  FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      {
+{
+  FLD (f_sn) = ((FLD (f_sn6)) & (7));
+  FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer);
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+	       opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+int epiphany_cgen_extract_operand
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+
+/* Main entry point for operand extraction.
+   The result is <= 0 for error, >0 for success.
+   ??? Actual values aren't well defined right now.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+int
+epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
+{
+  /* Assume success (for those operands that are nops).  */
+  int length = 1;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx);
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8);
+        if (length <= 0) break;
+{
+  FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd);
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+        if (length <= 0) break;
+{
+  FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+        if (length <= 0) break;
+{
+  FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+        if (length <= 0) break;
+{
+  FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8);
+        if (length <= 0) break;
+{
+  FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8);
+      break;
+    case EPIPHANY_OPERAND_RD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd);
+        if (length <= 0) break;
+{
+  FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_RM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm);
+        if (length <= 0) break;
+{
+  FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_RN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn);
+        if (length <= 0) break;
+{
+  FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+        if (length <= 0) break;
+{
+  FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+        if (length <= 0) break;
+{
+  FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+        if (length <= 0) break;
+{
+  FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd);
+        if (length <= 0) break;
+{
+  FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift);
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8);
+        if (length <= 0) break;
+{
+  FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value);
+        value = ((((value) << (1))) + (pc));
+        fields->f_simm24 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3);
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value);
+        value = ((((value) << (1))) + (pc));
+        fields->f_simm8 = value;
+      }
+      break;
+    case EPIPHANY_OPERAND_SN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+        if (length <= 0) break;
+{
+  FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+        if (length <= 0) break;
+{
+  FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+        if (length <= 0) break;
+{
+  FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn);
+        if (length <= 0) break;
+{
+  FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn)));
+}
+      }
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num);
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+	       opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+cgen_insert_fn * const epiphany_cgen_insert_handlers[] = 
+{
+  insert_insn_normal,
+};
+
+cgen_extract_fn * const epiphany_cgen_extract_handlers[] = 
+{
+  extract_insn_normal,
+};
+
+int epiphany_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they return.
+   TODO: floating point, inlining support, remove cases where result type
+   not appropriate.  */
+
+int
+epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  int value;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      value = fields->f_addsubx;
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      value = fields->f_disp11;
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      value = fields->f_disp3;
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      value = fields->f_subd;
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      value = fields->f_rd;
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      value = fields->f_rd6;
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      value = fields->f_rm;
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      value = fields->f_rm6;
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      value = fields->f_rn;
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      value = fields->f_rn6;
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      value = fields->f_imm16;
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      value = fields->f_imm8;
+      break;
+    case EPIPHANY_OPERAND_RD :
+      value = fields->f_rd;
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      value = fields->f_rd6;
+      break;
+    case EPIPHANY_OPERAND_RM :
+      value = fields->f_rm;
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      value = fields->f_rm6;
+      break;
+    case EPIPHANY_OPERAND_RN :
+      value = fields->f_rn;
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      value = fields->f_rn6;
+      break;
+    case EPIPHANY_OPERAND_SD :
+      value = fields->f_sd;
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      value = fields->f_shift;
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      value = fields->f_sdisp11;
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      value = fields->f_simm24;
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      value = fields->f_sdisp3;
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      value = fields->f_simm8;
+      break;
+    case EPIPHANY_OPERAND_SN :
+      value = fields->f_sn;
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      value = fields->f_trap_num;
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      value = fields->f_trap_num;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+bfd_vma
+epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      value = fields->f_addsubx;
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      value = fields->f_disp11;
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      value = fields->f_disp3;
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      value = fields->f_subd;
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      value = fields->f_rd;
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      value = fields->f_rd6;
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      value = fields->f_rm;
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      value = fields->f_rm6;
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      value = fields->f_rn;
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      value = fields->f_rn6;
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      value = fields->f_imm16;
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      value = fields->f_imm8;
+      break;
+    case EPIPHANY_OPERAND_RD :
+      value = fields->f_rd;
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      value = fields->f_rd6;
+      break;
+    case EPIPHANY_OPERAND_RM :
+      value = fields->f_rm;
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      value = fields->f_rm6;
+      break;
+    case EPIPHANY_OPERAND_RN :
+      value = fields->f_rn;
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      value = fields->f_rn6;
+      break;
+    case EPIPHANY_OPERAND_SD :
+      value = fields->f_sd;
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      value = fields->f_sd6;
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      value = fields->f_shift;
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      value = fields->f_sdisp11;
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      value = fields->f_simm24;
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      value = fields->f_sdisp3;
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      value = fields->f_simm8;
+      break;
+    case EPIPHANY_OPERAND_SN :
+      value = fields->f_sn;
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      value = fields->f_sn6;
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      value = fields->f_trap_num;
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      value = fields->f_trap_num;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+void epiphany_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void epiphany_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they accept.
+   TODO: floating point, inlining support, remove cases where argument type
+   not appropriate.  */
+
+void
+epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
+{
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      fields->f_addsubx = value;
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      fields->f_disp11 = value;
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      fields->f_disp3 = value;
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      fields->f_subd = value;
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      fields->f_rd = value;
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      fields->f_rd6 = value;
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      fields->f_rm = value;
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      fields->f_rm6 = value;
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      fields->f_rn = value;
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      fields->f_rn6 = value;
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      fields->f_imm16 = value;
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      fields->f_imm8 = value;
+      break;
+    case EPIPHANY_OPERAND_RD :
+      fields->f_rd = value;
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      fields->f_rd6 = value;
+      break;
+    case EPIPHANY_OPERAND_RM :
+      fields->f_rm = value;
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      fields->f_rm6 = value;
+      break;
+    case EPIPHANY_OPERAND_RN :
+      fields->f_rn = value;
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      fields->f_rn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SD :
+      fields->f_sd = value;
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      fields->f_shift = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      fields->f_sdisp11 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      fields->f_simm24 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      fields->f_sdisp3 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      fields->f_simm8 = value;
+      break;
+    case EPIPHANY_OPERAND_SN :
+      fields->f_sn = value;
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      fields->f_trap_num = value;
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      fields->f_trap_num = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+void
+epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
+{
+  switch (opindex)
+    {
+    case EPIPHANY_OPERAND_DIRECTION :
+      fields->f_addsubx = value;
+      break;
+    case EPIPHANY_OPERAND_DISP11 :
+      fields->f_disp11 = value;
+      break;
+    case EPIPHANY_OPERAND_DISP3 :
+      fields->f_disp3 = value;
+      break;
+    case EPIPHANY_OPERAND_DPMI :
+      fields->f_subd = value;
+      break;
+    case EPIPHANY_OPERAND_FRD :
+      fields->f_rd = value;
+      break;
+    case EPIPHANY_OPERAND_FRD6 :
+      fields->f_rd6 = value;
+      break;
+    case EPIPHANY_OPERAND_FRM :
+      fields->f_rm = value;
+      break;
+    case EPIPHANY_OPERAND_FRM6 :
+      fields->f_rm6 = value;
+      break;
+    case EPIPHANY_OPERAND_FRN :
+      fields->f_rn = value;
+      break;
+    case EPIPHANY_OPERAND_FRN6 :
+      fields->f_rn6 = value;
+      break;
+    case EPIPHANY_OPERAND_IMM16 :
+      fields->f_imm16 = value;
+      break;
+    case EPIPHANY_OPERAND_IMM8 :
+      fields->f_imm8 = value;
+      break;
+    case EPIPHANY_OPERAND_RD :
+      fields->f_rd = value;
+      break;
+    case EPIPHANY_OPERAND_RD6 :
+      fields->f_rd6 = value;
+      break;
+    case EPIPHANY_OPERAND_RM :
+      fields->f_rm = value;
+      break;
+    case EPIPHANY_OPERAND_RM6 :
+      fields->f_rm6 = value;
+      break;
+    case EPIPHANY_OPERAND_RN :
+      fields->f_rn = value;
+      break;
+    case EPIPHANY_OPERAND_RN6 :
+      fields->f_rn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SD :
+      fields->f_sd = value;
+      break;
+    case EPIPHANY_OPERAND_SD6 :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDDMA :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDMEM :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SDMESH :
+      fields->f_sd6 = value;
+      break;
+    case EPIPHANY_OPERAND_SHIFT :
+      fields->f_shift = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM11 :
+      fields->f_sdisp11 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM24 :
+      fields->f_simm24 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM3 :
+      fields->f_sdisp3 = value;
+      break;
+    case EPIPHANY_OPERAND_SIMM8 :
+      fields->f_simm8 = value;
+      break;
+    case EPIPHANY_OPERAND_SN :
+      fields->f_sn = value;
+      break;
+    case EPIPHANY_OPERAND_SN6 :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNDMA :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNMEM :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SNMESH :
+      fields->f_sn6 = value;
+      break;
+    case EPIPHANY_OPERAND_SWI_NUM :
+      fields->f_trap_num = value;
+      break;
+    case EPIPHANY_OPERAND_TRAPNUM6 :
+      fields->f_trap_num = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+/* Function to call before using the instruction builder tables.  */
+
+void
+epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+{
+  cd->insert_handlers = & epiphany_cgen_insert_handlers[0];
+  cd->extract_handlers = & epiphany_cgen_extract_handlers[0];
+
+  cd->insert_operand = epiphany_cgen_insert_operand;
+  cd->extract_operand = epiphany_cgen_extract_operand;
+
+  cd->get_int_operand = epiphany_cgen_get_int_operand;
+  cd->set_int_operand = epiphany_cgen_set_int_operand;
+  cd->get_vma_operand = epiphany_cgen_get_vma_operand;
+  cd->set_vma_operand = epiphany_cgen_set_vma_operand;
+}
diff --git a/opcodes/epiphany-opc.c b/opcodes/epiphany-opc.c
new file mode 100644
index 0000000..e761061
--- /dev/null
+++ b/opcodes/epiphany-opc.c
@@ -0,0 +1,4035 @@
+/* Instruction opcode table for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "epiphany-desc.h"
+#include "epiphany-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+
+
+
+/* -- asm.c */
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
+
+/* Instruction formats.  */
+
+#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f]
+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
+  0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq16 ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_SIMM8) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_SIMM24) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jr16 ATTRIBUTE_UNUSED = {
+  16, 16, 0xe3ff, { { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rts ATTRIBUTE_UNUSED = {
+  32, 32, 0xffffffff, { { F (F_DC_31_3) }, { F (F_RN_X) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jr ATTRIBUTE_UNUSED = {
+  32, 32, 0xe3ffe3ff, { { F (F_DC_31_3) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx16_s ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbp_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_DC_22_2) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd16_s ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_PM) }, { F (F_SUBD) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DISP11) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov16EQ ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmovEQ ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_RD) }, { F (F_SN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts6 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsdma ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsmem ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtsmesh ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
+  16, 16, 0xffff, { { F (F_DC_15_7) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_unimpl ATTRIBUTE_UNUSED = {
+  32, 32, 0xffffffff, { { F (F_OPC_31_32) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_gien ATTRIBUTE_UNUSED = {
+  16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_GIEN_GIDIS_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_swi_num ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = {
+  16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_trap16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
+  32, 32, 0x300007f, { { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x1f, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff001f, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitr16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitr ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fext ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov8 ATTRIBUTE_UNUSED = {
+  16, 16, 0x1f, { { F (F_RD) }, { F (F_IMM8) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov16 ATTRIBUTE_UNUSED = {
+  32, 32, 0x100f001f, { { F (F_DC_28_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_IMM16) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_loatf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_recipf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } }
+};
+
+#undef F
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.  */
+
+static const CGEN_OPCODE epiphany_cgen_insn_opcode_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* beq.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x0 }
+  },
+/* beq.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x8 }
+  },
+/* bne.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x10 }
+  },
+/* bne.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x18 }
+  },
+/* bgtu.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x20 }
+  },
+/* bgtu.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x28 }
+  },
+/* bgteu.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x30 }
+  },
+/* bgteu.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x38 }
+  },
+/* blteu.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x40 }
+  },
+/* blteu.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x48 }
+  },
+/* bltu.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x50 }
+  },
+/* bltu.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x58 }
+  },
+/* bgt.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x60 }
+  },
+/* bgt.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x68 }
+  },
+/* bgte.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x70 }
+  },
+/* bgte.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x78 }
+  },
+/* blt.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x80 }
+  },
+/* blt.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x88 }
+  },
+/* blte.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0x90 }
+  },
+/* blte.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0x98 }
+  },
+/* bbeq.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xa0 }
+  },
+/* bbeq.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xa8 }
+  },
+/* bbne.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xb0 }
+  },
+/* bbne.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xb8 }
+  },
+/* bblt.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xc0 }
+  },
+/* bblt.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xc8 }
+  },
+/* bblte.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xd0 }
+  },
+/* bblte.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xd8 }
+  },
+/* b.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xe0 }
+  },
+/* b.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xe8 }
+  },
+/* bl.s $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16, { 0xf0 }
+  },
+/* bl.l $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq, { 0xf8 }
+  },
+/* jr $rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), 0 } },
+    & ifmt_jr16, { 0x142 }
+  },
+/* rts */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_rts, { 0x402194f }
+  },
+/* jr $rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN6), 0 } },
+    & ifmt_jr, { 0x2014f }
+  },
+/* jalr $rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN), 0 } },
+    & ifmt_jr16, { 0x152 }
+  },
+/* jalr $rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RN6), 0 } },
+    & ifmt_jr, { 0x2015f }
+  },
+/* ldrb $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x1 }
+  },
+/* ldrb $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x5 }
+  },
+/* ldrb $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x9 }
+  },
+/* ldrb $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0xd }
+  },
+/* ldrb $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x4 }
+  },
+/* ldrb $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0xc }
+  },
+/* ldrb $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200000c }
+  },
+/* ldrh $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x21 }
+  },
+/* ldrh $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x25 }
+  },
+/* ldrh $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x29 }
+  },
+/* ldrh $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x2d }
+  },
+/* ldrh $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x24 }
+  },
+/* ldrh $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x2c }
+  },
+/* ldrh $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200002c }
+  },
+/* ldr $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x41 }
+  },
+/* ldr $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x45 }
+  },
+/* ldr $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x49 }
+  },
+/* ldr $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x4d }
+  },
+/* ldr $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x44 }
+  },
+/* ldr $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x4c }
+  },
+/* ldr $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200004c }
+  },
+/* ldrd $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x61 }
+  },
+/* ldrd $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x65 }
+  },
+/* ldrd $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x69 }
+  },
+/* ldrd $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x6d }
+  },
+/* ldrd $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x64 }
+  },
+/* ldrd $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x6c }
+  },
+/* ldrd $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200006c }
+  },
+/* testsetb $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x200009 }
+  },
+/* testseth $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x200029 }
+  },
+/* testset $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x200049 }
+  },
+/* strb $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x11 }
+  },
+/* strb $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x19 }
+  },
+/* strb $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x15 }
+  },
+/* strb $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x1d }
+  },
+/* strb $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x14 }
+  },
+/* strb $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x1c }
+  },
+/* strb $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200001c }
+  },
+/* strh $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x31 }
+  },
+/* strh $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x39 }
+  },
+/* strh $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x35 }
+  },
+/* strh $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x3d }
+  },
+/* strh $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x34 }
+  },
+/* strh $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x3c }
+  },
+/* strh $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200003c }
+  },
+/* str $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x51 }
+  },
+/* str $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x59 }
+  },
+/* str $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x55 }
+  },
+/* str $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x5d }
+  },
+/* str $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x54 }
+  },
+/* str $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x5c }
+  },
+/* str $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200005c }
+  },
+/* strd $rd,[$rn,$rm] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } },
+    & ifmt_ldrbx16_s, { 0x71 }
+  },
+/* strd $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx_l, { 0x79 }
+  },
+/* strd $rd,[$rn],$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } },
+    & ifmt_ldrbx16_s, { 0x75 }
+  },
+/* strd $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp_l, { 0x7d }
+  },
+/* strd $rd,[$rn,$disp3] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } },
+    & ifmt_ldrbd16_s, { 0x74 }
+  },
+/* strd $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd_l, { 0x7c }
+  },
+/* strd $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbd_l, { 0x200007c }
+  },
+/* moveq $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x2 }
+  },
+/* moveq $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2000f }
+  },
+/* movne $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x12 }
+  },
+/* movne $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2001f }
+  },
+/* movgtu $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x22 }
+  },
+/* movgtu $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2002f }
+  },
+/* movgteu $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x32 }
+  },
+/* movgteu $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2003f }
+  },
+/* movlteu $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x42 }
+  },
+/* movlteu $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2004f }
+  },
+/* movltu $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x52 }
+  },
+/* movltu $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2005f }
+  },
+/* movgt $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x62 }
+  },
+/* movgt $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2006f }
+  },
+/* movgte $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x72 }
+  },
+/* movgte $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2007f }
+  },
+/* movlt $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x82 }
+  },
+/* movlt $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2008f }
+  },
+/* movlte $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0x92 }
+  },
+/* movlte $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x2009f }
+  },
+/* mov $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0xe2 }
+  },
+/* mov $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x200ef }
+  },
+/* movbeq $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0xa2 }
+  },
+/* movbeq $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x200af }
+  },
+/* movbne $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0xb2 }
+  },
+/* movbne $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x200bf }
+  },
+/* movblt $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0xc2 }
+  },
+/* movblt $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x200cf }
+  },
+/* movblte $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_cmov16EQ, { 0xd2 }
+  },
+/* movblte $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmovEQ, { 0x200df }
+  },
+/* movts $sn,$rd */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SN), ',', OP (RD), 0 } },
+    & ifmt_movts16, { 0x102 }
+  },
+/* movts $sn6,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } },
+    & ifmt_movts6, { 0x2010f }
+  },
+/* movts $sndma,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } },
+    & ifmt_movtsdma, { 0x12010f }
+  },
+/* movts $snmem,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } },
+    & ifmt_movtsmem, { 0x22010f }
+  },
+/* movts $snmesh,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } },
+    & ifmt_movtsmesh, { 0x32010f }
+  },
+/* movfs $rd,$sn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (SN), 0 } },
+    & ifmt_movts16, { 0x112 }
+  },
+/* movfs $rd6,$sn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } },
+    & ifmt_movts6, { 0x2011f }
+  },
+/* movfs $rd6,$sndma */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } },
+    & ifmt_movtsdma, { 0x12011f }
+  },
+/* movfs $rd6,$snmem */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } },
+    & ifmt_movtsmem, { 0x22011f }
+  },
+/* movfs $rd6,$snmesh */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } },
+    & ifmt_movtsmesh, { 0x32011f }
+  },
+/* nop */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x1a2 }
+  },
+/* snop */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x3a2 }
+  },
+/* unimpl */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_unimpl, { 0xf000f }
+  },
+/* idle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x1b2 }
+  },
+/* bkpt */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x1c2 }
+  },
+/* mbkpt */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x3c2 }
+  },
+/* rti */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x1d2 }
+  },
+/* wand */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x182 }
+  },
+/* sync */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x1f2 }
+  },
+/* gie */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_gien, { 0x192 }
+  },
+/* gid */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_gien, { 0x392 }
+  },
+/* swi $swi_num */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SWI_NUM), 0 } },
+    & ifmt_swi_num, { 0x1e2 }
+  },
+/* swi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_swi, { 0x1e2 }
+  },
+/* trap $trapnum6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (TRAPNUM6), 0 } },
+    & ifmt_trap16, { 0x3e2 }
+  },
+/* add $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x1a }
+  },
+/* add $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa001f }
+  },
+/* sub $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x3a }
+  },
+/* sub $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa003f }
+  },
+/* and $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x5a }
+  },
+/* and $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa005f }
+  },
+/* orr $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x7a }
+  },
+/* orr $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa007f }
+  },
+/* eor $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0xa }
+  },
+/* eor $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa000f }
+  },
+/* add.s $rd,$rn,$simm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+    & ifmt_addi16, { 0x13 }
+  },
+/* add.l $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_addi, { 0x1b }
+  },
+/* sub.s $rd,$rn,$simm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+    & ifmt_addi16, { 0x33 }
+  },
+/* sub.l $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_addi, { 0x3b }
+  },
+/* asr $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x6a }
+  },
+/* asr $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa006f }
+  },
+/* lsr $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x4a }
+  },
+/* lsr $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa004f }
+  },
+/* lsl $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x2a }
+  },
+/* lsl $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0xa002f }
+  },
+/* lsr $rd,$rn,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri16, { 0x6 }
+  },
+/* lsr $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri32, { 0x6000f }
+  },
+/* lsl $rd,$rn,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri16, { 0x16 }
+  },
+/* lsl $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri32, { 0x6001f }
+  },
+/* asr $rd,$rn,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri16, { 0xe }
+  },
+/* asr $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri32, { 0xe000f }
+  },
+/* bitr $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_bitr16, { 0x1e }
+  },
+/* bitr $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_bitr, { 0xe001f }
+  },
+/* fext $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_fext, { 0x1a000f }
+  },
+/* fdep $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_fext, { 0x1a001f }
+  },
+/* lfsr $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_fext, { 0x1a002f }
+  },
+/* mov.b $rd,$imm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } },
+    & ifmt_mov8, { 0x3 }
+  },
+/* mov.l $rd6,$imm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+    & ifmt_mov16, { 0x2000b }
+  },
+/* movt $rd6,$imm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+    & ifmt_mov16, { 0x1002000b }
+  },
+/* fadd $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x7 }
+  },
+/* fadd $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0x7000f }
+  },
+/* fsub $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x17 }
+  },
+/* fsub $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0x7001f }
+  },
+/* fmul $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x27 }
+  },
+/* fmul $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0x7002f }
+  },
+/* fmadd $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x37 }
+  },
+/* fmadd $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0x7003f }
+  },
+/* fmsub $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_add16, { 0x47 }
+  },
+/* fmsub $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add, { 0x7004f }
+  },
+/* fabs rd,rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', 'r', 'd', ',', 'r', 'n', 0 } },
+    & ifmt_f_absf16, { 0x77 }
+  },
+/* fabs $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_absf32, { 0x7007f }
+  },
+/* float $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_f_loatf16, { 0x57 }
+  },
+/* float $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_absf32, { 0x7005f }
+  },
+/* fix $rd,$rn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } },
+    & ifmt_f_absf16, { 0x67 }
+  },
+/* fix $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_absf32, { 0x7006f }
+  },
+/* frecip $frd6,$frn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+    & ifmt_f_recipf32, { 0x17000f }
+  },
+/* fsqrt $frd6,$frn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+    & ifmt_f_recipf32, { 0x17001f }
+  },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns.  */
+
+#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f]
+static const CGEN_IFMT ifmt_beq16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bne16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bne32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgtu16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgtu32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgteu16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgteu32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blteu16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blteu32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bltu16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bltu32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgt16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgt32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgte16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bgte32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blt16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blt32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blte16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blte32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbeq16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbeq32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbne16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bbne32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblt16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblt32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblte16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bblte32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_b16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_b32r ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bl16r ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_blr ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbx ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbp ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbd ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdpm ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrbdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhx ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhp ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhd ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdpm ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrhdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrx ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrp ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrd ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdpm ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdx ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdp ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdd ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddpm ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrdds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldrddl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsetbt_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsetht_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_testsett_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbx_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbp_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbd_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdpm_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strbdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhx_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhp_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhd_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdpm_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strhdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strx_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strp_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strd_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdpm_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdx_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdp_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdd_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddpm_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strdds0 ATTRIBUTE_UNUSED = {
+  16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddl0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_strddl0_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lEQ ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lNE ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTU ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTEU ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTEU ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTU ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGT ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lGTE ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLT ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lLTE ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lB ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBEQ ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBNE ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBLT ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmov_lBLTE ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_l6 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_ldma ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_lmem ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movts_lmesh ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_l6 ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_ldma ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_lmem ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfs_lmesh ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sub_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_and_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_orr_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_eor_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addir ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi32r ATTRIBUTE_UNUSED = {
+  32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi32m ATTRIBUTE_UNUSED = {
+  32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subir ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subi32r ATTRIBUTE_UNUSED = {
+  32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_subi32m ATTRIBUTE_UNUSED = {
+  32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asr_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsr_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsl_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsri32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lsli32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_asri32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bitrl ATTRIBUTE_UNUSED = {
+  32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fext_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fdep_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lfsr_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov8r ATTRIBUTE_UNUSED = {
+  16, 16, 0x1f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_RD) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov16r ATTRIBUTE_UNUSED = {
+  32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movtl ATTRIBUTE_UNUSED = {
+  32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_addf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_addf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_subf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_subf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_mulf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_mulf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_maddf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_maddf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf16 ATTRIBUTE_UNUSED = {
+  16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_msubf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf32 ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_i_msubf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_absf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_loatf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_ixf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_recipf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_f_sqrtf32_l ATTRIBUTE_UNUSED = {
+  32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } }
+};
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities.  */
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) EPIPHANY_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table.  */
+
+static const CGEN_IBASE epiphany_cgen_macro_insn_table[] =
+{
+/* beq $simm8 */
+  {
+    -1, "beq16r", "beq", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* beq $simm24 */
+  {
+    -1, "beq32r", "beq", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bne $simm8 */
+  {
+    -1, "bne16r", "bne", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bne $simm24 */
+  {
+    -1, "bne32r", "bne", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgtu $simm8 */
+  {
+    -1, "bgtu16r", "bgtu", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgtu $simm24 */
+  {
+    -1, "bgtu32r", "bgtu", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgteu $simm8 */
+  {
+    -1, "bgteu16r", "bgteu", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgteu $simm24 */
+  {
+    -1, "bgteu32r", "bgteu", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blteu $simm8 */
+  {
+    -1, "blteu16r", "blteu", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blteu $simm24 */
+  {
+    -1, "blteu32r", "blteu", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bltu $simm8 */
+  {
+    -1, "bltu16r", "bltu", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bltu $simm24 */
+  {
+    -1, "bltu32r", "bltu", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgt $simm8 */
+  {
+    -1, "bgt16r", "bgt", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgt $simm24 */
+  {
+    -1, "bgt32r", "bgt", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgte $simm8 */
+  {
+    -1, "bgte16r", "bgte", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bgte $simm24 */
+  {
+    -1, "bgte32r", "bgte", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blt $simm8 */
+  {
+    -1, "blt16r", "blt", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blt $simm24 */
+  {
+    -1, "blt32r", "blt", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blte $simm8 */
+  {
+    -1, "blte16r", "blte", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* blte $simm24 */
+  {
+    -1, "blte32r", "blte", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbeq $simm8 */
+  {
+    -1, "bbeq16r", "bbeq", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbeq $simm24 */
+  {
+    -1, "bbeq32r", "bbeq", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbne $simm8 */
+  {
+    -1, "bbne16r", "bbne", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bbne $simm24 */
+  {
+    -1, "bbne32r", "bbne", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblt $simm8 */
+  {
+    -1, "bblt16r", "bblt", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblt $simm24 */
+  {
+    -1, "bblt32r", "bblt", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblte $simm8 */
+  {
+    -1, "bblte16r", "bblte", 16,
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bblte $simm24 */
+  {
+    -1, "bblte32r", "bblte", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* b $simm8 */
+  {
+    -1, "b16r", "b", 16,
+    { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* b $simm24 */
+  {
+    -1, "b32r", "b", 32,
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bl $simm8 */
+  {
+    -1, "bl16r", "bl", 16,
+    { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bl $simm24 */
+  {
+    -1, "blr", "bl", 32,
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "ldrbx", "ldrb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "ldrbp", "ldrb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "ldrbd", "ldrb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "ldrbdpm", "ldrb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd,[$rn] */
+  {
+    -1, "ldrbds0", "ldrb", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb $rd6,[$rn6] */
+  {
+    -1, "ldrbdl0", "ldrb", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrb.l $rd6,[$rn6] */
+  {
+    -1, "ldrbdl0.l", "ldrb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "ldrhx", "ldrh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "ldrhp", "ldrh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "ldrhd", "ldrh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "ldrhdpm", "ldrh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd,[$rn] */
+  {
+    -1, "ldrhds0", "ldrh", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh $rd6,[$rn6] */
+  {
+    -1, "ldrhdl0", "ldrh", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrh.l $rd6,[$rn6] */
+  {
+    -1, "ldrhdl0.l", "ldrh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "ldrx", "ldr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "ldrp", "ldr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "ldrd", "ldr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "ldrdpm", "ldr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd,[$rn] */
+  {
+    -1, "ldrds0", "ldr", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr $rd6,[$rn6] */
+  {
+    -1, "ldrdl0", "ldr", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldr.l $rd6,[$rn6] */
+  {
+    -1, "ldrdl0.l", "ldr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "ldrdx", "ldrd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "ldrdp", "ldrd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "ldrdd", "ldrd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "ldrddpm", "ldrd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd,[$rn] */
+  {
+    -1, "ldrdds0", "ldrd", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd $rd6,[$rn6] */
+  {
+    -1, "ldrddl0", "ldrd", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* ldrd.l $rd6,[$rn6] */
+  {
+    -1, "ldrddl0.l", "ldrd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testsetb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "testsetbt.l", "testsetb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testseth.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "testsetht.l", "testseth.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* testset.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "testsett.l", "testset.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "strbx.l", "strb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "strbp.l", "strb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "strbd.l", "strb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "strbdpm.l", "strb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd,[$rn] */
+  {
+    -1, "strbds0", "strb", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb $rd6,[$rn6] */
+  {
+    -1, "strbdl0", "strb", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strb.l $rd6,[$rn6] */
+  {
+    -1, "strbdl0.l", "strb.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "strhx.l", "strh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "strhp.l", "strh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "strhd.l", "strh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "strhdpm.l", "strh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd,[$rn] */
+  {
+    -1, "strhds0", "strh", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh $rd6,[$rn6] */
+  {
+    -1, "strhdl0", "strh", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strh.l $rd6,[$rn6] */
+  {
+    -1, "strhdl0.l", "strh.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "strx.l", "str.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "strp.l", "str.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "strd.l", "str.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "strdpm.l", "str.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd,[$rn] */
+  {
+    -1, "strds0", "str", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str $rd6,[$rn6] */
+  {
+    -1, "strdl0", "str", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* str.l $rd6,[$rn6] */
+  {
+    -1, "strdl0.l", "str.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd.l $rd6,[$rn6,$direction$rm6] */
+  {
+    -1, "strdx.l", "strd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd.l $rd6,[$rn6],$direction$rm6 */
+  {
+    -1, "strdp.l", "strd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    -1, "strdd.l", "strd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    -1, "strddpm.l", "strd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd,[$rn] */
+  {
+    -1, "strdds0", "strd", 16,
+    { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd $rd6,[$rn6] */
+  {
+    -1, "strddl0", "strd", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* strd.l $rd6,[$rn6] */
+  {
+    -1, "strddl0.l", "strd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* moveq.l $rd6,$rn6 */
+  {
+    -1, "cmov.lEQ", "moveq.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movne.l $rd6,$rn6 */
+  {
+    -1, "cmov.lNE", "movne.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgtu.l $rd6,$rn6 */
+  {
+    -1, "cmov.lGTU", "movgtu.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgteu.l $rd6,$rn6 */
+  {
+    -1, "cmov.lGTEU", "movgteu.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlteu.l $rd6,$rn6 */
+  {
+    -1, "cmov.lLTEU", "movlteu.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movltu.l $rd6,$rn6 */
+  {
+    -1, "cmov.lLTU", "movltu.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgt.l $rd6,$rn6 */
+  {
+    -1, "cmov.lGT", "movgt.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movgte.l $rd6,$rn6 */
+  {
+    -1, "cmov.lGTE", "movgte.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlt.l $rd6,$rn6 */
+  {
+    -1, "cmov.lLT", "movlt.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movlte.l $rd6,$rn6 */
+  {
+    -1, "cmov.lLTE", "movlte.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov.l $rd6,$rn6 */
+  {
+    -1, "cmov.lB", "mov.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbeq.l $rd6,$rn6 */
+  {
+    -1, "cmov.lBEQ", "movbeq.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movbne.l $rd6,$rn6 */
+  {
+    -1, "cmov.lBNE", "movbne.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblt.l $rd6,$rn6 */
+  {
+    -1, "cmov.lBLT", "movblt.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movblte.l $rd6,$rn6 */
+  {
+    -1, "cmov.lBLTE", "movblte.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts.l $sn6,$rd6 */
+  {
+    -1, "movts.l6", "movts.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts.l $sndma,$rd6 */
+  {
+    -1, "movts.ldma", "movts.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts.l $snmem,$rd6 */
+  {
+    -1, "movts.lmem", "movts.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movts.l $snmesh,$rd6 */
+  {
+    -1, "movts.lmesh", "movts.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs.l $rd6,$sn6 */
+  {
+    -1, "movfs.l6", "movfs.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs.l $rd6,$sndma */
+  {
+    -1, "movfs.ldma", "movfs.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs.l $rd6,$snmem */
+  {
+    -1, "movfs.lmem", "movfs.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movfs.l $rd6,$snmesh */
+  {
+    -1, "movfs.lmesh", "movfs.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add.l $rd6,$rn6,$rm6 */
+  {
+    -1, "add.l", "add.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub.l $rd6,$rn6,$rm6 */
+  {
+    -1, "sub.l", "sub.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* and.l $rd6,$rn6,$rm6 */
+  {
+    -1, "and.l", "and.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* orr.l $rd6,$rn6,$rm6 */
+  {
+    -1, "orr.l", "orr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* eor.l $rd6,$rn6,$rm6 */
+  {
+    -1, "eor.l", "eor.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add $rd,$rn,$simm3 */
+  {
+    -1, "addir", "add", 16,
+    { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add $rd6,$rn6,$simm11 */
+  {
+    -1, "addi32r", "add", 32,
+    { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* add $rd6,$rn6,$simm11 */
+  {
+    -1, "addi32m", "add", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub $rd,$rn,$simm3 */
+  {
+    -1, "subir", "sub", 16,
+    { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub $rd6,$rn6,$simm11 */
+  {
+    -1, "subi32r", "sub", 32,
+    { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* sub $rd6,$rn6,$simm11 */
+  {
+    -1, "subi32m", "sub", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr.l $rd6,$rn6,$rm6 */
+  {
+    -1, "asr.l", "asr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr.l $rd6,$rn6,$rm6 */
+  {
+    -1, "lsr.l", "lsr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl.l $rd6,$rn6,$rm6 */
+  {
+    -1, "lsl.l", "lsl.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsr.l $rd6,$rn6,$shift */
+  {
+    -1, "lsri32.l", "lsr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lsl.l $rd6,$rn6,$shift */
+  {
+    -1, "lsli32.l", "lsl.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* asr.l $rd6,$rn6,$shift */
+  {
+    -1, "asri32.l", "asr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* bitr.l $rd6,$rn6 */
+  {
+    -1, "bitrl", "bitr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fext.l $rd6,$rn6,$rm6 */
+  {
+    -1, "fext.l", "fext.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fdep.l $rd6,$rn6,$rm6 */
+  {
+    -1, "fdep.l", "fdep.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* lfsr.l $rd6,$rn6,$rm6 */
+  {
+    -1, "lfsr.l", "lfsr.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov $rd,$imm8 */
+  {
+    -1, "mov8r", "mov", 16,
+    { 0|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* mov $rd6,$imm16 */
+  {
+    -1, "mov16r", "mov", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* movt.l $rd6,$imm16 */
+  {
+    -1, "movtl", "movt.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* iadd $rd,$rn,$rm */
+  {
+    -1, "i_addf16", "iadd", 16,
+    { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fadd.l $rd6,$rn6,$rm6 */
+  {
+    -1, "f_addf32.l", "fadd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* iadd $rd6,$rn6,$rm6 */
+  {
+    -1, "i_addf32", "iadd", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* iadd.l $rd6,$rn6,$rm6 */
+  {
+    -1, "i_addf32.l", "iadd.l", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* isub $rd,$rn,$rm */
+  {
+    -1, "i_subf16", "isub", 16,
+    { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fsub.l $rd6,$rn6,$rm6 */
+  {
+    -1, "f_subf32.l", "fsub.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* isub $rd6,$rn6,$rm6 */
+  {
+    -1, "i_subf32", "isub", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* isub.l $rd6,$rn6,$rm6 */
+  {
+    -1, "i_subf32.l", "isub.l", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imul $rd,$rn,$rm */
+  {
+    -1, "i_mulf16", "imul", 16,
+    { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmul.l $rd6,$rn6,$rm6 */
+  {
+    -1, "f_mulf32.l", "fmul.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imul $rd6,$rn6,$rm6 */
+  {
+    -1, "i_mulf32", "imul", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imul.l $rd6,$rn6,$rm6 */
+  {
+    -1, "i_mulf32.l", "imul.l", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imadd $rd,$rn,$rm */
+  {
+    -1, "i_maddf16", "imadd", 16,
+    { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmadd.l $rd6,$rn6,$rm6 */
+  {
+    -1, "f_maddf32.l", "fmadd.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imadd $rd6,$rn6,$rm6 */
+  {
+    -1, "i_maddf32", "imadd", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imadd.l $rd6,$rn6,$rm6 */
+  {
+    -1, "i_maddf32.l", "imadd.l", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imsub $rd,$rn,$rm */
+  {
+    -1, "i_msubf16", "imsub", 16,
+    { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fmsub.l $rd6,$rn6,$rm6 */
+  {
+    -1, "f_msubf32.l", "fmsub.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imsub $rd6,$rn6,$rm6 */
+  {
+    -1, "i_msubf32", "imsub", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* imsub.l $rd6,$rn6,$rm6 */
+  {
+    -1, "i_msubf32.l", "imsub.l", 32,
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fabs.l $rd6,$rn6 */
+  {
+    -1, "f_absf32.l", "fabs.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* float.l $rd6,$rn6 */
+  {
+    -1, "f_loatf32.l", "float.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fix.l $rd6,$rn6 */
+  {
+    -1, "f_ixf32.l", "fix.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* frecip.l $frd6,$frn6 */
+  {
+    -1, "f_recipf32.l", "frecip.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+/* fsqrt.l $frd6,$frn6 */
+  {
+    -1, "f_sqrtf32.l", "fsqrt.l", 32,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
+  },
+};
+
+/* The macro instruction opcode table.  */
+
+static const CGEN_OPCODE epiphany_cgen_macro_insn_opcode_table[] =
+{
+/* beq $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_beq16r, { 0x0 }
+  },
+/* beq $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_beq32r, { 0x8 }
+  },
+/* bne $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bne16r, { 0x10 }
+  },
+/* bne $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bne32r, { 0x18 }
+  },
+/* bgtu $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bgtu16r, { 0x20 }
+  },
+/* bgtu $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bgtu32r, { 0x28 }
+  },
+/* bgteu $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bgteu16r, { 0x30 }
+  },
+/* bgteu $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bgteu32r, { 0x38 }
+  },
+/* blteu $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_blteu16r, { 0x40 }
+  },
+/* blteu $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_blteu32r, { 0x48 }
+  },
+/* bltu $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bltu16r, { 0x50 }
+  },
+/* bltu $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bltu32r, { 0x58 }
+  },
+/* bgt $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bgt16r, { 0x60 }
+  },
+/* bgt $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bgt32r, { 0x68 }
+  },
+/* bgte $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bgte16r, { 0x70 }
+  },
+/* bgte $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bgte32r, { 0x78 }
+  },
+/* blt $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_blt16r, { 0x80 }
+  },
+/* blt $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_blt32r, { 0x88 }
+  },
+/* blte $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_blte16r, { 0x90 }
+  },
+/* blte $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_blte32r, { 0x98 }
+  },
+/* bbeq $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bbeq16r, { 0xa0 }
+  },
+/* bbeq $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bbeq32r, { 0xa8 }
+  },
+/* bbne $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bbne16r, { 0xb0 }
+  },
+/* bbne $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bbne32r, { 0xb8 }
+  },
+/* bblt $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bblt16r, { 0xc0 }
+  },
+/* bblt $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bblt32r, { 0xc8 }
+  },
+/* bblte $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bblte16r, { 0xd0 }
+  },
+/* bblte $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_bblte32r, { 0xd8 }
+  },
+/* b $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_b16r, { 0xe0 }
+  },
+/* b $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_b32r, { 0xe8 }
+  },
+/* bl $simm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM8), 0 } },
+    & ifmt_bl16r, { 0xf0 }
+  },
+/* bl $simm24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SIMM24), 0 } },
+    & ifmt_blr, { 0xf8 }
+  },
+/* ldrb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrbx, { 0x9 }
+  },
+/* ldrb.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrbp, { 0xd }
+  },
+/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrbd, { 0xc }
+  },
+/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrbdpm, { 0x200000c }
+  },
+/* ldrb $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_ldrbds0, { 0x4 }
+  },
+/* ldrb $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrbdl0, { 0xc }
+  },
+/* ldrb.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrbdl0_l, { 0xc }
+  },
+/* ldrh.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrhx, { 0x29 }
+  },
+/* ldrh.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrhp, { 0x2d }
+  },
+/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrhd, { 0x2c }
+  },
+/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrhdpm, { 0x200002c }
+  },
+/* ldrh $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_ldrhds0, { 0x24 }
+  },
+/* ldrh $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrhdl0, { 0x2c }
+  },
+/* ldrh.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrhdl0_l, { 0x2c }
+  },
+/* ldr.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrx, { 0x49 }
+  },
+/* ldr.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrp, { 0x4d }
+  },
+/* ldr.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrd, { 0x4c }
+  },
+/* ldr.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrdpm, { 0x200004c }
+  },
+/* ldr $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_ldrds0, { 0x44 }
+  },
+/* ldr $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrdl0, { 0x4c }
+  },
+/* ldr.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrdl0_l, { 0x4c }
+  },
+/* ldrd.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_ldrdx, { 0x69 }
+  },
+/* ldrd.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_ldrdp, { 0x6d }
+  },
+/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_ldrdd, { 0x6c }
+  },
+/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_ldrddpm, { 0x200006c }
+  },
+/* ldrd $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_ldrdds0, { 0x64 }
+  },
+/* ldrd $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrddl0, { 0x6c }
+  },
+/* ldrd.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_ldrddl0_l, { 0x6c }
+  },
+/* testsetb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_testsetbt_l, { 0x200009 }
+  },
+/* testseth.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_testsetht_l, { 0x200029 }
+  },
+/* testset.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_testsett_l, { 0x200049 }
+  },
+/* strb.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_strbx_l, { 0x19 }
+  },
+/* strb.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_strbp_l, { 0x1d }
+  },
+/* strb.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_strbd_l, { 0x1c }
+  },
+/* strb.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_strbdpm_l, { 0x200001c }
+  },
+/* strb $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_strbds0, { 0x14 }
+  },
+/* strb $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strbdl0, { 0x1c }
+  },
+/* strb.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strbdl0_l, { 0x1c }
+  },
+/* strh.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_strhx_l, { 0x39 }
+  },
+/* strh.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_strhp_l, { 0x3d }
+  },
+/* strh.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_strhd_l, { 0x3c }
+  },
+/* strh.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_strhdpm_l, { 0x200003c }
+  },
+/* strh $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_strhds0, { 0x34 }
+  },
+/* strh $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strhdl0, { 0x3c }
+  },
+/* strh.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strhdl0_l, { 0x3c }
+  },
+/* str.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_strx_l, { 0x59 }
+  },
+/* str.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_strp_l, { 0x5d }
+  },
+/* str.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_strd_l, { 0x5c }
+  },
+/* str.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_strdpm_l, { 0x200005c }
+  },
+/* str $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_strds0, { 0x54 }
+  },
+/* str $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strdl0, { 0x5c }
+  },
+/* str.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strdl0_l, { 0x5c }
+  },
+/* strd.l $rd6,[$rn6,$direction$rm6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } },
+    & ifmt_strdx_l, { 0x79 }
+  },
+/* strd.l $rd6,[$rn6],$direction$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } },
+    & ifmt_strdp_l, { 0x7d }
+  },
+/* strd.l $rd6,[$rn6,$dpmi$disp11] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } },
+    & ifmt_strdd_l, { 0x7c }
+  },
+/* strd.l $rd6,[$rn6],$dpmi$disp11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } },
+    & ifmt_strddpm_l, { 0x200007c }
+  },
+/* strd $rd,[$rn] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } },
+    & ifmt_strdds0, { 0x74 }
+  },
+/* strd $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strddl0, { 0x7c }
+  },
+/* strd.l $rd6,[$rn6] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } },
+    & ifmt_strddl0_l, { 0x7c }
+  },
+/* moveq.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lEQ, { 0x2000f }
+  },
+/* movne.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lNE, { 0x2001f }
+  },
+/* movgtu.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lGTU, { 0x2002f }
+  },
+/* movgteu.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lGTEU, { 0x2003f }
+  },
+/* movlteu.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lLTEU, { 0x2004f }
+  },
+/* movltu.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lLTU, { 0x2005f }
+  },
+/* movgt.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lGT, { 0x2006f }
+  },
+/* movgte.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lGTE, { 0x2007f }
+  },
+/* movlt.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lLT, { 0x2008f }
+  },
+/* movlte.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lLTE, { 0x2009f }
+  },
+/* mov.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lB, { 0x200ef }
+  },
+/* movbeq.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lBEQ, { 0x200af }
+  },
+/* movbne.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lBNE, { 0x200bf }
+  },
+/* movblt.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lBLT, { 0x200cf }
+  },
+/* movblte.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_cmov_lBLTE, { 0x200df }
+  },
+/* movts.l $sn6,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } },
+    & ifmt_movts_l6, { 0x2010f }
+  },
+/* movts.l $sndma,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } },
+    & ifmt_movts_ldma, { 0x12010f }
+  },
+/* movts.l $snmem,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } },
+    & ifmt_movts_lmem, { 0x22010f }
+  },
+/* movts.l $snmesh,$rd6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } },
+    & ifmt_movts_lmesh, { 0x32010f }
+  },
+/* movfs.l $rd6,$sn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } },
+    & ifmt_movfs_l6, { 0x2011f }
+  },
+/* movfs.l $rd6,$sndma */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } },
+    & ifmt_movfs_ldma, { 0x12011f }
+  },
+/* movfs.l $rd6,$snmem */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } },
+    & ifmt_movfs_lmem, { 0x22011f }
+  },
+/* movfs.l $rd6,$snmesh */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } },
+    & ifmt_movfs_lmesh, { 0x32011f }
+  },
+/* add.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_add_l, { 0xa001f }
+  },
+/* sub.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_sub_l, { 0xa003f }
+  },
+/* and.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_and_l, { 0xa005f }
+  },
+/* orr.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_orr_l, { 0xa007f }
+  },
+/* eor.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_eor_l, { 0xa000f }
+  },
+/* add $rd,$rn,$simm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+    & ifmt_addir, { 0x13 }
+  },
+/* add $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_addi32r, { 0x1b }
+  },
+/* add $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_addi32m, { 0x1b }
+  },
+/* sub $rd,$rn,$simm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } },
+    & ifmt_subir, { 0x33 }
+  },
+/* sub $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_subi32r, { 0x3b }
+  },
+/* sub $rd6,$rn6,$simm11 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } },
+    & ifmt_subi32m, { 0x3b }
+  },
+/* asr.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_asr_l, { 0xa006f }
+  },
+/* lsr.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_lsr_l, { 0xa004f }
+  },
+/* lsl.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_lsl_l, { 0xa002f }
+  },
+/* lsr.l $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_lsri32_l, { 0x6000f }
+  },
+/* lsl.l $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_lsli32_l, { 0x6001f }
+  },
+/* asr.l $rd6,$rn6,$shift */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } },
+    & ifmt_asri32_l, { 0xe000f }
+  },
+/* bitr.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_bitrl, { 0xe001f }
+  },
+/* fext.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_fext_l, { 0x1a000f }
+  },
+/* fdep.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_fdep_l, { 0x1a001f }
+  },
+/* lfsr.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_lfsr_l, { 0x1a002f }
+  },
+/* mov $rd,$imm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } },
+    & ifmt_mov8r, { 0x3 }
+  },
+/* mov $rd6,$imm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+    & ifmt_mov16r, { 0x2000b }
+  },
+/* movt.l $rd6,$imm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } },
+    & ifmt_movtl, { 0x1002000b }
+  },
+/* iadd $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_i_addf16, { 0x7 }
+  },
+/* fadd.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_f_addf32_l, { 0x7000f }
+  },
+/* iadd $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_addf32, { 0x7000f }
+  },
+/* iadd.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_addf32_l, { 0x7000f }
+  },
+/* isub $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_i_subf16, { 0x17 }
+  },
+/* fsub.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_f_subf32_l, { 0x7001f }
+  },
+/* isub $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_subf32, { 0x7001f }
+  },
+/* isub.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_subf32_l, { 0x7001f }
+  },
+/* imul $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_i_mulf16, { 0x27 }
+  },
+/* fmul.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_f_mulf32_l, { 0x7002f }
+  },
+/* imul $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_mulf32, { 0x7002f }
+  },
+/* imul.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_mulf32_l, { 0x7002f }
+  },
+/* imadd $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_i_maddf16, { 0x37 }
+  },
+/* fmadd.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_f_maddf32_l, { 0x7003f }
+  },
+/* imadd $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_maddf32, { 0x7003f }
+  },
+/* imadd.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_maddf32_l, { 0x7003f }
+  },
+/* imsub $rd,$rn,$rm */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } },
+    & ifmt_i_msubf16, { 0x47 }
+  },
+/* fmsub.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_f_msubf32_l, { 0x7004f }
+  },
+/* imsub $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_msubf32, { 0x7004f }
+  },
+/* imsub.l $rd6,$rn6,$rm6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } },
+    & ifmt_i_msubf32_l, { 0x7004f }
+  },
+/* fabs.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_absf32_l, { 0x7007f }
+  },
+/* float.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_loatf32_l, { 0x7005f }
+  },
+/* fix.l $rd6,$rn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } },
+    & ifmt_f_ixf32_l, { 0x7006f }
+  },
+/* frecip.l $frd6,$frn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+    & ifmt_f_recipf32_l, { 0x17000f }
+  },
+/* fsqrt.l $frd6,$frn6 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } },
+    & ifmt_f_sqrtf32_l, { 0x17001f }
+  },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
+
+static int
+asm_hash_insn_p (insn)
+     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+  return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+     const CGEN_INSN *insn;
+{
+  /* If building the hash table and the NO-DIS attribute is present,
+     ignore.  */
+  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+    return 0;
+  return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+   but while this is under development we do.
+   BUFFER is a pointer to the bytes of the insn, target order.
+   VALUE is the first base_insn_bitsize bits as an int in host order.  */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
+
+static unsigned int
+asm_hash_insn (mnem)
+     const char * mnem;
+{
+  return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+   VALUE is the first base_insn_bitsize bits as an int in host order.  */
+
+static unsigned int
+dis_hash_insn (buf, value)
+     const char * buf ATTRIBUTE_UNUSED;
+     CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+  return CGEN_DIS_HASH (buf, value);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+  CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+   This plugs the opcode entries and macro instructions into the cpu table.  */
+
+void
+epiphany_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+{
+  int i;
+  int num_macros = (sizeof (epiphany_cgen_macro_insn_table) /
+		    sizeof (epiphany_cgen_macro_insn_table[0]));
+  const CGEN_IBASE *ib = & epiphany_cgen_macro_insn_table[0];
+  const CGEN_OPCODE *oc = & epiphany_cgen_macro_insn_opcode_table[0];
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
+  /* This test has been added to avoid a warning generated
+     if memset is called with a third argument of value zero.  */
+  if (num_macros >= 1)
+    memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+  for (i = 0; i < num_macros; ++i)
+    {
+      insns[i].base = &ib[i];
+      insns[i].opcode = &oc[i];
+      epiphany_cgen_build_insn_regex (& insns[i]);
+    }
+  cd->macro_insn_table.init_entries = insns;
+  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->macro_insn_table.num_init_entries = num_macros;
+
+  oc = & epiphany_cgen_insn_opcode_table[0];
+  insns = (CGEN_INSN *) cd->insn_table.init_entries;
+  for (i = 0; i < MAX_INSNS; ++i)
+    {
+      insns[i].opcode = &oc[i];
+      epiphany_cgen_build_insn_regex (& insns[i]);
+    }
+
+  cd->sizeof_fields = sizeof (CGEN_FIELDS);
+  cd->set_fields_bitsize = set_fields_bitsize;
+
+  cd->asm_hash_p = asm_hash_insn_p;
+  cd->asm_hash = asm_hash_insn;
+  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+  cd->dis_hash_p = dis_hash_insn_p;
+  cd->dis_hash = dis_hash_insn;
+  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
diff --git a/opcodes/epiphany-opc.h b/opcodes/epiphany-opc.h
new file mode 100644
index 0000000..d3f9348
--- /dev/null
+++ b/opcodes/epiphany-opc.h
@@ -0,0 +1,226 @@
+/* Instruction opcode header for epiphany.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef EPIPHANY_OPC_H
+#define EPIPHANY_OPC_H
+
+/* -- opc.h */
+
+/* enumerate relaxation types for gas. */
+typedef enum epiphany_relax_types
+{
+  EPIPHANY_RELAX_NONE=0,
+  EPIPHANY_RELAX_NEED_RELAXING,
+
+  EPIPHANY_RELAX_BRANCH_SHORT,	/* Fits into +127..-128 */
+  EPIPHANY_RELAX_BRANCH_LONG,	/* b/bl/b<cond> +-2*16 */
+
+  EPIPHANY_RELAX_ARITH_SIMM3,	/* add/sub -7..3 */
+  EPIPHANY_RELAX_ARITH_SIMM11,	/* add/sub -2**11-1 .. 2**10-1 */
+
+  EPIPHANY_RELAX_MOV_IMM8,		/* mov r,imm8 */
+  EPIPHANY_RELAX_MOV_IMM16,	/* mov r,imm16 */
+
+  EPIPHANY_RELAX_LDST_IMM3,	/* (ldr|str)* r,[r,disp3] */
+  EPIPHANY_RELAX_LDST_IMM11	/* (ldr|str)* r,[r,disp11] */
+
+} EPIPHANY_RELAX_TYPES;
+
+/* Override disassembly hashing... */
+
+/* Can only depend on instruction having 4 decode bits which gets us to the
+   major groups of 16/32 instructions. */
+#undef CGEN_DIS_HASH_SIZE
+#if 1
+
+/* hash code on the 4 LSBs */
+#define CGEN_DIS_HASH_SIZE 16
+
+#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
+#else
+#define CGEN_DIS_HASH_SIZE 1
+#define CGEN_DIS_HASH(buf, value) 0
+#endif
+
+extern const char * parse_shortregs (CGEN_CPU_DESC cd,
+				     const char ** strp,
+				     CGEN_KEYWORD * keywords,
+				     long * valuep);
+
+extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
+				       const char ** strp,
+				       int opindex,
+				       int opinfo,
+				       enum cgen_parse_operand_result * resultp,
+				       unsigned long * valuep);
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+
+/* -- opc.c */
+/* Enum declaration for epiphany instruction types.  */
+typedef enum cgen_insn_type {
+  EPIPHANY_INSN_INVALID, EPIPHANY_INSN_BEQ16, EPIPHANY_INSN_BEQ, EPIPHANY_INSN_BNE16
+ , EPIPHANY_INSN_BNE, EPIPHANY_INSN_BGTU16, EPIPHANY_INSN_BGTU, EPIPHANY_INSN_BGTEU16
+ , EPIPHANY_INSN_BGTEU, EPIPHANY_INSN_BLTEU16, EPIPHANY_INSN_BLTEU, EPIPHANY_INSN_BLTU16
+ , EPIPHANY_INSN_BLTU, EPIPHANY_INSN_BGT16, EPIPHANY_INSN_BGT, EPIPHANY_INSN_BGTE16
+ , EPIPHANY_INSN_BGTE, EPIPHANY_INSN_BLT16, EPIPHANY_INSN_BLT, EPIPHANY_INSN_BLTE16
+ , EPIPHANY_INSN_BLTE, EPIPHANY_INSN_BBEQ16, EPIPHANY_INSN_BBEQ, EPIPHANY_INSN_BBNE16
+ , EPIPHANY_INSN_BBNE, EPIPHANY_INSN_BBLT16, EPIPHANY_INSN_BBLT, EPIPHANY_INSN_BBLTE16
+ , EPIPHANY_INSN_BBLTE, EPIPHANY_INSN_B16, EPIPHANY_INSN_B, EPIPHANY_INSN_BL16
+ , EPIPHANY_INSN_BL, EPIPHANY_INSN_JR16, EPIPHANY_INSN_RTS, EPIPHANY_INSN_JR
+ , EPIPHANY_INSN_JALR16, EPIPHANY_INSN_JALR, EPIPHANY_INSN_LDRBX16_S, EPIPHANY_INSN_LDRBP16_S
+ , EPIPHANY_INSN_LDRBX_L, EPIPHANY_INSN_LDRBP_L, EPIPHANY_INSN_LDRBD16_S, EPIPHANY_INSN_LDRBD_L
+ , EPIPHANY_INSN_LDRBDPM_L, EPIPHANY_INSN_LDRHX16_S, EPIPHANY_INSN_LDRHP16_S, EPIPHANY_INSN_LDRHX_L
+ , EPIPHANY_INSN_LDRHP_L, EPIPHANY_INSN_LDRHD16_S, EPIPHANY_INSN_LDRHD_L, EPIPHANY_INSN_LDRHDPM_L
+ , EPIPHANY_INSN_LDRX16_S, EPIPHANY_INSN_LDRP16_S, EPIPHANY_INSN_LDRX_L, EPIPHANY_INSN_LDRP_L
+ , EPIPHANY_INSN_LDRD16_S, EPIPHANY_INSN_LDRD_L, EPIPHANY_INSN_LDRDPM_L, EPIPHANY_INSN_LDRDX16_S
+ , EPIPHANY_INSN_LDRDP16_S, EPIPHANY_INSN_LDRDX_L, EPIPHANY_INSN_LDRDP_L, EPIPHANY_INSN_LDRDD16_S
+ , EPIPHANY_INSN_LDRDD_L, EPIPHANY_INSN_LDRDDPM_L, EPIPHANY_INSN_TESTSETBT, EPIPHANY_INSN_TESTSETHT
+ , EPIPHANY_INSN_TESTSETT, EPIPHANY_INSN_STRBX16, EPIPHANY_INSN_STRBX, EPIPHANY_INSN_STRBP16
+ , EPIPHANY_INSN_STRBP, EPIPHANY_INSN_STRBD16, EPIPHANY_INSN_STRBD, EPIPHANY_INSN_STRBDPM
+ , EPIPHANY_INSN_STRHX16, EPIPHANY_INSN_STRHX, EPIPHANY_INSN_STRHP16, EPIPHANY_INSN_STRHP
+ , EPIPHANY_INSN_STRHD16, EPIPHANY_INSN_STRHD, EPIPHANY_INSN_STRHDPM, EPIPHANY_INSN_STRX16
+ , EPIPHANY_INSN_STRX, EPIPHANY_INSN_STRP16, EPIPHANY_INSN_STRP, EPIPHANY_INSN_STRD16
+ , EPIPHANY_INSN_STRD, EPIPHANY_INSN_STRDPM, EPIPHANY_INSN_STRDX16, EPIPHANY_INSN_STRDX
+ , EPIPHANY_INSN_STRDP16, EPIPHANY_INSN_STRDP, EPIPHANY_INSN_STRDD16, EPIPHANY_INSN_STRDD
+ , EPIPHANY_INSN_STRDDPM, EPIPHANY_INSN_CMOV16EQ, EPIPHANY_INSN_CMOVEQ, EPIPHANY_INSN_CMOV16NE
+ , EPIPHANY_INSN_CMOVNE, EPIPHANY_INSN_CMOV16GTU, EPIPHANY_INSN_CMOVGTU, EPIPHANY_INSN_CMOV16GTEU
+ , EPIPHANY_INSN_CMOVGTEU, EPIPHANY_INSN_CMOV16LTEU, EPIPHANY_INSN_CMOVLTEU, EPIPHANY_INSN_CMOV16LTU
+ , EPIPHANY_INSN_CMOVLTU, EPIPHANY_INSN_CMOV16GT, EPIPHANY_INSN_CMOVGT, EPIPHANY_INSN_CMOV16GTE
+ , EPIPHANY_INSN_CMOVGTE, EPIPHANY_INSN_CMOV16LT, EPIPHANY_INSN_CMOVLT, EPIPHANY_INSN_CMOV16LTE
+ , EPIPHANY_INSN_CMOVLTE, EPIPHANY_INSN_CMOV16B, EPIPHANY_INSN_CMOVB, EPIPHANY_INSN_CMOV16BEQ
+ , EPIPHANY_INSN_CMOVBEQ, EPIPHANY_INSN_CMOV16BNE, EPIPHANY_INSN_CMOVBNE, EPIPHANY_INSN_CMOV16BLT
+ , EPIPHANY_INSN_CMOVBLT, EPIPHANY_INSN_CMOV16BLTE, EPIPHANY_INSN_CMOVBLTE, EPIPHANY_INSN_MOVTS16
+ , EPIPHANY_INSN_MOVTS6, EPIPHANY_INSN_MOVTSDMA, EPIPHANY_INSN_MOVTSMEM, EPIPHANY_INSN_MOVTSMESH
+ , EPIPHANY_INSN_MOVFS16, EPIPHANY_INSN_MOVFS6, EPIPHANY_INSN_MOVFSDMA, EPIPHANY_INSN_MOVFSMEM
+ , EPIPHANY_INSN_MOVFSMESH, EPIPHANY_INSN_NOP, EPIPHANY_INSN_SNOP, EPIPHANY_INSN_UNIMPL
+ , EPIPHANY_INSN_IDLE, EPIPHANY_INSN_BKPT, EPIPHANY_INSN_MBKPT, EPIPHANY_INSN_RTI
+ , EPIPHANY_INSN_WAND, EPIPHANY_INSN_SYNC, EPIPHANY_INSN_GIEN, EPIPHANY_INSN_GIDIS
+ , EPIPHANY_INSN_SWI_NUM, EPIPHANY_INSN_SWI, EPIPHANY_INSN_TRAP16, EPIPHANY_INSN_ADD16
+ , EPIPHANY_INSN_ADD, EPIPHANY_INSN_SUB16, EPIPHANY_INSN_SUB, EPIPHANY_INSN_AND16
+ , EPIPHANY_INSN_AND, EPIPHANY_INSN_ORR16, EPIPHANY_INSN_ORR, EPIPHANY_INSN_EOR16
+ , EPIPHANY_INSN_EOR, EPIPHANY_INSN_ADDI16, EPIPHANY_INSN_ADDI, EPIPHANY_INSN_SUBI16
+ , EPIPHANY_INSN_SUBI, EPIPHANY_INSN_ASR16, EPIPHANY_INSN_ASR, EPIPHANY_INSN_LSR16
+ , EPIPHANY_INSN_LSR, EPIPHANY_INSN_LSL16, EPIPHANY_INSN_LSL, EPIPHANY_INSN_LSRI16
+ , EPIPHANY_INSN_LSRI32, EPIPHANY_INSN_LSLI16, EPIPHANY_INSN_LSLI32, EPIPHANY_INSN_ASRI16
+ , EPIPHANY_INSN_ASRI32, EPIPHANY_INSN_BITR16, EPIPHANY_INSN_BITR, EPIPHANY_INSN_FEXT
+ , EPIPHANY_INSN_FDEP, EPIPHANY_INSN_LFSR, EPIPHANY_INSN_MOV8, EPIPHANY_INSN_MOV16
+ , EPIPHANY_INSN_MOVT, EPIPHANY_INSN_F_ADDF16, EPIPHANY_INSN_F_ADDF32, EPIPHANY_INSN_F_SUBF16
+ , EPIPHANY_INSN_F_SUBF32, EPIPHANY_INSN_F_MULF16, EPIPHANY_INSN_F_MULF32, EPIPHANY_INSN_F_MADDF16
+ , EPIPHANY_INSN_F_MADDF32, EPIPHANY_INSN_F_MSUBF16, EPIPHANY_INSN_F_MSUBF32, EPIPHANY_INSN_F_ABSF16
+ , EPIPHANY_INSN_F_ABSF32, EPIPHANY_INSN_F_LOATF16, EPIPHANY_INSN_F_LOATF32, EPIPHANY_INSN_F_IXF16
+ , EPIPHANY_INSN_F_IXF32, EPIPHANY_INSN_F_RECIPF32, EPIPHANY_INSN_F_SQRTF32
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID EPIPHANY_INSN_INVALID
+
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) EPIPHANY_INSN_F_SQRTF32 + 1)
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields
+{
+  int length;
+  long f_nil;
+  long f_anyof;
+  long f_opc;
+  long f_opc_4_1;
+  long f_opc_6_3;
+  long f_opc_8_5;
+  long f_opc_19_4;
+  long f_condcode;
+  long f_secondary_ccs;
+  long f_shift;
+  long f_wordsize;
+  long f_store;
+  long f_opc_8_1;
+  long f_opc_31_32;
+  long f_simm8;
+  long f_simm24;
+  long f_sdisp3;
+  long f_disp3;
+  long f_disp8;
+  long f_imm8;
+  long f_imm_27_8;
+  long f_addsubx;
+  long f_subd;
+  long f_pm;
+  long f_rm;
+  long f_rn;
+  long f_rd;
+  long f_rm_x;
+  long f_rn_x;
+  long f_rd_x;
+  long f_dc_9_1;
+  long f_sn;
+  long f_sd;
+  long f_sn_x;
+  long f_sd_x;
+  long f_dc_7_4;
+  long f_trap_swi_9_1;
+  long f_gien_gidis_9_1;
+  long f_dc_15_3;
+  long f_dc_15_7;
+  long f_dc_15_6;
+  long f_trap_num;
+  long f_dc_20_1;
+  long f_dc_21_1;
+  long f_dc_21_2;
+  long f_dc_22_3;
+  long f_dc_22_2;
+  long f_dc_22_1;
+  long f_dc_25_6;
+  long f_dc_25_4;
+  long f_dc_25_2;
+  long f_dc_25_1;
+  long f_dc_28_1;
+  long f_dc_31_3;
+  long f_disp11;
+  long f_sdisp11;
+  long f_imm16;
+  long f_rd6;
+  long f_rn6;
+  long f_rm6;
+  long f_sd6;
+  long f_sn6;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* EPIPHANY_OPC_H */
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index bf9bf04..5c54192 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -24,6 +24,13 @@ dis-buf.c
 dis-init.c
 disassemble.c
 dlx-dis.c
+epiphany-asm.c
+epiphany-desc.c
+epiphany-desc.h
+epiphany-dis.c
+epiphany-ibld.c
+epiphany-opc.c
+epiphany-opc.h
 fr30-asm.c
 fr30-desc.c
 fr30-desc.h
@@ -121,6 +128,7 @@ mep-opc.c
 mep-opc.h
 microblaze-dis.c
 microblaze-opc.h
+micromips-opc.c
 mips-dis.c
 mips-opc.c
 mips16-opc.c
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index ecdb232..90a4bb5 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2011-06-02 14:30+0100\n"
+"POT-Creation-Date: 2011-10-25 11:34+0100\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -111,23 +111,23 @@ msgstr ""
 msgid "must specify .jd or no nullify suffix"
 msgstr ""
 
-#: arm-dis.c:1994
+#: arm-dis.c:2000
 msgid "<illegal precision>"
 msgstr ""
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:4376
+#: arm-dis.c:4395
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:4384
+#: arm-dis.c:4403
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:4976
+#: arm-dis.c:4995
 #, c-format
 msgid ""
 "\n"
@@ -135,25 +135,25 @@ msgid ""
 "the -M switch:\n"
 msgstr ""
 
-#: avr-dis.c:115 avr-dis.c:135
+#: avr-dis.c:115 avr-dis.c:136
 #, c-format
 msgid "undefined"
 msgstr ""
 
-#: avr-dis.c:197
+#: avr-dis.c:198
 #, c-format
 msgid "Internal disassembler error"
 msgstr ""
 
-#: avr-dis.c:250
+#: avr-dis.c:251
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201
-#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201
-#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201
-#: xstormy16-ibld.c:201
+#: cgen-asm.c:336 epiphany-ibld.c:201 fr30-ibld.c:201 frv-ibld.c:201
+#: ip2k-ibld.c:201 iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201
+#: m32r-ibld.c:201 mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201
+#: xc16x-ibld.c:201 xstormy16-ibld.c:201
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr ""
@@ -179,36 +179,58 @@ msgstr ""
 msgid "Address 0x%s is out of bounds.\n"
 msgstr ""
 
-#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
-msgid "Register number is not valid"
+#: epiphany-asm.c:68
+msgid "register unavailable for short instructions"
 msgstr ""
 
-#: fr30-asm.c:95
-msgid "Register must be between r0 and r7"
+#: epiphany-asm.c:115
+msgid "register name used as immediate value"
 msgstr ""
 
-#: fr30-asm.c:97
-msgid "Register must be between r8 and r15"
+#. Don't treat "mov ip,ip" as a move-immediate.
+#: epiphany-asm.c:178 epiphany-asm.c:234
+msgid "register source in immediate move"
 msgstr ""
 
-#: fr30-asm.c:116 m32c-asm.c:910
-msgid "Register list is not valid"
+#: epiphany-asm.c:187
+msgid "byte relocation unsupported"
+msgstr ""
+
+#. -- assembler routines inserted here.
+#. -- asm.c
+#: epiphany-asm.c:193 frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95
+#: lm32-asm.c:127 lm32-asm.c:157 lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247
+#: m32c-asm.c:140 m32c-asm.c:235 m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355
+#: m32r-asm.c:53 mep-asm.c:241 mep-asm.c:259 mep-asm.c:274 mep-asm.c:289
+#: mep-asm.c:301 openrisc-asm.c:54
+msgid "missing `)'"
 msgstr ""
 
-#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
-#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595
-#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
+#: epiphany-asm.c:270
+msgid "ABORT: unknown operand"
+msgstr ""
+
+#: epiphany-asm.c:296
+msgid "Not a pc-relative address."
+msgstr ""
+
+#: epiphany-asm.c:455 fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511
+#: iq2000-asm.c:459 lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328
+#: mep-asm.c:1286 mt-asm.c:595 openrisc-asm.c:241 xc16x-asm.c:376
+#: xstormy16-asm.c:276
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr ""
 
-#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
-#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646
-#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
+#: epiphany-asm.c:506 fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562
+#: iq2000-asm.c:510 lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379
+#: mep-asm.c:1337 mt-asm.c:646 openrisc-asm.c:292 xc16x-asm.c:427
+#: xstormy16-asm.c:327
 msgid "missing mnemonic in syntax string"
 msgstr ""
 
 #. We couldn't parse it.
+#: epiphany-asm.c:641 epiphany-asm.c:645 epiphany-asm.c:734 epiphany-asm.c:841
 #: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449
 #: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701
 #: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649
@@ -224,116 +246,147 @@ msgstr ""
 msgid "unrecognized instruction"
 msgstr ""
 
-#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
-#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828
-#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
+#: epiphany-asm.c:688 fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744
+#: iq2000-asm.c:692 lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561
+#: mep-asm.c:1519 mt-asm.c:828 openrisc-asm.c:474 xc16x-asm.c:609
+#: xstormy16-asm.c:509
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr ""
 
-#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
-#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838
-#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
+#: epiphany-asm.c:698 fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754
+#: iq2000-asm.c:702 lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571
+#: mep-asm.c:1529 mt-asm.c:838 openrisc-asm.c:484 xc16x-asm.c:619
+#: xstormy16-asm.c:519
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr ""
 
-#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732
-#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868
-#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549
+#: epiphany-asm.c:728 fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784
+#: iq2000-asm.c:732 lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601
+#: mep-asm.c:1559 mt-asm.c:868 openrisc-asm.c:514 xc16x-asm.c:649
+#: xstormy16-asm.c:549
 msgid "junk at end of line"
 msgstr ""
 
-#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844
-#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980
-#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661
+#: epiphany-asm.c:840 fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896
+#: iq2000-asm.c:844 lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713
+#: mep-asm.c:1671 mt-asm.c:980 openrisc-asm.c:626 xc16x-asm.c:761
+#: xstormy16-asm.c:661
 msgid "unrecognized form of instruction"
 msgstr ""
 
-#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858
-#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994
-#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675
+#: epiphany-asm.c:854 fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910
+#: iq2000-asm.c:858 lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727
+#: mep-asm.c:1685 mt-asm.c:994 openrisc-asm.c:640 xc16x-asm.c:775
+#: xstormy16-asm.c:675
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr ""
 
-#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861
-#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997
-#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678
+#: epiphany-asm.c:857 fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913
+#: iq2000-asm.c:861 lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730
+#: mep-asm.c:1688 mt-asm.c:997 openrisc-asm.c:643 xc16x-asm.c:778
+#: xstormy16-asm.c:678
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr ""
 
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
-#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41
-#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
+#: epiphany-dis.c:41 fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41
+#: lm32-dis.c:41 m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277
+#: mt-dis.c:41 openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
 msgstr ""
 
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
-#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290
-#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168
+#: epiphany-dis.c:277 fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288
+#: iq2000-dis.c:189 lm32-dis.c:147 m32c-dis.c:891 m32r-dis.c:279
+#: mep-dis.c:1187 mt-dis.c:290 openrisc-dis.c:135 xc16x-dis.c:420
+#: xstormy16-dis.c:168
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164
-#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164
-#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164
+#: epiphany-ibld.c:164 fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164
+#: iq2000-ibld.c:164 lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164
+#: mep-ibld.c:164 mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164
+#: xstormy16-ibld.c:164
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr ""
 
-#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185
-#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185
-#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185
+#: epiphany-ibld.c:185 fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185
+#: iq2000-ibld.c:185 lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185
+#: mep-ibld.c:185 mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185
+#: xstormy16-ibld.c:185
 #, c-format
 msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
 msgstr ""
 
-#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710
-#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205
-#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675
+#: epiphany-ibld.c:872 fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604
+#: iq2000-ibld.c:710 lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662
+#: mep-ibld.c:1205 mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749
+#: xstormy16-ibld.c:675
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885
-#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804
-#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821
+#: epiphany-ibld.c:1166 fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679
+#: iq2000-ibld.c:885 lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799
+#: mep-ibld.c:1804 mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969
+#: xstormy16-ibld.c:821
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016
-#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274
-#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931
+#: epiphany-ibld.c:1309 fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753
+#: iq2000-ibld.c:1016 lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912
+#: mep-ibld.c:2274 mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190
+#: xstormy16-ibld.c:931
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129
-#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726
-#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023
+#: epiphany-ibld.c:1434 fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809
+#: iq2000-ibld.c:1129 lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007
+#: mep-ibld.c:2726 mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393
+#: xstormy16-ibld.c:1023
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249
-#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139
-#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122
+#: epiphany-ibld.c:1566 fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868
+#: iq2000-ibld.c:1249 lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108
+#: mep-ibld.c:3139 mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597
+#: xstormy16-ibld.c:1122
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359
-#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542
-#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211
+#: epiphany-ibld.c:1688 fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917
+#: iq2000-ibld.c:1359 lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199
+#: mep-ibld.c:3542 mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791
+#: xstormy16-ibld.c:1211
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr ""
 
+#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
+msgid "Register number is not valid"
+msgstr ""
+
+#: fr30-asm.c:95
+msgid "Register must be between r0 and r7"
+msgstr ""
+
+#: fr30-asm.c:97
+msgid "Register must be between r8 and r15"
+msgstr ""
+
+#: fr30-asm.c:116 m32c-asm.c:910
+msgid "Register list is not valid"
+msgstr ""
+
 #: frv-asm.c:608
 msgid "missing `]'"
 msgstr ""
@@ -350,15 +403,6 @@ msgstr ""
 msgid "register number must be even"
 msgstr ""
 
-#. -- assembler routines inserted here.
-#. -- asm.c
-#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
-#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235
-#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241
-#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
-msgid "missing `)'"
-msgstr ""
-
 #: h8300-dis.c:314
 #, c-format
 msgid "Hmmmm 0x%x"
@@ -380,11 +424,11 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:10774
+#: i386-dis.c:10504
 msgid "<internal disassembler error>"
 msgstr ""
 
-#: i386-dis.c:11071
+#: i386-dis.c:10801
 #, c-format
 msgid ""
 "\n"
@@ -393,126 +437,126 @@ msgid ""
 "with the -M switch (multiple options should be separated by commas):\n"
 msgstr ""
 
-#: i386-dis.c:11075
+#: i386-dis.c:10805
 #, c-format
 msgid "  x86-64      Disassemble in 64bit mode\n"
 msgstr ""
 
-#: i386-dis.c:11076
+#: i386-dis.c:10806
 #, c-format
 msgid "  i386        Disassemble in 32bit mode\n"
 msgstr ""
 
-#: i386-dis.c:11077
+#: i386-dis.c:10807
 #, c-format
 msgid "  i8086       Disassemble in 16bit mode\n"
 msgstr ""
 
-#: i386-dis.c:11078
+#: i386-dis.c:10808
 #, c-format
 msgid "  att         Display instruction in AT&T syntax\n"
 msgstr ""
 
-#: i386-dis.c:11079
+#: i386-dis.c:10809
 #, c-format
 msgid "  intel       Display instruction in Intel syntax\n"
 msgstr ""
 
-#: i386-dis.c:11080
+#: i386-dis.c:10810
 #, c-format
 msgid ""
 "  att-mnemonic\n"
 "              Display instruction in AT&T mnemonic\n"
 msgstr ""
 
-#: i386-dis.c:11082
+#: i386-dis.c:10812
 #, c-format
 msgid ""
 "  intel-mnemonic\n"
 "              Display instruction in Intel mnemonic\n"
 msgstr ""
 
-#: i386-dis.c:11084
+#: i386-dis.c:10814
 #, c-format
 msgid "  addr64      Assume 64bit address size\n"
 msgstr ""
 
-#: i386-dis.c:11085
+#: i386-dis.c:10815
 #, c-format
 msgid "  addr32      Assume 32bit address size\n"
 msgstr ""
 
-#: i386-dis.c:11086
+#: i386-dis.c:10816
 #, c-format
 msgid "  addr16      Assume 16bit address size\n"
 msgstr ""
 
-#: i386-dis.c:11087
+#: i386-dis.c:10817
 #, c-format
 msgid "  data32      Assume 32bit data size\n"
 msgstr ""
 
-#: i386-dis.c:11088
+#: i386-dis.c:10818
 #, c-format
 msgid "  data16      Assume 16bit data size\n"
 msgstr ""
 
-#: i386-dis.c:11089
+#: i386-dis.c:10819
 #, c-format
 msgid "  suffix      Always display instruction suffix in AT&T syntax\n"
 msgstr ""
 
-#: i386-gen.c:467 ia64-gen.c:307
+#: i386-gen.c:483 ia64-gen.c:307
 #, c-format
 msgid "%s: Error: "
 msgstr ""
 
-#: i386-gen.c:599
+#: i386-gen.c:615
 #, c-format
 msgid "%s: %d: Unknown bitfield: %s\n"
 msgstr ""
 
-#: i386-gen.c:601
+#: i386-gen.c:617
 #, c-format
 msgid "Unknown bitfield: %s\n"
 msgstr ""
 
-#: i386-gen.c:657
+#: i386-gen.c:673
 #, c-format
 msgid "%s: %d: Missing `)' in bitfield: %s\n"
 msgstr ""
 
-#: i386-gen.c:922
+#: i386-gen.c:938
 #, c-format
 msgid "can't find i386-opc.tbl for reading, errno = %s\n"
 msgstr ""
 
-#: i386-gen.c:1053
+#: i386-gen.c:1069
 #, c-format
 msgid "can't find i386-reg.tbl for reading, errno = %s\n"
 msgstr ""
 
-#: i386-gen.c:1130
+#: i386-gen.c:1146
 #, c-format
 msgid "can't create i386-init.h, errno = %s\n"
 msgstr ""
 
-#: i386-gen.c:1219 ia64-gen.c:2820
+#: i386-gen.c:1235 ia64-gen.c:2820
 #, c-format
 msgid "unable to change directory to \"%s\", errno = %s\n"
 msgstr ""
 
-#: i386-gen.c:1226
+#: i386-gen.c:1242
 #, c-format
 msgid "%d unused bits in i386_cpu_flags.\n"
 msgstr ""
 
-#: i386-gen.c:1233
+#: i386-gen.c:1249
 #, c-format
 msgid "%d unused bits in i386_operand_type.\n"
 msgstr ""
 
-#: i386-gen.c:1247
+#: i386-gen.c:1263
 #, c-format
 msgid "can't create i386-tbl.h, errno = %s\n"
 msgstr ""
@@ -830,26 +874,41 @@ msgstr ""
 msgid "Value is not aligned enough"
 msgstr ""
 
-#: mips-dis.c:845
+#: mips-dis.c:947
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr ""
 
-#: mips-dis.c:1011
+#: mips-dis.c:1113
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr ""
 
-#: mips-dis.c:1371
+#: mips-dis.c:1485
 #, c-format
 msgid "# internal error, undefined modifier (%c)"
 msgstr ""
 
-#: mips-dis.c:1975
+#: mips-dis.c:2089
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr ""
 
-#: mips-dis.c:2213
+#: mips-dis.c:2664
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (+%c)"
+msgstr ""
+
+#: mips-dis.c:2894
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (m%c)"
+msgstr ""
+
+#: mips-dis.c:2904
+#, c-format
+msgid "# internal disassembler error, unrecognized modifier (%c)"
+msgstr ""
+
+#: mips-dis.c:3052
 #, c-format
 msgid ""
 "\n"
@@ -857,7 +916,7 @@ msgid ""
 "with the -M switch (multiple options should be separated by commas):\n"
 msgstr ""
 
-#: mips-dis.c:2217
+#: mips-dis.c:3056
 #, c-format
 msgid ""
 "\n"
@@ -865,7 +924,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:2221
+#: mips-dis.c:3060
 #, c-format
 msgid ""
 "\n"
@@ -873,7 +932,7 @@ msgid ""
 "                           Default: numeric.\n"
 msgstr ""
 
-#: mips-dis.c:2225
+#: mips-dis.c:3064
 #, c-format
 msgid ""
 "\n"
@@ -882,7 +941,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:2230
+#: mips-dis.c:3069
 #, c-format
 msgid ""
 "\n"
@@ -891,7 +950,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:2235
+#: mips-dis.c:3074
 #, c-format
 msgid ""
 "\n"
@@ -899,7 +958,7 @@ msgid ""
 "                           specified ABI.\n"
 msgstr ""
 
-#: mips-dis.c:2239
+#: mips-dis.c:3078
 #, c-format
 msgid ""
 "\n"
@@ -907,7 +966,7 @@ msgid ""
 "                           specified architecture.\n"
 msgstr ""
 
-#: mips-dis.c:2243
+#: mips-dis.c:3082
 #, c-format
 msgid ""
 "\n"
@@ -915,12 +974,12 @@ msgid ""
 "   "
 msgstr ""
 
-#: mips-dis.c:2248 mips-dis.c:2256 mips-dis.c:2258
+#: mips-dis.c:3087 mips-dis.c:3095 mips-dis.c:3097
 #, c-format
 msgid "\n"
 msgstr ""
 
-#: mips-dis.c:2250
+#: mips-dis.c:3089
 #, c-format
 msgid ""
 "\n"
@@ -995,43 +1054,51 @@ msgid ""
 "the -M switch:\n"
 msgstr ""
 
-#: ppc-opc.c:879 ppc-opc.c:907
+#: ppc-opc.c:906 ppc-opc.c:936
 msgid "invalid conditional option"
 msgstr ""
 
-#: ppc-opc.c:909
+#: ppc-opc.c:908 ppc-opc.c:938
+msgid "invalid counter access"
+msgstr ""
+
+#: ppc-opc.c:940
 msgid "attempt to set y bit when using + or - modifier"
 msgstr ""
 
-#: ppc-opc.c:941
+#: ppc-opc.c:972
 msgid "invalid mask field"
 msgstr ""
 
-#: ppc-opc.c:967
+#: ppc-opc.c:998
 msgid "ignoring invalid mfcr mask"
 msgstr ""
 
-#: ppc-opc.c:1017 ppc-opc.c:1052
+#: ppc-opc.c:1048 ppc-opc.c:1083
 msgid "illegal bitmask"
 msgstr ""
 
-#: ppc-opc.c:1172
+#: ppc-opc.c:1170
+msgid "address register in load range"
+msgstr ""
+
+#: ppc-opc.c:1223
 msgid "index register in load range"
 msgstr ""
 
-#: ppc-opc.c:1188
+#: ppc-opc.c:1239 ppc-opc.c:1295
 msgid "source and target register operands must be different"
 msgstr ""
 
-#: ppc-opc.c:1203
+#: ppc-opc.c:1254
 msgid "invalid register operand when updating"
 msgstr ""
 
-#: ppc-opc.c:1282
+#: ppc-opc.c:1349
 msgid "invalid sprg number"
 msgstr ""
 
-#: ppc-opc.c:1452
+#: ppc-opc.c:1519
 msgid "invalid constant"
 msgstr ""
 
@@ -1058,23 +1125,23 @@ msgstr ""
 msgid "<illegal instruction>"
 msgstr ""
 
-#: sparc-dis.c:283
+#: sparc-dis.c:285
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:294
+#: sparc-dis.c:296
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:344
+#: sparc-dis.c:346
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr ""
 
 #. Mark as non-valid instruction.
-#: sparc-dis.c:1015
+#: sparc-dis.c:1028
 msgid "unknown"
 msgstr ""