diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-10-19 11:21:44 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-10-24 09:47:36 -0700 |
| commit | 63a25ea0de6d2f6d45b26af8d9c808aa35962256 (patch) | |
| tree | cfdf414c06e214a4886a85c57e56912902a59884 /opcodes | |
| parent | 09a7c6aa7a07f874f5357cde62b5753a10a5e107 (diff) | |
| download | gdb-63a25ea0de6d2f6d45b26af8d9c808aa35962256.zip gdb-63a25ea0de6d2f6d45b26af8d9c808aa35962256.tar.gz gdb-63a25ea0de6d2f6d45b26af8d9c808aa35962256.tar.bz2 | |
RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0
These are all invalid instructions, so they should not disassemble.
opcodes/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (match_c_addi16sp) : New function.
(match_c_addi4spn): New function.
(match_c_lui): Don't allow 0-immediate encodings.
(riscv_opcodes) <addi>: Use the above functions.
<add>: Likewise.
<c.addi4spn>: Likewise.
<c.addi16sp>: Likewise.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-addi16sp-fail.d: New test.
testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
testsuite/gas/riscv/riscv.exp: Add new tests.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 30 |
2 files changed, 33 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e47ede5..89ab194 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2017-10-24 Andrew Waterman <andrew@sifive.com> + + * riscv-opc.c (match_c_addi16sp) : New function. + (match_c_addi4spn): New function. + (match_c_lui): Don't allow 0-immediate encodings. + (riscv_opcodes) <addi>: Use the above functions. + <add>: Likewise. + <c.addi4spn>: Likewise. + <c.addi16sp>: Likewise. + 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-init.h: Regenerate diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 27b4b9f..84cdea8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -114,9 +114,25 @@ match_c_add (const struct riscv_opcode *op, insn_t insn) } static int +match_c_addi16sp (const struct riscv_opcode *op, insn_t insn) +{ + return (match_opcode (op, insn) + && (((insn & MASK_RD) >> OP_SH_RD) == 2) + && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0); +} + +static int match_c_lui (const struct riscv_opcode *op, insn_t insn) { - return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2); + return (match_rd_nonzero (op, insn) + && (((insn & MASK_RD) >> OP_SH_RD) != 2) + && EXTRACT_RVC_LUI_IMM (insn) != 0); +} + +static int +match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0; } const struct riscv_opcode riscv_opcodes[] = @@ -188,15 +204,15 @@ const struct riscv_opcode riscv_opcodes[] = {"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, {"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, {"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, -{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, -{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, +{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, @@ -628,8 +644,8 @@ const struct riscv_opcode riscv_opcodes[] = {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, {"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, -{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, -{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, +{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, {"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, {"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, {"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, |