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authorJeff Law <law@redhat.com>1996-08-23 06:56:44 +0000
committerJeff Law <law@redhat.com>1996-08-23 06:56:44 +0000
commit3c72ab70359f1c5455a70c7f2989b13e80d0f1e7 (patch)
treec627b6c1e9bcd8e7eab454005b9fc7df0d759f62 /opcodes
parent1510cd39b6af2f606999a09dbacf609a8b8a7ac3 (diff)
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* v850-opc.c (v850_operansd): 3-bit immediate for bit insns
is unsigned.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog3
-rw-r--r--opcodes/v850-opc.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f723268..430bc69 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,9 @@
start-sanitize-v850
Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
+ * v850-opc.c (v850_operansd): 3-bit immediate for bit insns
+ is unsigned.
+
* v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
short store word (sst.w).
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 78c769f..cf6f6cf 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -62,7 +62,7 @@ const struct v850_operand v850_operands[] = {
#define B3 (D22+1)
/* The 3 bit immediate field in format 8 insn. */
- { 3, 11, 0, 0, V850_OPERAND_SIGNED },
+ { 3, 11, 0, 0, 0 },
#define CCCC (B3+1)
/* The 4 bit condition code in a setf instruction */