Fix typo.

1 files changed, 166 insertions, 172 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ffd2670..f02f542 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -12,14 +12,10 @@ Wed Jun  7 21:36:45 2000  Denis Chertykov  <denisc@overta.ru>
 
 	* avr-dis.c: completely rewritten.
 
-2000-06-02  Kazu Hirata  <kazu@hxi.com>=0A=
+2000-06-02  Kazu Hirata  <kazu@hxi.com>
 
 	* h8300-dis.c: Follow the GNU coding style.
 	(bfd_h8_disassemble) Fix a typo.
-	
-2000-06-02  Nick Clifton  <nickc@cygnus.com>
-
-	* h8300-dis.c (bfd_h8_disassemble): 
 
 2000-06-01  Kazu Hirata  <kazu@hxi.com>
 
@@ -84,9 +80,9 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 
 2000-05-11  Thomas de Lellis  <tdel@windriver.com>
 
-        * arm-opc.c: Disassembly of thumb ldsb/ldsh
-        instructions changed to ldrsb/ldrsh.
-	
+	* arm-opc.c: Disassembly of thumb ldsb/ldsh
+	instructions changed to ldrsb/ldrsh.
+
 2000-05-11  Ulf Carlsson  <ulfc@engr.sgi.com>
 
 	* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
@@ -110,12 +106,12 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 	* configure.in: Added tic54x target.
 	* configure: Ditto.
 	* Makefile.am: Add tic54x dependencies.
-	* Makefile.in: Ditto. 
+	* Makefile.in: Ditto.
 
 2000-05-03  J.T. Conklin  <jtc@redback.com>
 
 	* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
- 	vector unit operands.
+	vector unit operands.
 	(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
 	unit instruction formats.
 	(PPCVEC): New macro, mask for vector instructions.
@@ -147,7 +143,7 @@ Mon Apr 24 15:21:35 2000  Clinton Popetz  <cpopetz@cygnus.com>
 2000-04-24  Nick Clifton  <nickc@cygnus.com>
 
 	* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
-	field. 
+	field.
 
 2000-04-22  Timothy Wall  <twall@cygnus.com>
 
@@ -165,7 +161,7 @@ Mon Apr 24 15:21:35 2000  Clinton Popetz  <cpopetz@cygnus.com>
 	the highest priority.
 	* ia64-opc-b.c: Use more abbreviations.
 	* ia64-asmtab.c: Regenerate.
-	
+
 Fri Apr 21 16:03:39 2000  Jason Eckhardt  <jle@cygnus.com>
 
 	* hppa-dis.c (extract_16): New function.
@@ -194,7 +190,7 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 	ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
 	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
 	ia64-war.tbl, ia64-waw.tbl): New files.
-	
+
 2000-04-20  Alexandre Oliva  <aoliva@cygnus.com>
 
 	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
@@ -220,9 +216,9 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 	ansidecl.h as sysdep.h includes it.
 
 Fri Apr  7 15:56:57 2000  Andrew Cagney  <cagney@b1.cygnus.com>
- 
+
 	* configure.in (WARN_CFLAGS): Set to -W -Wall by default.  Add
- 	--enable-build-warnings option.
+	--enable-build-warnings option.
 	* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
 	* Makefile.in, configure: Re-generate.
 
@@ -308,24 +304,24 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 
 2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
 
-        * d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
-        flag to determine if operand is pc-relative.
-        * d30v-opc.c:
-        (d30v_format_table):
-        (REL6S3): Renamed from IMM6S3.
-        Added flag OPERAND_PCREL.
-        (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
-        added flag OPERAND_PCREL.
-        (IMM12S3U): Replaced with REL12S3.
-        (SHORT_D2, LONG_D): Delay target is pc-relative.
-        (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
-        Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
-        using the REL* operands.
-        (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
-        (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
-        LONG_Db, using REL* operands.
-        (SHORT_U, SHORT_A5S): Removed stray alternatives.
-        (d30v_opcode_table): Use new *r formats.
+	* d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
+	flag to determine if operand is pc-relative.
+	* d30v-opc.c:
+	(d30v_format_table):
+	(REL6S3): Renamed from IMM6S3.
+	Added flag OPERAND_PCREL.
+	(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
+	added flag OPERAND_PCREL.
+	(IMM12S3U): Replaced with REL12S3.
+	(SHORT_D2, LONG_D): Delay target is pc-relative.
+	(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
+	Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
+	using the REL* operands.
+	(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
+	(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
+	LONG_Db, using REL* operands.
+	(SHORT_U, SHORT_A5S): Removed stray alternatives.
+	(d30v_opcode_table): Use new *r formats.
 
 2000-02-28  Nick Clifton  <nickc@cygnus.com>
 
@@ -346,7 +342,7 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 
 2000-02-23  Andrew Haley  <aph@cygnus.com>
 
-        * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+	* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
 	m32r-ibld.c,m32r-opc.h: Rebuild.
 
 2000-02-23  Linas Vepstas <linas@linas.org>
@@ -428,12 +424,12 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* arm-dis.c (parse_arm_diassembler_option): Rename again.
 	Previous delat did not take.
 
-2000-02-03  Timothy Wall  <twall@redhat.com>	
-	
+2000-02-03  Timothy Wall  <twall@redhat.com>
+
 	* dis-buf.c (buffer_read_memory):  Use octets_per_byte field
 	to adjust target address bounds checking and calculate the
 	appropriate octet offset into data.
-	
+
 2000-01-27  Nick Clifton  <nickc@redhat.com>
 
 	* arm-dis.c: (parse_disassembler_option): Rename to
@@ -442,7 +438,7 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* disassemble.c (disassembler_usage): New function: Print out any
 	target specific disassembler options.
 	Call arm_disassembler_options() if the ARM architecture is being
-	supported.  
+	supported.
 
 	* arm-dis.c (NUM_ELEM): Define this macro if not already
 	defined.
@@ -455,18 +451,18 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	(print_insn_little_arm): Call print_insn.
 	(print_arm_disassembler_options): Display list of supported,
 	ARM specific disassembler options.
-	  
+
 2000-01-27  Thomas de Lellis  <tdel@windriver.com>
 
-        * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
+	* arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
 	ARM_STT_16BIT flag as Thumb code symbols.
-        
-        * arm-dis.c (printf_insn_little_arm): Ditto.
+
+	* arm-dis.c (printf_insn_little_arm): Ditto.
 
 2000-01-25  Thomas de Lellis  <tdel@windriver.com>
 
 	* arm-dis.c (printf_insn_thumb): Prevent double dumping
-        of raw thumb instructions.
+	of raw thumb instructions.
 
 2000-01-20  Nick Clifton  <nickc@cygnus.com>
 
@@ -534,7 +530,7 @@ Mon Nov 15 19:34:58 1999  Donald Lindsay  <dlindsay@cygnus.com>
 
 1999-10-28  Nick Clifton  <nickc@cygnus.com>
 
-	* mcore-dis.c: Remove spurious code introduced in previous delta. 
+	* mcore-dis.c: Remove spurious code introduced in previous delta.
 
 1999-10-27  Scott Bambrough  <scottb@netwinder.org>
 
@@ -579,7 +575,7 @@ Thu Oct  7 00:12:43 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
 1999-09-29  Nick Clifton  <nickc@cygnus.com>
 
 	* sh-opc.h: Fix bit patterns for several load and store
-	instructions.  
+	instructions.
 
 Thu Sep 23 08:27:20 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org
 
@@ -670,7 +666,7 @@ Mon Aug 30 18:56:14 1999  Richard Henderson  <rth@cygnus.com>
 
 Sat Aug 28 00:27:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 
-        * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'.  Prefix float
+	* hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'.  Prefix float
 	register args by 'f'.
 
 	* hppa-dis.c (print_insn_hppa): Add args q, %, !, and |.
@@ -683,7 +679,7 @@ Sat Aug 28 00:27:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 	saturation_names):  New.
 	(print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'.
 
-	* hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. 
+	* hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'.
 
 	* hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!'
 
@@ -744,7 +740,7 @@ Wed Jul 28 04:33:58 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 1999-07-05  Nick Clifton  <nickc@cygnus.com>
 
 	* arm-dis.c (print_insn_arm): Display hex equivalent of rotated
-	constant. 
+	constant.
 
 1999-06-23  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -762,14 +758,14 @@ Wed Jul 28 04:33:58 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 1999-06-16  Nick Clifton  <nickc@cygnus.com>
 
 	* arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange
-	SWIs. 
+	SWIs.
 
 1999-06-14  Nick Clifton  <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com>
 
 	* arm-dis.c (arm_regnames): Turn into a pointer to a register
 	name set.
 	(arm_regnames_standard): New variable: Array of ARM register
-	names according to ARM instruction set nomenclature. 
+	names according to ARM instruction set nomenclature.
 	(arm_regnames_apcs): New variable: Array of ARM register names
 	according to ARM Procedure Call Standard.
 	(arm_regnames_raw): New variable: Array of ARM register names
@@ -1053,30 +1049,28 @@ Thu Feb  4 13:48:52 1999  Ian Lance Taylor  <ian@cygnus.com>
 
 Mon Feb  1 20:54:36 1999  Catherine Moore  <clm@cygnus.com>
 
-        * disassemble.c (disassembler):  Handle bfd_mach_i386_i386_intel_syntax.
-        * i386-dis.c (x_mode):  Define.
-        (dis386):  Remove.
-        (dis386_att):  New.
-        (dis386_intel):  New.
-        (dis386_twobyte):  Remove.
-        (dis386_twobyte_att):  New.
-        (dis386_twobyte_intel):  New.
-        (print_insn_x86):  Use new arrays.
-        (float_mem):  Remove.
-        (float_mem_intel):  New.
-        (float_mem_att):  New.
-        (dofloat):  Use new float_mem arrays.
-        (print_insn_i386_att):  New.
-        (print_insn_i386_intel):  New.
-        (print_insn_i386):  Handle bfd_mach_i386_i386_intel_syntax.
-        (putop):  Handle intel syntax.
-        (OP_indirE):  Handle intel syntax.
-        (OP_E):  Handle intel syntax.
-        (OP_I):  Handle intel syntax.
-        (OP_sI):  Handle intel syntax.
-        (OP_OFF):  Handle intel syntax.
-
-
+	* disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax.
+	* i386-dis.c (x_mode):  Define.
+	(dis386):  Remove.
+	(dis386_att):  New.
+	(dis386_intel):  New.
+	(dis386_twobyte):  Remove.
+	(dis386_twobyte_att):  New.
+	(dis386_twobyte_intel):  New.
+	(print_insn_x86):  Use new arrays.
+	(float_mem):  Remove.
+	(float_mem_intel):  New.
+	(float_mem_att):  New.
+	(dofloat):  Use new float_mem arrays.
+	(print_insn_i386_att):  New.
+	(print_insn_i386_intel):  New.
+	(print_insn_i386):  Handle bfd_mach_i386_i386_intel_syntax.
+	(putop):  Handle intel syntax.
+	(OP_indirE):  Handle intel syntax.
+	(OP_E):  Handle intel syntax.
+	(OP_I):  Handle intel syntax.
+	(OP_sI):  Handle intel syntax.
+	(OP_OFF):  Handle intel syntax.
 
 1999-01-27  Doug Evans  <devans@casey.cygnus.com>
 
@@ -1088,7 +1082,7 @@ Tue Jan 19 18:01:54 1999  David Taylor  <taylor@texas.cygnus.com>
 
 	* hppa-dis.c: revert HP merge changes until HP gives us
 	an updated file.
-	
+
 1999-01-19  Nick Clifton  <nickc@cygnus.com>
 
 	* arm-dis.c (print_insn_arm): Display ARM syntax for PC relative
@@ -1168,12 +1162,12 @@ Tue Dec  8 10:50:46 1998  David Taylor  <taylor@texas.cygnus.com>
 	* dis-buf.c (generic_strcat_address): new function.
 
 	* hppa-dis.c: Changes to improve hppa disassembly.
-	  Changed formatting in : reg_names, fp_reg_names,control_reg, 
+	  Changed formatting in : reg_names, fp_reg_names,control_reg,
 	  New variables : sign_extension_names, deposit_names, conversion_names
 	    float_test_names, compare_cond_names_double, add_cond_names_double,
-	    logical_cond_names_double, unit_cond_names_double, 
+	    logical_cond_names_double, unit_cond_names_double,
 	    branch_push_pop_names, saturation_names, shift_names, mix_names,
-	  New Macros :   GET_COMPL_O, GET_PUSH_POP,MERGED_REG 
+	  New Macros :   GET_COMPL_O, GET_PUSH_POP,MERGED_REG
 	  Move some definitions to libhppa.h: GET_FIELD, GET_BIT
 	  (fput_const): renamed as fput_hex_const
 	  (print_insn_hppa):
@@ -1183,11 +1177,11 @@ Tue Dec  8 10:50:46 1998  David Taylor  <taylor@texas.cygnus.com>
 	   - Some new code ifdefed for LOCAL_ONLY, all related to figuring out
 	     architecture version number of current machine. HP folks are
 	     trying to handle situation where the target program was compiled
-	     for PA 1.x (32-bit), but is running on a PA 2.0 machine and 
+	     for PA 1.x (32-bit), but is running on a PA 2.0 machine and
 	     visa versa.
 	   - added new cases : 'g', 'B', 'm'
 	   - added cases specifically for PA 2.0
-	   - changed the following cases : '"', 'n', 'N', 'p', 'Z', 
+	   - changed the following cases : '"', 'n', 'N', 'p', 'Z',
 	   - calls to fput_const become calls to fput_hex_const
 
 1998-12-07  James E Wilson  <wilson@wilson-pc.cygnus.com>
@@ -1200,7 +1194,7 @@ Tue Dec  8 10:50:46 1998  David Taylor  <taylor@texas.cygnus.com>
 	i960-dis.c to ta.
 	* i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
 	* i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
-	
+
 Mon Dec  7 14:33:44 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
@@ -1281,7 +1275,7 @@ Wed Nov 18 11:30:04 1998  Dave Brolley  <brolley@cygnus.com>
 	* fr30-opc.c: Regenerated.
 
 Mon Nov 16 19:21:48 1998  Dave Brolley  <brolley@cygnus.com>
-	
+
 	* fr30-opc.c: Regenerated.
 	* fr30-opc.h: Regenerated.
 	* fr30-dis.c: Regenerated.
@@ -1298,7 +1292,7 @@ Thu Nov 12 19:24:18 1998  Dave Brolley  <brolley@cygnus.com>
 Tue Nov 10 15:26:27 1998  Nick Clifton  <nickc@cygnus.com>
 
 	* disassemble.c (disassembler): Add support for FR30 target.
-	
+
 Tue Nov 10 11:00:04 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild.
@@ -1331,8 +1325,8 @@ Wed Nov  4 18:46:47 1998  Dave Brolley  <brolley@cygnus.com>
 
 Mon Nov  2 15:05:33 1998  Geoffrey Noer  <noer@cygnus.com>
 
-        * configure.in: detect cygwin* instead of cygwin32*
-        * configure: regenerate
+	* configure.in: detect cygwin* instead of cygwin32*
+	* configure: regenerate
 
 Tue Oct 27 08:58:37 1998  Gavin Romig-Koch  <gavin@cygnus.com>
 
@@ -1373,12 +1367,12 @@ Mon Sep 28 14:35:43 1998  Martin M. Hunt  <hunt@cygnus.com>
 Thu Sep 24 09:20:03 1998  Nick Clifton  <nickc@cygnus.com>
 
 	* d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP
-	insns. 
+	insns.
 
 Tue Sep 22 17:55:14 1998  Nick Clifton  <nickc@cygnus.com>
 
 	* d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit
-	class. 
+	class.
 
 Tue Sep 15 15:14:45 1998  Doug Evans  <devans@canuck.cygnus.com>
 
@@ -1394,7 +1388,7 @@ Fri Sep  4 19:42:59 1998  Nick Clifton  <nickc@cygnus.com>
 	* arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf
 	object files.
 	(print_insn_little_arm): Detect Thumb symbols in elf object
-	files. 
+	files.
 
 Sat Aug 29 22:24:09 1998  Richard Henderson  <rth@cygnus.com>
 
@@ -1437,14 +1431,14 @@ Mon Aug 10 14:08:22 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 Mon Aug 10 12:51:12 1998  Catherine Moore  <clm@cygnus.com>
 
-        * arm-dis.c (print_insn_big_arm):  Fix indentation.
-        (print_insn_little_arm): Likewise.
+	* arm-dis.c (print_insn_big_arm):  Fix indentation.
+	(print_insn_little_arm): Likewise.
 
 Sun Aug  9 20:17:28 1998  Catherine Moore  <clm@cygnus.com>
 
-        * arm-dis.c (print_insn_big_arm):  Check for thumb symbol
-        attributes.
-        (print_insn_little_arm): Likewise.
+	* arm-dis.c (print_insn_big_arm):  Check for thumb symbol
+	attributes.
+	(print_insn_little_arm): Likewise.
 
 Mon Aug  3 12:43:16 1998  Doug Evans  <devans@seba.cygnus.com>
 
@@ -1505,7 +1499,7 @@ Fri Jun 26 12:04:21 1998  Ian Lance Taylor  <ian@cygnus.com>
 
 	* configure.in: For bfd_vax_arch, build vax-dis.lo.
 	* Makefile.am: Rebuild dependencies.
- 	(CFILES): Add vax-dis.c.
+	(CFILES): Add vax-dis.c.
 	(ALL_MACHINES): Add vax-dis.lo.
 	* aclocal.m4: Rebuild with current libtool.
 	* configure, Makefile.in: Rebuild.
@@ -1545,13 +1539,13 @@ Fri Jun 19 09:16:42 1998  Mark Alexander  <marka@cygnus.com>
 Thu Jun 18 10:22:24 1998  John Metzler  <jmetzler@cygnus.com>
 
 	* mips-dis.c (print_insn_little_mips): Previously, instruction
- 	printing references the symbol table to determine whether the
- 	instruction resides in a block regular instructions or mips16
- 	instructions. However, when the disassembler gets used in other
- 	environments where the symbol table is not present, we no longer
- 	rely in the symbol table, rather, use the low bit of the
- 	instructions address to guess. There should be no change for usage
- 	of the disassembler in host based programs, gdb, objdump.
+	printing references the symbol table to determine whether the
+	instruction resides in a block regular instructions or mips16
+	instructions. However, when the disassembler gets used in other
+	environments where the symbol table is not present, we no longer
+	rely in the symbol table, rather, use the low bit of the
+	instructions address to guess. There should be no change for usage
+	of the disassembler in host based programs, gdb, objdump.
 	(print_insn_big_mips): ditto.
 	(print_insn_mips): ditto
 
@@ -1600,7 +1594,7 @@ Fri Jun 12 11:04:06 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.
 	(print_insn_x86): Cast to bfd_vma when passing a value to
 	print_address_func.
 	* ns32k-dis.c (CORE_ADDR): Don't define.
- 	(print_insn_ns32k): Change type of addr to bfd_vma.  Use
+	(print_insn_ns32k): Change type of addr to bfd_vma.  Use
 	bfd_scan_vma to read back address.
 	(print_insn_arg): Change type of addr to bfd_vma.  Use sprintf_vma
 	to format it.
@@ -1722,7 +1716,7 @@ Thu May  7 17:15:59 1998  Ian Lance Taylor  <ian@cygnus.com>
 Thu May  7 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 
 	* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
- 	variety of ISA2 instructions to set bottom ten bits of trap code.
+	variety of ISA2 instructions to set bottom ten bits of trap code.
 
 Thu May  7 11:54:25 1998  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -1862,10 +1856,10 @@ Thu Apr  2 17:25:49 1998  Nick Clifton  <nickc@cygnus.com>
 
 Wed Apr  1 16:20:27 1998  Ian Dall  <Ian.Dall@dsto.defence.gov.au>
 
-        * ns32k-dis.c (bit_extract_simple): New function to extract bits
-        from an arbitrary valid buffer instead of fetching them on demand
-        using fetch_data().
-        (invalid_float): use bit_extract_simple() instead of bit_extract().
+	* ns32k-dis.c (bit_extract_simple): New function to extract bits
+	from an arbitrary valid buffer instead of fetching them on demand
+	using fetch_data().
+	(invalid_float): use bit_extract_simple() instead of bit_extract().
 
 Tue Mar 31 11:09:08 1998  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -2127,13 +2121,13 @@ Thu Jan 22 16:20:17 1998  Fred Fish  <fnf@cygnus.com>
 
 	* d10v-dis.c (PC_MASK): Correct value.
 	(print_operand): If there's a reloc, don't calculate the
- 	address because they could be in different sections.
+	address because they could be in different sections.
 
 Fri Jan 16 15:29:11 1998  Jim Blandy  <jimb@zwingli.cygnus.com>
 
 	* mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu"
- 	instruction after the 4650's "mul" instruction; nobody's using the
- 	4010 these days.  If object files someday indicate which processor
+	instruction after the 4650's "mul" instruction; nobody's using the
+	4010 these days.  If object files someday indicate which processor
 	variant they're intended for, we can do a better job at this.
 
 Mon Jan 12 14:43:54 1998  Doug Evans  <devans@seba.cygnus.com>
@@ -2179,7 +2173,7 @@ Fri Dec 12 11:57:04 1997  Fred Fish  <fnf@cygnus.com>
 
 	* tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
 	(tic80_opcodes): Reorder table entries to put the 32 bit PC relative
- 	offset forms before the 15 bit forms, to default to the long forms.
+	offset forms before the 15 bit forms, to default to the long forms.
 
 Fri Dec 12 01:32:30 1997  Richard Henderson  <rth@cygnus.com>
 
@@ -2327,7 +2321,7 @@ Tue Oct  7 23:37:21 1997  Gavin Koch  <gavin@cygnus.com>
 Fri Oct  3 17:26:54 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
- 	than assuming that char is signed.  Explicitly sign extend 16 bit
+	than assuming that char is signed.  Explicitly sign extend 16 bit
 	values, rather than assuming that short is 16 bits.
 	(OP_sI, OP_J, OP_DIR): Likewise.
 
@@ -2433,7 +2427,7 @@ Wed Aug 27 21:42:39 1997  Ken Raeburn  <raeburn@cygnus.com>
 	if an opcode has a short and a long form.  Used for deciding
 	to append a ".s" or ".l".
 	(print_insn): Append a ".s" to an instruction if it is
- 	the short form and ".l" if it is a long form. Do not append
+	the short form and ".l" if it is a long form. Do not append
 	anything if the instruction has only one possible size.
 
 	* d30v-opc.c: Change mulx2h to require an even register.
@@ -2469,8 +2463,8 @@ Mon Sep  8 14:06:59 1997  Doug Evans  <dje@canuck.cygnus.com>
 
 Tue Sep  2 18:39:08 1997  Jeffrey A Law  (law@cygnus.com)
 
-        * mn10200-dis.c (disassemble): PC relative instructions are
-        relative to the next instruction, not the current instruction.
+	* mn10200-dis.c (disassemble): PC relative instructions are
+	relative to the next instruction, not the current instruction.
 
 Tue Sep  2 15:41:55 1997  Nick Clifton  <nickc@cygnus.com>
 
@@ -2612,9 +2606,9 @@ Thu Jul 10 12:56:10 1997  Jeffrey A Law  (law@cygnus.com)
 Wed Jun 25 15:25:57 1997  Felix Lee  <flee@cirdan.cygnus.com>
 
 	* ppc-opc.c (extract_nsi): make unsigned expression signed before
- 	negating it.
+	negating it.
 	(UNUSED): remove one level of parens, so MSVC doesn't choke on
- 	nesting depth when all the macros are expanded.
+	nesting depth when all the macros are expanded.
 
 Tue Jun 17 17:02:17 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -2848,7 +2842,7 @@ Tue Mar 18 14:17:03 1997  Jeffrey A Law  (law@cygnus.com)
 Mon Mar 17 08:48:03 1997  J.T. Conklin  <jtc@beauty.cygnus.com>
 
 	* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
- 	mulul insns on the coldfire.
+	mulul insns on the coldfire.
 
 Sat Mar 15 17:13:05 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -2896,7 +2890,7 @@ Tue Mar  4 06:10:36 1997  J.T. Conklin  <jtc@cygnus.com>
 Mon Mar  3 07:45:20 1997  J.T. Conklin  <jtc@cygnus.com>
 
 	* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
- 	the mc68000.
+	the mc68000.
 
 Thu Feb 27 14:04:32 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
 
@@ -3056,7 +3050,7 @@ Thu Jan 30 14:09:03 1997  Fred Fish  <fnf@cygnus.com>
 	(tic80_symbol_to_value): New function.
 	(tic80_value_to_symbol): New function.
 	* tic80-dis.c (print_operand_control_register,
- 	print_operand_condition_code, print_operand_bitnum):
+	print_operand_condition_code, print_operand_bitnum):
 	Remove private tables and use tic80_value_to_symbol function.
 
 Thu Jan 30 11:30:45 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
@@ -3075,13 +3069,13 @@ Tue Jan 28 15:57:34 1997  Ian Lance Taylor  <ian@cygnus.com>
 	(print_mips16_insn_arg): Likewise.
 
 	* mips-dis.c (print_insn_mips16): Better handling of an extend
- 	opcode followed by an instruction which can not be extended.
+	opcode followed by an instruction which can not be extended.
 
 Fri Jan 24 12:08:21 1997  J.T. Conklin  <jtc@cygnus.com>
 
 	* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
- 	coldfire moveb instruction to not allow an address register as
- 	destination.  Although the documentation does not indicate that
+	coldfire moveb instruction to not allow an address register as
+	destination.  Although the documentation does not indicate that
 	this is invalid, experiments uncovered unexpected behavior.
 	Added a comment explaining the situation.  Thanks to Andreas
 	Schwab for pointing this out to me.
@@ -3089,7 +3083,7 @@ Fri Jan 24 12:08:21 1997  J.T. Conklin  <jtc@cygnus.com>
 Wed Jan 22 20:13:51 1997  Fred Fish  <fnf@cygnus.com>
 
 	* tic80-opc.c (tic80_opcodes): Expand comment to note that the
- 	entries are presorted so that entries with the same mnemonic are
+	entries are presorted so that entries with the same mnemonic are
 	adjacent to each other in the table.  Sort the entries for each
 	instruction so that this is true.
 
@@ -3141,9 +3135,9 @@ Wed Jan 15 18:59:51 1997  Fred Fish  <fnf@cygnus.com>
 	* tic80-opc.c (tic80_operands): Reorder some table entries to make
 	the order more logical.  Move the shift alias instructions ("rotl",
 	"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
- 	interspersed with the regular sr.x and sl.x instructions.  Add
+	interspersed with the regular sr.x and sl.x instructions.  Add
 	and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
- 	"sub", "subu", "swcr", and "trap".
+	"sub", "subu", "swcr", and "trap".
 
 Tue Jan 14 19:42:50 1997  Fred Fish  <fnf@cygnus.com>
 
@@ -3157,9 +3151,9 @@ Tue Jan 14 19:42:50 1997  Fred Fish  <fnf@cygnus.com>
 	"ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr"
 	instructions.
 	* tic80-dis.c (print_insn_tic80): Print opcode name with fixed width
- 	10 char field, padded with spaces on rhs, rather than a string
- 	followed by a tab.  Use renamed TIC80_OPERAND_PCREL flag bit rather
- 	than old TIC80_OPERAND_RELATIVE.  Add support for new
+	10 char field, padded with spaces on rhs, rather than a string
+	followed by a tab.  Use renamed TIC80_OPERAND_PCREL flag bit rather
+	than old TIC80_OPERAND_RELATIVE.  Add support for new
 	TIC80_OPERAND_BASEREL flag bit.
 
 Mon Jan 13 15:58:56 1997  Fred Fish  <fnf@cygnus.com>
@@ -3200,9 +3194,9 @@ Mon Jan  6 10:56:25 1997  Fred Fish  <fnf@cygnus.com>
 Sun Jan  5 12:18:14 1997  Fred Fish  <fnf@cygnus.com>
 
 	* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
- 	in an instruction.
+	in an instruction.
 	* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
-  	Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
+	Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
 	* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
 	(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New	bit-twiddlers.
 	(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
@@ -3270,7 +3264,7 @@ Sun Dec 29 10:58:22 1996  Fred Fish  <fnf@cygnus.com>
 	* Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
 	* disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
 	(disassembler): Add bfd_arch_tic80 support to set disassemble
- 	to print_insn_tic80.
+	to print_insn_tic80.
 	* tic80-dis.c (print_insn_tic80): Add stub.
 
 Fri Dec 27 22:30:57 1996  Fred Fish  <fnf@cygnus.com>
@@ -3346,7 +3340,7 @@ Fri Dec  6 17:34:39 1996  Ian Lance Taylor  <ian@cygnus.com>
 Fri Dec  6 14:48:09 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300-opc.c: Add some comments explaining the various
- 	operands and such.
+	operands and such.
 
 	* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
 
@@ -3397,19 +3391,19 @@ Tue Nov 26 10:53:21 1996  Ian Lance Taylor  <ian@cygnus.com>
 Mon Nov 25 16:15:17 1996  J.T. Conklin  <jtc@cygnus.com>
 
 	* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
- 	operand specifiers in *save, *restore and movem* instructions.
+	operand specifiers in *save, *restore and movem* instructions.
 
 	* m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
- 	the coldfire.
+	the coldfire.
 
 	* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
- 	register operands for immediate arithmetic, not, neg, negx, and
+	register operands for immediate arithmetic, not, neg, negx, and
 	set according to condition instructions.
 
 	* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
- 	specifier of the effective-address operand in immediate forms of
- 	arithmetic instructions.  The specifier for the immediate operand
- 	notes how and where the constant will be stored.
+	specifier of the effective-address operand in immediate forms of
+	arithmetic instructions.  The specifier for the immediate operand
+	notes how and where the constant will be stored.
 
 Mon Nov 25 11:17:01 1996  Jeffrey A Law  (law@cygnus.com)
 
@@ -3492,7 +3486,7 @@ Tue Nov  5 13:26:58 1996  Jeffrey A Law  (law@cygnus.com)
 Tue Nov  5 10:30:51 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* d10v-opc.c (d10v_opcodes): Declare the trap instruction
- 	sequential so the assembler never parallelizes it with
+	sequential so the assembler never parallelizes it with
 	other instructions.
 
 Mon Nov  4 12:50:40 1996  Jeffrey A Law  (law@cygnus.com)
@@ -3652,8 +3646,8 @@ Fri Sep 27 18:28:59 1996  Stu Grossman  (grossman@critters.cygnus.com)
 Mon Sep 23 12:32:26 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* m68k-opc.c: Move the fmovemx data register cases before the
- 	other cases, so that they get recognized before the data register
- 	does gets treated as a degenerate register list.
+	other cases, so that they get recognized before the data register
+	does gets treated as a degenerate register list.
 
 Tue Sep 17 12:06:51 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -3668,7 +3662,7 @@ Tue Sep 10 16:12:39 1996  Fred Fish  <fnf@rtl.cygnus.com>
 Mon Sep  9 14:26:26 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* mips-dis.c (print_insn_arg): Print condition code registers as
- 	$fccN.
+	$fccN.
 
 Tue Sep  3 12:09:46 1996  Doug Evans  <dje@canuck.cygnus.com>
 
@@ -3816,7 +3810,7 @@ Fri Aug 23 00:27:01 1996  Jeffrey A Law  (law@cygnus.com)
 Thu Aug 22 16:57:27 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* v850-opc.c (v850_operands): Added insert and extract fields,
- 	pointers to functions that handle unusual operand encodings.
+	pointers to functions that handle unusual operand encodings.
 
 Thu Aug 22 01:05:24 1996  Jeffrey A Law  (law@cygnus.com)
 
@@ -3838,7 +3832,7 @@ Wed Aug 21 18:46:26 1996  Jeffrey A Law  (law@cygnus.com)
 Wed Aug 21 17:31:26 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
 
 	* v850-opc.c (v850_operands): Add flags field.
- 	(v850_opcodes): add move opcodes.
+	(v850_opcodes): add move opcodes.
 
 Tue Aug 20 14:41:03 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
 
@@ -3885,7 +3879,7 @@ Thu Aug  8 12:43:52 1996  Klaus Kaempf  <kkaempf@progis.de>
 Wed Aug  7 11:55:10 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* i386-dis.c (print_insn_i386): Actually return the correct value.
- 	(ONE, OP_ONE): #ifdef out; not used.
+	(ONE, OP_ONE): #ifdef out; not used.
 
 Fri Aug  2 17:47:03 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
@@ -3900,14 +3894,14 @@ Wed Jul 31 16:21:41 1996  Ian Lance Taylor  <ian@cygnus.com>
 Wed Jul 31 14:39:27 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
- 	memory transfer instructions. Add new format string entries %h and %s.
+	memory transfer instructions. Add new format string entries %h and %s.
 	* arm-dis.c: (print_insn_arm): Provide decoding of the new
 	formats %h and %s.
 
 Fri Jul 26 11:45:04 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
- 	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
+	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
 
 Fri Jul 26 14:01:43 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -3935,13 +3929,13 @@ Tue Jul 23 11:02:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 Mon Jul 22 15:38:53 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
 
 	* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
- 	move ccr/sr insns more strict so that the disassembler only
- 	selects them when the addressing mode is data register.
+	move ccr/sr insns more strict so that the disassembler only
+	selects them when the addressing mode is data register.
 
 Mon Jul 22 11:25:24 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-        * d10v-opc.c (pre_defined_registers):  Declare.
-        * d10v-dis.c (print_operand): Now uses pre_defined_registers
-        to pick a better name for the registers.
+	* d10v-opc.c (pre_defined_registers):  Declare.
+	* d10v-dis.c (print_operand): Now uses pre_defined_registers
+	to pick a better name for the registers.
 
 Mon Jul 22 13:47:23 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -3976,7 +3970,7 @@ Wed Jul 17 14:39:05 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 Wed Jul 17 10:12:05 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
- 	to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
+	to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
 
 Mon Jul 15 16:59:55 1996  Stu Grossman  (grossman@critters.cygnus.com)
 
@@ -4129,7 +4123,7 @@ Mon Apr  8 17:02:48 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
 
 	* ppc-opc.c (PPC860): Macro for 860/821 specific instructions and
 	registers.
- 	(powerpc_opcodes): Add 860/821 specific SPRs.
+	(powerpc_opcodes): Add 860/821 specific SPRs.
 
 Mon Apr  8 14:00:44 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -4354,14 +4348,14 @@ Mon Jan 22 08:29:59 1996  Doug Evans  <dje@charmed.cygnus.com>
 Fri Jan 12 14:35:58 1996  David Mosberger-Tang  <davidm@AZStarNet.com>
 
 	* alpha-opc.h (alpha_insn_set): VAX floating point opcode was
- 	incorrectly defined as 0x16 when it should be 0x15.
+	incorrectly defined as 0x16 when it should be 0x15.
 	(FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
 	(alpha_insn_set): added cvtst and cvttq float ops.  Also added
- 	excb (exception barrier) which is defined in the Alpha
- 	Architecture Handbook version 2.
+	excb (exception barrier) which is defined in the Alpha
+	Architecture Handbook version 2.
 	* alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
- 	OPERATE_FORMAT_CODE type instructions.  The bug caused mulq to be
- 	disassembled as or, for example.
+	OPERATE_FORMAT_CODE type instructions.  The bug caused mulq to be
+	disassembled as or, for example.
 
 Wed Jan 10 12:37:22 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -4387,7 +4381,7 @@ Fri Dec 15 14:14:15 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
 	* sh-opc.h (sh_nibble_type): Added REG_B.
 	(sh_arg_type): Added A_REG_B.
 	(sh_table): Added pref and bank reg versions of ldc, ldc.l, stc
- 	and stc.l opcodes.
+	and stc.l opcodes.
 	* sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B.
 
 Fri Dec 15 16:44:31 1995  Ian Lance Taylor  <ian@cygnus.com>
@@ -4403,7 +4397,7 @@ Tue Dec  5 13:42:44 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
 	From David Mosberger-Tang  <davidm@azstarnet.com>:
 	* alpha-dis.c (print_insn_alpha): fixed decoding of cpys
- 	instruction.
+	instruction.
 
 Mon Dec  4 12:29:05 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
 
@@ -4474,7 +4468,7 @@ Mon Oct 30 20:50:40 1995  Fred Fish  <fnf@cygnus.com>
 Mon Oct 23 11:11:34 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
 
 	* mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added
- 	the VR4100 specific instructions to the mips_opcodes structure.
+	the VR4100 specific instructions to the mips_opcodes structure.
 
 Thu Oct 19 11:05:23 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
@@ -4496,7 +4490,7 @@ Fri Oct  6 16:26:45 1995  Ken Raeburn  <raeburn@cygnus.com>
 
 	* m68k-dis.c (print_insn_m68k): Recognize all two-word
 	instructions that take no args by looking at the match mask.
-  	(print_insn_arg): Always print "%" before register names.
+	(print_insn_arg): Always print "%" before register names.
 	[case 'c']: Use "nc" for the no-cache case, as recognized by gas.
 	[case '_']: Don't print "@#" before address.
 	[case 'J']: Use "%s" as format string, not register name.
@@ -4512,12 +4506,12 @@ Tue Oct  3 08:30:20 1995  steve chamberlain  <sac@slash.cygnus.com>
 	From David Mosberger-Tang  <davidm@azstarnet.com>
 
 	* alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
-  	(alpha_insn_set): added definitions for VAX floating point
- 	instructions (Unix compilers don't generate these, but handcoded
- 	assembly might still use them).
+	(alpha_insn_set): added definitions for VAX floating point
+	instructions (Unix compilers don't generate these, but handcoded
+	assembly might still use them).
 
 	* alpha-dis.c (print_insn_alpha): added support for disassembling
- 	the miscellaneous instructions in the Alpha instruction set.
+	the miscellaneous instructions in the Alpha instruction set.
 
 Tue Sep 26 18:47:20 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
@@ -4933,7 +4927,7 @@ Thu Feb 16 17:34:41 1995  Ian Lance Taylor  <ian@cygnus.com>
 Wed Feb 15 15:45:20 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* mips-opc.c: Add uld and usd macros for unaligned double load and
-        store.
+	store.
 
 Tue Feb 14 13:17:37 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
 
@@ -4943,12 +4937,12 @@ Tue Feb 14 13:17:37 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
 Thu Feb  9 12:28:13 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
 	* i960-dis.c (struct tabent, struct sparse_tabent): Change the
-        signed char fields to shorts, more portable.
+	signed char fields to shorts, more portable.
 
 Wed Feb  8 17:29:29 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
 	* i960-dis.c (struct tabent, struct sparse_tabent): Declare the
-        char fields as signed chars, since they may have negative values.
+	char fields as signed chars, since they may have negative values.
 
 Mon Feb  6 10:52:06 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
 
@@ -5846,7 +5840,7 @@ Thu Jan  7 13:15:17 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
 
 Thu Jan  7 07:36:33 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
 
-    	* z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines
+	* z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines
 	* z8kgen.c, z8k-opc.h: fix sizes of some shifts.
 
 Tue Dec 22 15:42:44 1992  Per Bothner  (bothner@rtl.cygnus.com)