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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:11:13 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:11:13 +0000 |
| commit | 30bdf75259fabb1825e7244eed21551c024b725c (patch) | |
| tree | de7ae3600745db7c2cc1eda07155b6a73405d313 /opcodes | |
| parent | 7e8e6784961bb3d4dad66fd2a0d076628531acfa (diff) | |
| download | gdb-30bdf75259fabb1825e7244eed21551c024b725c.zip gdb-30bdf75259fabb1825e7244eed21551c024b725c.tar.gz gdb-30bdf75259fabb1825e7244eed21551c024b725c.tar.bz2 | |
* gas/config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
(neon_cvt_mode): Add neon_cvt_mode_r.
(do_vrint_1): New function.
(do_vrint_x): Likewise.
(do_vrint_z): Likewise.
(do_vrint_r): Likewise.
(do_vrint_a): Likewise.
(do_vrint_n): Likewise.
(do_vrint_p): Likewise.
(do_vrint_m): Likewise.
(insns): Add VRINT instructions.
* gas/testsuite/gas/arm/armv8-a+fpv5.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+fpv5.s: Likewise.
* gas/testsuite/gas/arm/armv8-a+simdv3.d: Likewise.
* gas/testsuite/gas/arm/armv8-a+simdv3.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VRINT.
(neon_opcodes): Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 10a541d..ca6cae7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * arm-dis.c (coprocessor_opcodes): Add VRINT. + (neon_opcodes): Likewise. + 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (coprocessor_opcodes): Add support for new VCVT diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 9d77432..60463d1 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -496,6 +496,10 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"}, /* Generic coprocessor instructions. */ { 0, SENTINEL_GENERIC_START, 0, "" }, @@ -578,6 +582,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* Two registers, miscellaneous. */ + {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, |