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| author | Renlin Li <renlin.li@arm.com> | 2016-02-24 13:48:59 +0000 |
|---|---|---|
| committer | Renlin Li <renlin.li@arm.com> | 2016-02-24 14:02:51 +0000 |
| commit | 8afc7bea4018bf535902503c9a25dd4a96dfa3ca (patch) | |
| tree | 25a64180700aa5d0fa5a650702468514f950457a /opcodes | |
| parent | 30bdf5c82e5734ac9f0b18eb7af631806d419270 (diff) | |
| download | gdb-8afc7bea4018bf535902503c9a25dd4a96dfa3ca.zip gdb-8afc7bea4018bf535902503c9a25dd4a96dfa3ca.tar.gz gdb-8afc7bea4018bf535902503c9a25dd4a96dfa3ca.tar.bz2 | |
[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2
opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (print_insn_coprocessor): Check co-processor number for
cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
* testsuite/gas/arm/copro.d: Update.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 23 |
2 files changed, 28 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e9f1578..60d2d7d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-02-24 Renlin Li <renlin.li@arm.com> + + * arm-dis.c (print_insn_coprocessor): Check co-processor number for + cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. + 2016-02-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Parenthesize expression to prevent diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 481270e..4960140 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3198,6 +3198,7 @@ print_insn_coprocessor (bfd_vma pc, unsigned long mask; unsigned long value = 0; int cond; + int cp_num; struct arm_private_data *private_data = info->private_data; arm_feature_set allowed_arches = ARM_ARCH_NONE; @@ -3236,6 +3237,8 @@ print_insn_coprocessor (bfd_vma pc, mask = insn->mask; value = insn->value; + cp_num = (given >> 8) & 0xf; + if (thumb) { /* The high 4 bits are 0xe for Arm conditional instructions, and @@ -3271,6 +3274,26 @@ print_insn_coprocessor (bfd_vma pc, if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) continue; + if (insn->value == 0xfe000010 /* mcr2 */ + || insn->value == 0xfe100010 /* mrc2 */ + || insn->value == 0xfc100000 /* ldc2 */ + || insn->value == 0xfc000000) /* stc2 */ + { + if (cp_num == 10 || cp_num == 11) + is_unpredictable = TRUE; + } + else if (insn->value == 0x0e000000 /* cdp */ + || insn->value == 0xfe000000 /* cdp2 */ + || insn->value == 0x0e000010 /* mcr */ + || insn->value == 0x0e100010 /* mrc */ + || insn->value == 0x0c100000 /* ldc */ + || insn->value == 0x0c000000) /* stc */ + { + /* Floating-point instructions. */ + if (cp_num == 10 || cp_num == 11) + continue; + } + for (c = insn->assembler; *c; c++) { if (*c == '%') |