diff options
| author | Jeff Law <law@redhat.com> | 1998-07-23 15:51:24 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1998-07-23 15:51:24 +0000 |
| commit | 47254a1631b7d9b79c1e6117125c2a89b8db8467 (patch) | |
| tree | bcbbb4f06708ac7f7e50d3f6b85c91869cb615e9 /opcodes | |
| parent | 511068f6c334fbfa26ac720cd75c36e656256c0f (diff) | |
| download | gdb-47254a1631b7d9b79c1e6117125c2a89b8db8467.zip gdb-47254a1631b7d9b79c1e6117125c2a89b8db8467.tar.gz gdb-47254a1631b7d9b79c1e6117125c2a89b8db8467.tar.bz2 | |
* m10300-opc.c: Add DSP autoincrement memory loads/stores.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 2 | ||||
| -rw-r--r-- | opcodes/m10300-opc.c | 44 |
2 files changed, 46 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 55bd561..ccdf845 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,8 @@ start-sanitize-am33 Thu Jul 23 09:21:03 1998 Jeffrey A Law (law@cygnus.com) + * m10300-opc.c: Add DSP autoincrement memory loads/stores. + * m10300-opc.c: Add autoincrement memory loads/stores. end-sanitize-am33 diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c index 2c09ff8..6a26130 100644 --- a/opcodes/m10300-opc.c +++ b/opcodes/m10300-opc.c @@ -1724,6 +1724,50 @@ const struct mn10300_opcode mn10300_opcodes[] = { RM6, RN4}}, { "sub_xor", 0xf73a0000, 0xffff0000, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_llt", 0xf7e00000, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lgt", 0xf7e00001, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lge", 0xf7e00002, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lle", 0xf7e00003, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lcs", 0xf7e00004, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lhi", 0xf7e00005, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lcc", 0xf7e00006, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lls", 0xf7e00007, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_leq", 0xf7e00008, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lne", 0xf7e00009, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "mov_lra", 0xf7e0000a, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "llt_mov", 0xf7e00000, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lgt_mov", 0xf7e00001, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lge_mov", 0xf7e00002, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lle_mov", 0xf7e00003, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lcs_mov", 0xf7e00004, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lhi_mov", 0xf7e00005, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lcc_mov", 0xf7e00006, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lls_mov", 0xf7e00007, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "leq_mov", 0xf7e00008, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lne_mov", 0xf7e00009, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, +{ "lra_mov", 0xf7e0000a, 0xffff000f, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), + RM6}}, /* end-sanitize-am33 */ { 0, 0, 0, 0, 0, {0}}, |