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authorRichard Sandiford <rdsandiford@googlemail.com>2013-07-25 19:11:39 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2013-07-25 19:11:39 +0000
commit1d2db237d840ed479d6e725e1a7da2253f6f79b9 (patch)
tree768630bc464711fa84eb02bdae832816e4a7c6e8 /opcodes
parenta00464085799717f03cfee95a3de4d4f0fd58c64 (diff)
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opcodes/
2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> PR gas/15220 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. gas/testsuite/ * gas/mips/loongson-2f.d: Fix expected output for madd.ps, msub.ps, nmadd.ps and nmsub.ps.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/mips-opc.c8
2 files changed, 10 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a369c44..f8ea1e2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
+
+ PR gas/15220
+ * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
+ Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
+
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 28aa387..59a63dd 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1073,7 +1073,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 },
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 },
{"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },
-{"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
+{"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1, 0, 0 },
@@ -1197,7 +1197,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE, 0, 0 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 },
{"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },
-{"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
+{"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1, 0, 0 },
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55, 0, 0 },
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, 0, D32, 0 },
@@ -1321,7 +1321,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 },
{"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 },
{"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },
-{"nmadd.ps", "D,S,T", 0x7160001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
+{"nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33, 0, 0 },
{"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },
{"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
@@ -1330,7 +1330,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F, 0, 0 },
{"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33, 0, 0 },
{"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E, 0, 0 },
-{"nmsub.ps", "D,S,T", 0x7160001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
+{"nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F, 0, 0 },
/* nop is at the start of the table. */
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1, 0, 0 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 },