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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 11:38:53 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 12:05:48 +0000 |
| commit | 11dd08e9a0a2b7115aac32d9599f1bdb0ad12ea6 (patch) | |
| tree | 10c46667a26b08493e757b3181519d039b5ced4a /opcodes | |
| parent | 853faf5cc34cfac362f33939543ce569c8ba6341 (diff) | |
| download | gdb-11dd08e9a0a2b7115aac32d9599f1bdb0ad12ea6.zip gdb-11dd08e9a0a2b7115aac32d9599f1bdb0ad12ea6.tar.gz gdb-11dd08e9a0a2b7115aac32d9599f1bdb0ad12ea6.tar.bz2 | |
MIPS16/opcodes: Respect ISA and ASE in disassembly
Limit MIPS16 instruction disassembly according to the ISA level and ASE
set selected, as with the regular MIPS and microMIPS instruction sets.
Retain the property of `objdump -m mips:16' disassembling all MIPS16
instructions however, regardless of any ISA level recorded in the binary
examined.
To validate the disassembler use the GAS test suite for its convenience
of running tests across multiple ISAs, even though placing the tests in
the binutils test suite would be more appropriate. Adjust the single
binutils test which depends on 64-bit instruction disassembly to have
the ISA level required actually recorded in the binary examined.
opcodes/
* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
(print_insn_mips16): Check opcode entries for validity against
the ISA level and ASE set selected.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module'
rather than `.set' to set the ISA level.
gas/
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 5 |
2 files changed, 11 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bffa445..d009f23 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2016-12-20 Maciej W. Rozycki <macro@imgtec.com> + * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than + ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. + (print_insn_mips16): Check opcode entries for validity against + the ISA level and ASE set selected. + +2016-12-20 Maciej W. Rozycki <macro@imgtec.com> + * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 609e0ba..9cf737d 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -658,7 +658,7 @@ const struct mips_arch_choice mips_arch_choices[] = /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ - { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64, 0, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, }; @@ -2106,6 +2106,9 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) { enum match_kind match; + if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)) + continue; + if (op->pinfo == INSN_MACRO || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) match = MATCH_NONE; |