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| author | Nick Clifton <nickc@redhat.com> | 2015-08-11 18:00:36 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-08-11 18:00:36 +0100 |
| commit | 922c5db5e733526f12e2fbfeb72c7f1f90089d53 (patch) | |
| tree | 03e8cdf09b492755856c1f4f1c1c37af666a8246 /opcodes | |
| parent | dbac553d28887561e3f154654ec8e70195d89943 (diff) | |
| download | gdb-922c5db5e733526f12e2fbfeb72c7f1f90089d53.zip gdb-922c5db5e733526f12e2fbfeb72c7f1f90089d53.tar.gz gdb-922c5db5e733526f12e2fbfeb72c7f1f90089d53.tar.bz2 | |
Fix the disassembly of the AArch64 SIMD EXT instruction.
PR 18800
* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
instruction.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4638e15..9367d1c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2015-08-11 Nick Clifton <nickc@redhat.com> + + PR 18800 + * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT + instruction. + 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> * mips-opc.c (mips_builtin_opcodes): Add "sigrie". diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index cbb951b..86bc029 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1367,7 +1367,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, /* AdvSIMD EXT. */ - {"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ}, + {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ}, /* AdvSIMD modified immediate. */ {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, |