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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-01-16 00:05:56 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-01-16 00:05:56 +0000 |
| commit | fd07a1c8801d075ea29c8bc908d14df36f9d02b0 (patch) | |
| tree | 0fb5a3e40e386ba04a3e3315c60ce226c2c2e183 /opcodes | |
| parent | 38177b2923210edf02f1769959151dec17fd7aea (diff) | |
| download | gdb-fd07a1c8801d075ea29c8bc908d14df36f9d02b0.zip gdb-fd07a1c8801d075ea29c8bc908d14df36f9d02b0.tar.gz gdb-fd07a1c8801d075ea29c8bc908d14df36f9d02b0.tar.bz2 | |
gas/testsuite/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/prescott.s: Add tests for movddup in Intel syntax.
* gas/i386/x86-64-prescott.s: Likewise.
* gas/i386/prescott.d: Updated.
* gas/i386/x86-64-prescott.d: Likewise.
opcodes/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Use Qword on movddup.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4188e9f..20c0447 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> + * i386-opc.tbl: Use Qword on movddup. + * i386-tbl.h: Regenerated. + +2008-01-15 H.J. Lu <hongjiu.lu@intel.com> + * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. * i386-tbl.h: Regenerated. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 22c54c3..337722c 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1275,7 +1275,7 @@ monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 } // Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 } -movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movshdup, 2, 0xf30f16, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mwait, 0, 0xf01, 0xc9, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 8622fb3..4ee01a5 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -10919,7 +10919,7 @@ const template i386_optab[] = 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |