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| author | J.T. Conklin <jtc@acorntoolworks.com> | 1996-08-23 00:00:18 +0000 |
|---|---|---|
| committer | J.T. Conklin <jtc@acorntoolworks.com> | 1996-08-23 00:00:18 +0000 |
| commit | 69463cbb2baefd08e33df081dfb04d86fa63ac3e (patch) | |
| tree | cabac6619fed57bfade46f08f6bd46b280ac497b /opcodes | |
| parent | 27021dd45914b1295ffb66ddec20764d17357c73 (diff) | |
| download | gdb-69463cbb2baefd08e33df081dfb04d86fa63ac3e.zip gdb-69463cbb2baefd08e33df081dfb04d86fa63ac3e.tar.gz gdb-69463cbb2baefd08e33df081dfb04d86fa63ac3e.tar.bz2 | |
* v850-opc.c (v850_operands): Added insert and extract fields,
pointers to functions that handle unusual operand encodings.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/v850-opc.c | 28 |
2 files changed, 22 insertions, 15 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 83718dd..7430fc7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,9 @@ start-sanitize-v850 +Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850-opc.c (v850_operands): Added insert and extract fields, + pointers to functions that handle unusual operand encodings. + Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) * v850-opc.c (v850_opcodes): Enable "trap". @@ -18,8 +23,8 @@ Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com> - * v850-opc.c: Add flags field to struct v850_operands, add move - opcodes to opcode table. + * v850-opc.c (v850_operands): Add flags field. + (v850_opcodes): add move opcodes. Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com> diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index a424c09..6fe87d4 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -19,43 +19,47 @@ const struct v850_operand v850_operands[] = { #define UNUSED 0 - { 0, 0, 0 }, + { 0, 0, 0, 0, 0 }, /* The R1 field in a format 1, 6, 7, or 9 insn. */ #define R1 (UNUSED+1) - { 5, 0, OPERAND_REG }, + { 5, 0, 0, 0, V850_OPERAND_REG }, /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ #define R2 (R1+1) - { 5, 11, OPERAND_REG }, + { 5, 11, 0, 0, V850_OPERAND_REG }, /* The IMM5 field in a format 2 insn. */ #define I5 (R2+1) - { 5, 0, OPERAND_NUM }, + { 5, 0, 0, 0, 0 }, #define IMM16 field in a format 6 insn. */ #define I16 (I5+1) - { 16, 0, OPERAND_NUM }, + { 16, 0, 0, 0, 0 }, /* The DISP6 field in a format 4 insn. */ #define D6 (I16+1) - { 6, 1, OPERAND_NUM }, + { 6, 1, 0, 0, 0 }, /* The DISP8 field in a format 3 insn. */ #define D8 (D6+1) - { 9, 0, OPERAND_NUM }, + { 9, 0, 0, 0, 0 }, /* The DISP16 field in a format 6 insn. */ #define D16 (D8+1) - { 16, 0, OPERAND_NUM }, + { 16, 0, 0, 0, 0 }, /* The DISP22 field in a format 4 insn. */ #define D22 (D16+1) - { 16, 0, OPERAND_NUM }, + { 16, 0, 0, 0, 0 }, #define B3 (D22+1) /* The 3 bit immediate field in format 8 insn. */ - { 3, 11, OPERAND_NUM } + { 3, 11, 0, 0, 0 }, + +#define CCCC (B3+1) +/* The 4 bit condition code in a setf instruction */ + { 4, 0, 0, 0, V850_OPERAND_CC } } ; @@ -135,9 +139,7 @@ const struct v850_opcode v850_opcodes[] = { { "divh", OP(0x02), OP_MASK, IF1 }, { "cmp", OP(0x0f), OP_MASK, IF1 }, { "cmp", OP(0x13), OP_MASK, IF2 }, - -{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {I5,R2} }, - /* XXX - really I4 */ +{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} }, /* saturated operation instructions */ { "satadd", OP(0x06), OP_MASK, IF1 }, |