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| author | Jiawei <jiawei@iscas.ac.cn> | 2024-08-20 10:10:21 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-08-27 10:25:49 +0800 |
| commit | ca2590d7804b4ea563eec6f1127ed17a00c30315 (patch) | |
| tree | 850d78027e02d5d5e9cf5eb4fda22c6f9ade5cfd /opcodes | |
| parent | 47649afc965a611478f3dc42c43772ca8f182df4 (diff) | |
| download | gdb-ca2590d7804b4ea563eec6f1127ed17a00c30315.zip gdb-ca2590d7804b4ea563eec6f1127ed17a00c30315.tar.gz gdb-ca2590d7804b4ea563eec6f1127ed17a00c30315.tar.bz2 | |
RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'.
All disassemble instructions use the sreg format.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
gas/ChangeLog:
PR 32036
* NEWS: Updated.
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcmp-mv.d: New test.
* testsuite/gas/riscv/zcmp-mv.s: New test.
include/ChangeLog:
PR 32036
* opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.
(MASK_CM_MVA01S): New mask.
(MATCH_CM_MVSA01): New opcode.
(MASK_CM_MVSA01): New mask.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (OP_MASK_SREG1): New mask.
(OP_SH_SREG1): New operand code.
(OP_MASK_SREG2): New mask.
(OP_SH_SREG2): New operand code.
(X_A0): New reg number.
(X_A1): Ditto.
(X_S7): Ditto.
(RISCV_SREG_0_7): New macro function.
opcodes/ChangeLog:
PR 32036
* riscv-dis.c (riscv_zcmp_get_sregno): New function.
(print_insn_args): New operators.
* riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 19 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 9 |
2 files changed, 28 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index f292fc7..86b5287 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -285,6 +285,17 @@ riscv_get_spimm (insn_t l) return spimm; } +/* Get s-register regno by using sreg number. + e.g. the regno of s0 is 8, so + riscv_zcmp_get_sregno (0) equals 8. */ + +static unsigned +riscv_zcmp_get_sregno (unsigned sreg_idx) +{ + return sreg_idx > 1 ? + sreg_idx + 16 : sreg_idx + 8; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -698,6 +709,14 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'c': /* Zcb extension 16 bits length instruction fields. */ switch (*++oparg) { + case '1': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_zcmp_get_sregno (EXTRACT_OPERAND (SREG1, l))]); + break; + case '2': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_zcmp_get_sregno (EXTRACT_OPERAND (SREG2, l))]); + break; case 'b': print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_BYTE_UIMM (l)); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c4b089d..c922bcd 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -355,6 +355,13 @@ match_th_load_pair(const struct riscv_opcode *op, return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); } +static int +match_sreg1_not_eq_sreg2 (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) + && (EXTRACT_OPERAND (SREG1, insn) != EXTRACT_OPERAND (SREG2, insn)); +} + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -2186,6 +2193,8 @@ const struct riscv_opcode riscv_opcodes[] = {"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, {"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, {"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, +{"cm.mva01s", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVA01S, MASK_CM_MVA01S, match_opcode, 0 }, +{"cm.mvsa01", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVSA01, MASK_CM_MVSA01, match_sreg1_not_eq_sreg2, 0 }, /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, |