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author | Jeff Law <law@redhat.com> | 1997-01-29 16:40:15 +0000 |
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committer | Jeff Law <law@redhat.com> | 1997-01-29 16:40:15 +0000 |
commit | c9f649022e9df4c6f60c0340d0ea07e68bee0aab (patch) | |
tree | e541b64390cb53fc739886b698cd7b4b768abecc /opcodes | |
parent | 53bdb44c10b2b12cc9c6f55d374263d83b486c2a (diff) | |
download | gdb-c9f649022e9df4c6f60c0340d0ea07e68bee0aab.zip gdb-c9f649022e9df4c6f60c0340d0ea07e68bee0aab.tar.gz gdb-c9f649022e9df4c6f60c0340d0ea07e68bee0aab.tar.bz2 |
* mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
branchs relaxable.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 5 | ||||
-rw-r--r-- | opcodes/mn10200-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0f51c03..a855cc5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative + branchs relaxable. + Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> * mips-dis.c (print_insn_mips16): Set insn_info information. diff --git a/opcodes/mn10200-opc.c b/opcodes/mn10200-opc.c index 2024899..999d7cf 100644 --- a/opcodes/mn10200-opc.c +++ b/opcodes/mn10200-opc.c @@ -68,7 +68,7 @@ const struct mn10200_operand mn10200_operands[] = { /* 16 bit pc-relative immediate which may promote to a 16bit pc-relative immediate. */ #define IMM16_PCREL (IMM16+1) - {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_PCREL}, + {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, /* 16bit unsigned dispacement in a memory operation which may promote to a 32bit displacement. */ @@ -111,7 +111,7 @@ const struct mn10200_operand mn10200_operands[] = { /* 8 bit pc-relative displacement. */ #define SD8N_PCREL (SD16+1) - {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL}, + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, /* 8 bit signed immediate which may promote to 16bit signed immediate. */ #define SIMM8 (SD8N_PCREL+1) |