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| author | Dmitry Selyutin <ghostmansd@gmail.com> | 2022-07-25 16:10:18 +0300 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-08-11 18:38:29 +0930 |
| commit | baf97ef24f92a14f6872107adb2f08feed882be1 (patch) | |
| tree | 33c4ed1371f562dbbc847e51c407d608e84eb7ec /opcodes | |
| parent | 4c388a8e2c65fc997e7b84f9c5f1f5608e807455 (diff) | |
| download | gdb-baf97ef24f92a14f6872107adb2f08feed882be1.zip gdb-baf97ef24f92a14f6872107adb2f08feed882be1.tar.gz gdb-baf97ef24f92a14f6872107adb2f08feed882be1.tar.bz2 | |
ppc/svp64: support svshape instruction
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svshape
https://libre-soc.org/openpower/isa/simplev/
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ppc-opc.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index d027976..c8fd3b1 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3837,6 +3837,21 @@ const struct powerpc_operand powerpc_operands[] = #define ms vs + 1 { 0x1, 8, NULL, NULL, 0 }, + +#define SVLcr ms + 1 + { 0x1, 5, NULL, NULL, 0 }, + +#define SVxd SVLcr + 1 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVyd SVxd + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVzd SVyd + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define SVrm SVzd + 1 + { 0xf, 7, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -4719,6 +4734,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | (((uint64_t)(rc)) & 1)) #define SVL_MASK SVL (0x3f, 0x1f, 1) +/* An SVM form instruction. */ +#define SVM(op, xop) \ + (OP (op) \ + | (((uint64_t)(xop)) & 0x3f)) +#define SVM_MASK SVM (0x3f, 0x3f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6791,6 +6812,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}}, {"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}}, +{"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}}, + {"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, {"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, |