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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:13:31 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:13:31 +0100 |
| commit | 8c45011acd7a589c306e74563d00fb3fa5c14bbd (patch) | |
| tree | bacfec63705d92c7aa717e507e0069b76412b57f /opcodes | |
| parent | f4950f76fa56bd60314f05620c39fb31e96bb088 (diff) | |
| download | gdb-8c45011acd7a589c306e74563d00fb3fa5c14bbd.zip gdb-8c45011acd7a589c306e74563d00fb3fa5c14bbd.tar.gz gdb-8c45011acd7a589c306e74563d00fb3fa5c14bbd.tar.bz2 | |
Arm64: correct uzp{1,2} mnemonics
According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
3 files changed, 10 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bf031a7..ec64512 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2020-01-03 Jan Beulich <jbeulich@suse.com> + * opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from + uzip{1,2}. + * opcodes/aarch64-dis-2.c: Re-generate. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit FMMLA encoding. * opcodes/aarch64-dis-2.c: Re-generate. diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 950a5f2..23f32e9 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -9913,7 +9913,7 @@ aarch64_opcode_lookup_1 (uint32_t word) /* 33222222222211111111110000000000 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx - uzip1. */ + uzp1. */ return 2409; } else @@ -9943,7 +9943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) /* 33222222222211111111110000000000 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx - uzip2. */ + uzp2. */ return 2410; } else diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 8a74777..3128d84 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5084,8 +5084,8 @@ struct aarch64_opcode aarch64_opcode_table[] = F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), - F64MATMUL_SVE_INSN ("uzip1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), - F64MATMUL_SVE_INSN ("uzip2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), + F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), + F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), /* Matrix Multiply advanced SIMD instructions. */ |