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| author | Nick Clifton <nickc@redhat.com> | 2016-03-18 17:02:20 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2016-03-18 17:04:07 +0000 |
| commit | 8678914fcb40e4c620a33e6b38a14df928fa780a (patch) | |
| tree | a4d4f0d972c9c0ff7d7a15b8246cb97f2d35496a /opcodes | |
| parent | 9c3f22346dd632201807c0718d5281ed1eea329f (diff) | |
| download | gdb-8678914fcb40e4c620a33e6b38a14df928fa780a.zip gdb-8678914fcb40e4c620a33e6b38a14df928fa780a.tar.gz gdb-8678914fcb40e4c620a33e6b38a14df928fa780a.tar.bz2 | |
Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.
PR target/19721
opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
of MOV insn that aliases an ORR insn.
gas * testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0474fce..7a673e3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2016-03-18 Nick Clifton <nickc@redhat.com> + + PR target/19721 + * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand + of MOV insn that aliases an ORR insn. + 2016-03-16 Jiong Wang <jiong.wang@arm.com> * arm-dis.c (neon_opcodes): Support new FP16 instructions. diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 66a0cae..872e3d1 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2547,7 +2547,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, - {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF}, + {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF}, {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO}, {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF}, |