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| author | Jan Beulich <jbeulich@novell.com> | 2018-04-26 08:53:20 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-04-26 08:53:20 +0200 |
| commit | 7a69eac330adff3913a8698eac450cc7968ba8b0 (patch) | |
| tree | b18ae6062dbee55c24b75a279a83558f730dfec7 /opcodes | |
| parent | 1d3f82868db8881cd9ce79ad151fb0a7ebeb2c5a (diff) | |
| download | gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.zip gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.tar.gz gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.tar.bz2 | |
x86: also optimize zeroing-masking variants of insns
When zeroing an element of a register it doesn't matter whether the zero
results from the actual operation (xor, sub, or nand) or from the
zeroing-masking taking effect due to a clear mask register bit.
Diffstat (limited to 'opcodes')
0 files changed, 0 insertions, 0 deletions