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| author | Alan Modra <amodra@gmail.com> | 2022-10-14 12:28:33 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-10-16 13:54:50 +1030 |
| commit | 45685a2fd86073e76a772c5b677f14f8465a5040 (patch) | |
| tree | f7ddbaca363370fcdec5448d01896bcc744958e4 /opcodes | |
| parent | 206e9791cb09459bf92603428370c16bfde282ac (diff) | |
| download | gdb-45685a2fd86073e76a772c5b677f14f8465a5040.zip gdb-45685a2fd86073e76a772c5b677f14f8465a5040.tar.gz gdb-45685a2fd86073e76a772c5b677f14f8465a5040.tar.bz2 | |
PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many
I noticed recently that se_rfmci, a VLE mode instruction, was being
accepted by non-VLE cpus, and also that se_rfmci by itself in a
section did not cause SHF_PPC_VLE to be set. ie. both testcases added
by this patch fail without the changes to tc-ppc.c here.
Also, VLE, SPE2 and LSP insns were not accepted by the assembler with
-many nor were SPE2 and LSP being disassembled with -Many.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add
vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify
disassembler index segment checks. Add LSP and SPE2 opcodes
when PPC_OPCODE_ANY too.
(md_assemble): Correct logic adding PPC_APUINFO_VLE and
SHF_PPC_VLE.
* testsuite/gas/ppc/se_rfmci.s
* testsuite/gas/ppc/se_rfmci.d,
* testsuite/gas/ppc/se_rfmci_bad.d: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
opcodes/
* ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn
when -Many.
* ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ppc-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 6 |
2 files changed, 9 insertions, 1 deletions
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index cc9328c..33a9670 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -1016,6 +1016,10 @@ print_insn_powerpc (bfd_vma memaddr, opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) opcode = lookup_powerpc (insn, dialect); + if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) + opcode = lookup_spe2 (insn, dialect); + if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) + opcode = lookup_lsp (insn, dialect); } if (opcode != NULL) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index e1b6764..b470ebd 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -9675,6 +9675,10 @@ const struct powerpc_opcode vle_opcodes[] = { {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, +/* PPCRFMCI in the following does not enable the instruction for any + PPC_OPCODE_RFMCI supporting cpu as vle_opcodes are all added to the + assembler hash table or searched by the disassembler under control + of PPC_OPCODE_VLE. It's there to set apuinfo. */ {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, @@ -9746,7 +9750,7 @@ const struct powerpc_opcode vle_opcodes[] = { {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, -{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_stmvmcsrrw",OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, {"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}}, {"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}}, |