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authorJan Beulich <jbeulich@novell.com>2018-07-11 10:28:56 +0200
committerJan Beulich <jbeulich@suse.com>2018-07-11 10:28:56 +0200
commit2fb5be8dac9db623ef6e2a61b1f5b09fd246872b (patch)
tree538ca6d180320f7c01012901a31d753cb372b495 /opcodes
parentbd59a6313dbbf349dff197975f1b6a78be51b7d6 (diff)
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x86: drop {,reg16_}inoutportreg variables
The checking against reg16_inoutportreg can be had with a simple test of a bit, and the value setting from inoutportreg can be replaced by using the actual register's reg_type field. Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG is left in place, for its use in type_names[].
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/i386-gen.c4
-rw-r--r--opcodes/i386-init.h10
3 files changed, 7 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ec8587c..4ff2523 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,12 @@
2018-07-11 Jan Beulich <jbeulich@suse.com>
+ * i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
+ OPERAND_TYPE_INOUTPORTREG.
+ * i386-init.h: Re-generate.
+
+2018-07-11 Jan Beulich <jbeulich@suse.com>
+
* i386-opc.tbl (wrssd, wrussd): Add Dword.
(wrssq, wrussq): Add Qword.
* i386-tbl.h: Re-generate.
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index e976027..9b5314c 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -444,10 +444,6 @@ static initializer operand_type_init[] =
"Reg32|Acc|Dword" },
{ "OPERAND_TYPE_ACC64",
"Reg64|Acc|Qword" },
- { "OPERAND_TYPE_INOUTPORTREG",
- "InOutPortReg" },
- { "OPERAND_TYPE_REG16_INOUTPORTREG",
- "Reg16|InOutPortReg" },
{ "OPERAND_TYPE_DISP16_32",
"Disp16|Disp32" },
{ "OPERAND_TYPE_ANYDISP",
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index 75ee12d..15ef742 100644
--- a/opcodes/i386-init.h
+++ b/opcodes/i386-init.h
@@ -1452,16 +1452,6 @@
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0 } }
-#define OPERAND_TYPE_INOUTPORTREG \
- { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0 } }
-
-#define OPERAND_TYPE_REG16_INOUTPORTREG \
- { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0 } }
-
#define OPERAND_TYPE_DISP16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \