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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-07-21 00:26:29 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 25236d63fdb138e24cb34aa6c513ae8de2dac7b8 (patch) | |
| tree | a22052af6988dd1f70eb08d863e9892f093df565 /opcodes | |
| parent | 27cfd142d0a7e378d19aa9a1278e2137f849b71b (diff) | |
| download | gdb-25236d63fdb138e24cb34aa6c513ae8de2dac7b8.zip gdb-25236d63fdb138e24cb34aa6c513ae8de2dac7b8.tar.gz gdb-25236d63fdb138e24cb34aa6c513ae8de2dac7b8.tar.bz2 | |
RISC-V: Add support for literal instruction arguments
This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.
A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 2594e81..f2d3992 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -570,6 +570,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info switch (*++oparg) { + case 'l': /* Literal. */ + oparg++; + while (*oparg && *oparg != ',') + { + print (info->stream, dis_style_text, "%c", *oparg); + oparg++; + } + oparg--; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto print_imm; |