This commit was manufactured by cvs2svn to create branchcagney_framebase-20030326-branchpoint

'cagney_framebase-20030326-branch'.

Sprout from cagney_lazyid-20030317-branch 2003-03-17 14:23:51 UTC nobody 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2003-03-26 20:19:12 UTC Daniel Jacobowitz <drow@false.org> '	* breakpoint.c (handle_gnu_4_16_catch_command, get_catch_sals)':
    bfd/ChangeLog
    bfd/archures.c
    bfd/bfd-in2.h
    bfd/coff-arm.c
    bfd/coffcode.h
    bfd/coffgen.c
    bfd/cpu-arm.c
    bfd/elf32-arm.h
    bfd/elf32-m68k.c
    bfd/elf32-xstormy16.c
    bfd/elf64-mips.c
    bfd/elf64-sparc.c
    bfd/elfn32-mips.c
    bfd/elfxx-ia64.c
    bfd/elfxx-mips.c
    bfd/elfxx-mips.h
    bfd/libbfd.h
    bfd/peXXigen.c
    bfd/reloc.c
    bfd/version.h
    gdb/ChangeLog
    gdb/MAINTAINERS
    gdb/Makefile.in
    gdb/ada-lang.c
    gdb/alpha-osf1-tdep.c
    gdb/alpha-tdep.c
    gdb/arm-linux-tdep.c
    gdb/arm-tdep.c
    gdb/arm-tdep.h
    gdb/armnbsd-tdep.c
    gdb/avr-tdep.c
    gdb/blockframe.c
    gdb/breakpoint.c
    gdb/c-lang.c
    gdb/config/i386/cygwin.mt
    gdb/config/m68k/tm-os68k.h
    gdb/config/m68k/tm-sun3.h
    gdb/config/m68k/tm-vx68.h
    gdb/config/mips/tm-irix3.h
    gdb/config/mips/tm-irix6.h
    gdb/config/mips/tm-mips.h
    gdb/config/mips/tm-tx39.h
    gdb/config/mips/tm-tx39l.h
    gdb/config/pa/tm-hppa.h
    gdb/config/sparc/tm-sp64.h
    gdb/config/sparc/tm-sparc.h
    gdb/cris-tdep.c
    gdb/d10v-tdep.c
    gdb/defs.h
    gdb/disasm.c
    gdb/doc/ChangeLog
    gdb/doc/Makefile.in
    gdb/doc/gdb.texinfo
    gdb/doc/gdbint.texinfo
    gdb/doc/observer.texi
    gdb/dummy-frame.h
    gdb/dwarf2cfi.c
    gdb/expression.h
    gdb/f-lang.c
    gdb/frame.c
    gdb/frame.h
    gdb/frv-tdep.c
    gdb/gdbarch.c
    gdb/gdbarch.h
    gdb/gdbarch.sh
    gdb/gdbserver/ChangeLog
    gdb/gdbserver/config.in
    gdb/gdbserver/configure
    gdb/gdbserver/configure.in
    gdb/gdbserver/linux-low.c
    gdb/gdbtypes.h
    gdb/h8300-tdep.c
    gdb/hppa-tdep.c
    gdb/i386-cygwin-tdep.c
    gdb/i386-interix-tdep.c
    gdb/i386-tdep.c
    gdb/ia64-tdep.c
    gdb/inferior.h
    gdb/infrun.c
    gdb/jv-lang.c
    gdb/language.c
    gdb/language.h
    gdb/m2-lang.c
    gdb/m68hc11-tdep.c
    gdb/m68k-tdep.c
    gdb/main.c
    gdb/mcore-tdep.c
    gdb/mdebugread.c
    gdb/mips-tdep.c
    gdb/mn10300-tdep.c
    gdb/ns32k-tdep.c
    gdb/objc-lang.c
    gdb/objc-lang.h
    gdb/objfiles.h
    gdb/observer.c
    gdb/osabi.c
    gdb/p-lang.c
    gdb/ppc-linux-tdep.c
    gdb/ppc-sysv-tdep.c
    gdb/ppc-tdep.h
    gdb/printcmd.c
    gdb/rs6000-tdep.c
    gdb/s390-tdep.c
    gdb/scm-lang.c
    gdb/sh-tdep.c
    gdb/signals/signals.c
    gdb/somsolib.c
    gdb/sparc-tdep.c
    gdb/testsuite/ChangeLog
    gdb/testsuite/gdb.arch/e500-abi.c
    gdb/testsuite/gdb.arch/e500-abi.exp
    gdb/testsuite/gdb.arch/e500-regs.c
    gdb/testsuite/gdb.arch/e500-regs.exp
    gdb/testsuite/gdb.asm/asm-source.exp
    gdb/testsuite/gdb.asm/m68hc11.inc
    gdb/testsuite/gdb.base/args.exp
    gdb/testsuite/gdb.base/default.exp
    gdb/testsuite/gdb.base/ending-run.exp
    gdb/testsuite/gdb.base/help.exp
    gdb/testsuite/gdb.base/watchpoint.c
    gdb/testsuite/gdb.base/watchpoint.exp
    gdb/v850-tdep.c
    gdb/valops.c
    gdb/vax-tdep.c
    gdb/version.in
    gdb/x86-64-tdep.c
    gdb/xstormy16-tdep.c
    include/ChangeLog
    include/ansidecl.h
    include/coff/ChangeLog
    include/coff/arm.h
    include/elf/ChangeLog
    include/elf/arm.h
    include/gdb/ChangeLog
    include/gdb/sim-arm.h
    include/hashtab.h
    include/opcode/ChangeLog
    include/opcode/s390.h
    libiberty/ChangeLog
    libiberty/Makefile.in
    libiberty/hashtab.c
    opcodes/ChangeLog
    opcodes/arm-dis.c
    opcodes/arm-opc.h
    opcodes/i386-dis.c
    opcodes/s390-dis.c
    opcodes/s390-mkopc.c
    opcodes/s390-opc.c
    opcodes/s390-opc.txt
    sim/arm/ChangeLog
    sim/arm/Makefile.in
    sim/arm/armcopro.c
    sim/arm/armdefs.h
    sim/arm/armemu.h
    sim/arm/arminit.c
    sim/arm/configure
    sim/arm/configure.in
    sim/arm/maverick.c
    sim/arm/wrapper.c
    sim/h8300/ChangeLog
    sim/h8300/compile.c
    sim/h8300/inst.h

8 files changed, 960 insertions, 687 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 94d8721..b133896 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,33 @@
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm-dis.c (regnames): Add iWMMXt register names.
+	(set_iwmmxt_regnames): New function.
+	(print_insn_arm): Handle iWMMXt formatters.
+	* arm-opc.h: Document iWMMXt formatters.
+	(arm_opcod): Add iWMMXt instructions.
+
+2003-03-22  Doug Evans  <dje@sebabeach.org>
+
+	* i386-dis.c (dis386): Recognize icebp (0xf1).
+
+2003-03-21  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
+	S390_OPCODE_ZARCH.
+	(print_insn_s390): Use new modes field of s390_opcodes.
+	* s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove.
+	(s390_opcode_mode_val, s390_opcode_cpu_val): New enums.
+	(struct op_struct): Remove archbits. Add mode_bits and min_cpu.
+	(insertOpcode): Replace archbits by min_cpu and mode_bits.
+	(dumpTable): Write mode_bits and min_cpu instead of archbits.
+	(main): Adapt to new format in s390-opcode.txt.
+	* s390-opc.c (s390_opformats): Replace archbits by min_cpu and
+	mode_bits.
+	* s390-opc.txt: Replace archbits by min_cpu and mode_bits.
+
 2003-03-17  Nick Clifton  <nickc@redhat.com>
 
 	* ppc-opc.c: Fix formatting.  Update copyright date.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 62a2a39..8fb9702 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,24 +1,24 @@
 /* Instruction printing code for the ARM
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
-This file is part of libopcodes.
+   This file is part of libopcodes.
 
-This program is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 of the License, or (at your option)
-any later version.
+   This program is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 2 of the License, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-more details.
+   This program is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -70,7 +70,21 @@ static arm_regname regnames[] =
   { "atpcs", "Select register names used in the ATPCS",
     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
   { "special-atpcs", "Select special register names used in the ATPCS",
-    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
+    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
+  { "iwmmxt_regnames", "Select register names used on the Intel(r) Wireless MMX(tm) technology coprocessor",
+    { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}},
+  { "iwmmxt_Cregnames", "Select control register names used on the Intel(r) Wireless MMX(tm) technology coprocessor",
+    {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}}
+};
+
+static char * iwmmxt_wwnames[] =
+{"b", "h", "w", "d"};
+
+static char * iwmmxt_wwssnames[] =
+{"b", "bus", "b", "bss",
+ "h", "hus", "h", "hss",
+ "w", "wus", "w", "wss",
+ "d", "dus", "d", "dss"
 };
 
 /* Default to GCC register name set.  */
@@ -98,11 +112,15 @@ static void parse_disassembler_options
   PARAMS ((char *));
 static int  print_insn
   PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean));
-int get_arm_regname_num_options (void);
-int set_arm_regname_option (int option);
-int get_arm_regnames (int option, const char **setname,
-		      const char **setdescription,
-		      const char ***register_names);
+static int set_iwmmxt_regnames
+  PARAMS ((void));
+
+int get_arm_regname_num_options
+  PARAMS ((void));
+int set_arm_regname_option
+  PARAMS ((int));
+int get_arm_regnames
+  PARAMS ((int, const char **, const char **, const char ***));
 
 /* Functions.  */
 int
@@ -167,6 +185,24 @@ arm_decode_shift (given, func, stream)
     }
 }
 
+static int
+set_iwmmxt_regnames ()
+{
+  const char * setname;
+  const char * setdesc;
+  const char ** regnames;
+  int iwmmxt_regnames = 0;
+  int num_regnames = get_arm_regname_num_options ();
+
+  get_arm_regnames (iwmmxt_regnames, &setname,
+		    &setdesc, &regnames);
+  while ((strcmp ("iwmmxt_regnames", setname))
+	 && (iwmmxt_regnames < num_regnames))
+    get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, &regnames);
+
+  return iwmmxt_regnames;
+}
+			  
 /* Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (always 4 on ARM). */
 
@@ -179,9 +215,15 @@ print_insn_arm (pc, info, given)
   const struct arm_opcode *insn;
   void *stream = info->stream;
   fprintf_ftype func   = info->fprintf_func;
+  static int iwmmxt_regnames = 0;
 
   for (insn = arm_opcodes; insn->assembler; insn++)
     {
+      if (insn->value == FIRST_IWMMXT_INSN
+	  && info->mach != bfd_mach_arm_XScale
+	  && info->mach != bfd_mach_arm_iWMMXt)
+	insn = insn + IWMMXT_INSN_COUNT;
+
       if ((given & insn->mask) == insn->value)
 	{
 	  char * c;
@@ -629,6 +671,63 @@ print_insn_arm (pc, info, given)
 				    func (stream, "f%d", reg);
 				}
 				break;
+
+			      case 'w':
+				{
+				  long reg;
+
+				  if (bitstart != bitend)
+				    {
+				      reg = given >> bitstart;
+				      reg &= (2 << (bitend - bitstart)) - 1;
+				      if (bitend - bitstart == 1)
+					func (stream, "%s", iwmmxt_wwnames[reg]);
+				      else
+					func (stream, "%s", iwmmxt_wwssnames[reg]);
+				    }
+				  else
+				    {
+				      reg = (((given >> 8)  & 0x1) |
+					     ((given >> 22) & 0x1));
+				      func (stream, "%s", iwmmxt_wwnames[reg]);
+				    }
+				}
+				break;
+
+			      case 'g':
+				{
+				  long reg;
+				  int current_regnames;
+
+				  if (! iwmmxt_regnames)
+				    iwmmxt_regnames = set_iwmmxt_regnames ();
+				  current_regnames = set_arm_regname_option
+				    (iwmmxt_regnames);
+
+				  reg = given >> bitstart;
+				  reg &= (2 << (bitend - bitstart)) - 1;
+				  func (stream, "%s", arm_regnames[reg]);
+				  set_arm_regname_option (current_regnames);
+				}
+				break;
+
+			      case 'G':
+				{
+				  long reg;
+				  int current_regnames;
+
+				  if (! iwmmxt_regnames)
+				    iwmmxt_regnames = set_iwmmxt_regnames ();
+				  current_regnames = set_arm_regname_option
+				    (iwmmxt_regnames + 1);
+
+				  reg = given >> bitstart;
+				  reg &= (2 << (bitend - bitstart)) - 1;
+				  func (stream, "%s", arm_regnames[reg]);
+				  set_arm_regname_option (current_regnames);
+				}
+				break;
+
 			      default:
 				abort ();
 			      }
@@ -734,6 +833,54 @@ print_insn_arm (pc, info, given)
 			  }
 			break;
 
+		      case 'L':
+			switch (given & 0x00400100)
+			  {
+			  case 0x00000000: func (stream, "b"); break;
+			  case 0x00400000: func (stream, "h"); break;
+			  case 0x00000100: func (stream, "w"); break;
+			  case 0x00400100: func (stream, "d"); break;
+			  default:
+			    break;
+			  }
+			break;
+
+		      case 'Z':
+			{
+			  int value;
+			  /* given (20, 23) | given (0, 3) */
+			  value = ((given >> 16) & 0xf0) | (given & 0xf);
+			  func (stream, "%d", value);
+			}
+			break;
+
+		      case 'l':
+			/* This is like the 'A' operator, except that if
+			   the width field "M" is zero, then the offset is
+			   *not* multiplied by four.  */
+			{
+			  int offset = given & 0xff;
+			  int multiplier = (given & 0x00000100) ? 4 : 1;
+
+			  func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+
+			  if (offset)
+			    {
+			      if ((given & 0x01000000) != 0)
+				func (stream, ", %s#%d]%s",
+				      ((given & 0x00800000) == 0 ? "-" : ""),
+				      offset * multiplier,
+				      ((given & 0x00200000) != 0 ? "!" : ""));
+			      else
+				func (stream, "], %s#%d",
+				      ((given & 0x00800000) == 0 ? "-" : ""),
+				      offset * multiplier);
+			    }
+			  else
+			    func (stream, "]");
+			}
+			break;
+
 		      default:
 			abort ();
 		      }
diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 213d4f0..233a830 100644
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -1,6 +1,6 @@
 /* Opcode table for the ARM.
 
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003
    Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
@@ -60,6 +60,13 @@ struct thumb_opcode
    %m			print register mask for ldm/stm instruction
    %C			print the PSR sub type.
    %F			print the COUNT field of a LFM/SFM instruction.
+IWMMXT specific format options:
+   %<bitfield>g         print as an iWMMXt 64-bit register
+   %<bitfield>G         print as an iWMMXt general purpose or control register
+   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
+   %Z			print the Immediate of a WSHUFH instruction.
+   %L			print as an iWMMXt N/M width field.
+   %l			like 'A' except use byte offsets for 'B' & 'H' versions
 Thumb specific format options:
    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
@@ -101,6 +108,59 @@ static const struct arm_opcode arm_opcodes[] =
     {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
     {0xf450f000, 0xfc70f000, "pld\t%a"},
     
+    /* Intel(r) Wireless MMX(tm) technology instructions.  */
+#define FIRST_IWMMXT_INSN 0x0e130130
+#define IWMMXT_INSN_COUNT 47
+    {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
+    {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
+    {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+    {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+    {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+    {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
+    {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
+    {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
+    {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
+    {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
+    {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
+    {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
+    {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+    {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
+    {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
+    {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+    {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+    {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
+    {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
+    {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
+    {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+    {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
+
     /* V5 Instructions.  */
     {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
     {0xfa000000, 0xfe000000, "blx\t%B"},
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f185b28..79faee6 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -736,7 +736,7 @@ static const struct dis386 dis386[] = {
   { "outS",		indirDX, eAX, XX },
   /* f0 */
   { "(bad)",		XX, XX, XX },	/* lock prefix */
-  { "(bad)",		XX, XX, XX },
+  { "icebp",		XX, XX, XX },
   { "(bad)",		XX, XX, XX },	/* repne */
   { "(bad)",		XX, XX, XX },	/* repz */
   { "hlt",		XX, XX, XX },
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 8745a89..33121c7 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -57,7 +57,7 @@ init_disasm (info)
       current_arch_mask = 1 << S390_OPCODE_ESA;
       break;
     case bfd_mach_s390_64:
-      current_arch_mask = 1 << S390_OPCODE_ESAME;
+      current_arch_mask = 1 << S390_OPCODE_ZARCH;
       break;
     default:
       abort ();
@@ -161,7 +161,7 @@ print_insn_s390 (memaddr, info)
 	  const unsigned char *opindex;
 
 	  /* Check architecture.  */
-	  if (!(opcode->architecture & current_arch_mask))
+	  if (!(opcode->modes & current_arch_mask))
 	    continue;
 	  /* Check signature of the opcode.  */
 	  if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index d79ff81..caa9993 100644
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -23,21 +23,28 @@
 #include <stdlib.h>
 #include <string.h>
 
-/* ARCHBITS_ESA and ARCH_ESAME correspond to the bit numbers defined
-   by s390_opcode_arch_val in include/opcode/s390.h:
-     ARCHBITS_ESAONLY = (1<<S390_OPCODE_ESA)
-     ARCHBITS_ESA     = (1<<S390_OPCODE_ESA) + (1<<S390_OPCODE_ESAME)
-     ARCHBITS_ESA     = (1<<S390_OPCODE_ESAME).  */
-#define ARCHBITS_ESAONLY 1
-#define ARCHBITS_ESA     3
-#define ARCHBITS_ESAME   2
+/* Taken from opcodes/s390.h */
+enum s390_opcode_mode_val
+  {
+    S390_OPCODE_ESA = 0,
+    S390_OPCODE_ZARCH
+  };
+
+enum s390_opcode_cpu_val
+  {
+    S390_OPCODE_G5 = 0,
+    S390_OPCODE_G6,
+    S390_OPCODE_Z900
+  };
 
 struct op_struct
   {
     char  opcode[16];
     char  mnemonic[16];
     char  format[16];
-    int   archbits;
+    int   mode_bits;
+    int   min_cpu;
+    
     unsigned long long sort_value;
     int   no_nibbles;
   };
@@ -57,7 +64,8 @@ createTable (void)
 /* `insertOpcode': insert an op_struct into sorted opcode array.  */
 
 static void
-insertOpcode (char *opcode, char *mnemonic, char *format, int archbits)
+insertOpcode (char *opcode, char *mnemonic, char *format,
+	      int min_cpu, int mode_bits)
 {
   char *str;
   unsigned long long sort_value;
@@ -87,6 +95,7 @@ insertOpcode (char *opcode, char *mnemonic, char *format, int archbits)
       str ++;
     }
   sort_value <<= 4*(16 - ix);
+  sort_value += (min_cpu << 8) + mode_bits;
   no_nibbles = ix;
   for (ix = 0; ix < no_ops; ix++)
     if (sort_value > op_array[ix].sort_value)
@@ -98,7 +107,8 @@ insertOpcode (char *opcode, char *mnemonic, char *format, int archbits)
   strcpy(op_array[ix].format, format);
   op_array[ix].sort_value = sort_value;
   op_array[ix].no_nibbles = no_nibbles;
-  op_array[ix].archbits = archbits;
+  op_array[ix].min_cpu = min_cpu;
+  op_array[ix].mode_bits = mode_bits;
   no_ops++;
 }
 
@@ -136,7 +146,8 @@ dumpTable (void)
 	      op_array[ix].no_nibbles*4, op_array[ix].opcode);
       printf ("MASK_%s, INSTR_%s, ",
 	      op_array[ix].format, op_array[ix].format);
-      printf ("%i}", op_array[ix].archbits);
+      printf ("%i, ", op_array[ix].mode_bits);
+      printf ("%i}", op_array[ix].min_cpu);
       if (ix < no_ops-1)
 	printf (",\n");
       else
@@ -162,24 +173,50 @@ main (void)
       char  mnemonic[16];
       char  format[16];
       char  description[64];
-      char  archtag[16];
-      int   archbits;
+      char  cpu_string[16];
+      char  modes_string[16];
+      int   min_cpu;
+      int   mode_bits;
+      char  *str;
 
       if (currentLine[0] == '#')
         continue;
       memset (opcode, 0, 8);
-      if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s",
-		  opcode, mnemonic, format, description, archtag) == 5)
+      if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s %15s",
+		  opcode, mnemonic, format, description,
+		  cpu_string, modes_string) == 6)
 	{
-	  if (strcmp (archtag, "esaonly") == 0)
-	    archbits = ARCHBITS_ESAONLY;
-	  else if (strcmp (archtag, "esa") == 0)
-	    archbits = ARCHBITS_ESA;
-	  else if (strcmp (archtag, "esame") == 0)
-	    archbits = ARCHBITS_ESAME;
-	  else
-	    archbits = 0;
-	  insertOpcode (opcode, mnemonic, format, archbits);
+	  if (strcmp (cpu_string, "g5") == 0)
+	    min_cpu = S390_OPCODE_G5;
+	  else if (strcmp (cpu_string, "g6") == 0)
+	    min_cpu = S390_OPCODE_G6;
+	  else if (strcmp (cpu_string, "z900") == 0)
+	    min_cpu = S390_OPCODE_Z900;
+	  else {
+	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
+	    exit (1);
+	  }
+
+	  str = modes_string;
+	  mode_bits = 0;
+	  do {
+	    if (strncmp (str, "esa", 3) == 0
+		&& (str[3] == 0 || str[3] == ',')) {
+	      mode_bits |= 1 << S390_OPCODE_ESA;
+	      str += 3;
+	    } else if (strncmp (str, "zarch", 5) == 0
+		       && (str[5] == 0 || str[5] == ',')) {
+	      mode_bits |= 1 << S390_OPCODE_ZARCH;
+	      str += 5;
+	    } else {
+	      fprintf (stderr, "Couldn't parse modes string %s\n",
+		       modes_string);
+	      exit (1);
+	    }
+	    if (*str == ',')
+	      str++;
+	  } while (*str != 0);
+	  insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);
 	}
       else
         fprintf (stderr, "Couldn't scan line %s\n", currentLine);
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 7cd8231..a283783 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -293,23 +293,23 @@ const struct s390_operand s390_operands[] =
 
 const struct s390_opcode s390_opformats[] =
   {
-  { "e",	OP8(0x00LL),	MASK_E,		INSTR_E,	3 },
-  { "ri",	OP8(0x00LL),	MASK_RI_RI,	INSTR_RI_RI,	3 },
-  { "rie",	OP8(0x00LL),	MASK_RIE_RRP,	INSTR_RIE_RRP,	3 },
-  { "ril",	OP8(0x00LL),	MASK_RIL_RP,	INSTR_RIL_RP,	3 },
-  { "rr",	OP8(0x00LL),	MASK_RR_RR,	INSTR_RR_RR,	3 },
-  { "rre",	OP8(0x00LL),	MASK_RRE_RR,	INSTR_RRE_RR,	3 },
-  { "rrf",	OP8(0x00LL),	MASK_RRF_RURR,	INSTR_RRF_RURR,	3 },
-  { "rs",	OP8(0x00LL),	MASK_RS_RRRD,	INSTR_RS_RRRD,	3 },
-  { "rse",	OP8(0x00LL),	MASK_RSE_RRRD,	INSTR_RSE_RRRD,	3 },
-  { "rsi",	OP8(0x00LL),	MASK_RSI_RRP,	INSTR_RSI_RRP,	3 },
-  { "rx",	OP8(0x00LL),	MASK_RX_RRRD,	INSTR_RX_RRRD,	3 },
-  { "rxe",	OP8(0x00LL),	MASK_RXE_RRRD,	INSTR_RXE_RRRD,	3 },
-  { "rxf",	OP8(0x00LL),	MASK_RXF_RRRDR,	INSTR_RXF_RRRDR,3 },
-  { "s",	OP8(0x00LL),	MASK_S_RD,	INSTR_S_RD,	3 },
-  { "si",	OP8(0x00LL),	MASK_SI_URD,	INSTR_SI_URD,	3 },
-  { "ss",	OP8(0x00LL),	MASK_SS_RRRDRD,	INSTR_SS_RRRDRD,3 },
-  { "sse",	OP8(0x00LL),	MASK_SSE_RDRD,	INSTR_SSE_RDRD,	3 },
+  { "e",	OP8(0x00LL),	MASK_E,		INSTR_E,	3, 0 },
+  { "ri",	OP8(0x00LL),	MASK_RI_RI,	INSTR_RI_RI,	3, 0 },
+  { "rie",	OP8(0x00LL),	MASK_RIE_RRP,	INSTR_RIE_RRP,	3, 0 },
+  { "ril",	OP8(0x00LL),	MASK_RIL_RP,	INSTR_RIL_RP,	3, 0 },
+  { "rr",	OP8(0x00LL),	MASK_RR_RR,	INSTR_RR_RR,	3, 0 },
+  { "rre",	OP8(0x00LL),	MASK_RRE_RR,	INSTR_RRE_RR,	3, 0 },
+  { "rrf",	OP8(0x00LL),	MASK_RRF_RURR,	INSTR_RRF_RURR,	3, 0 },
+  { "rs",	OP8(0x00LL),	MASK_RS_RRRD,	INSTR_RS_RRRD,	3, 0 },
+  { "rse",	OP8(0x00LL),	MASK_RSE_RRRD,	INSTR_RSE_RRRD,	3, 0 },
+  { "rsi",	OP8(0x00LL),	MASK_RSI_RRP,	INSTR_RSI_RRP,	3, 0 },
+  { "rx",	OP8(0x00LL),	MASK_RX_RRRD,	INSTR_RX_RRRD,	3, 0 },
+  { "rxe",	OP8(0x00LL),	MASK_RXE_RRRD,	INSTR_RXE_RRRD,	3, 0 },
+  { "rxf",	OP8(0x00LL),	MASK_RXF_RRRDR,	INSTR_RXF_RRRDR,3, 0 },
+  { "s",	OP8(0x00LL),	MASK_S_RD,	INSTR_S_RD,	3, 0 },
+  { "si",	OP8(0x00LL),	MASK_SI_URD,	INSTR_SI_URD,	3, 0 },
+  { "ss",	OP8(0x00LL),	MASK_SS_RRRDRD,	INSTR_SS_RRRDRD,3, 0 },
+  { "sse",	OP8(0x00LL),	MASK_SSE_RDRD,	INSTR_SSE_RDRD,	3, 0 },
 };
 
 const int s390_num_opformats =
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index ddcf089..f0b7f83 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1,626 +1,625 @@
 #  S/390 opcodes list. Use s390-mkopc to convert it into the opcode table.
 #  Copyright 2000, 2001 Free Software Foundation, Inc.
 #  Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
-5a a RX_RRRD "add" esa
-6a ad RX_FRRD "add normalized (long)" esa
-2a adr RR_FF "add normalized (long)" esa
-7a ae RX_FRRD "add normalized (short)" esa
-3a aer RR_FF "add normalized (short)" esa
-4a ah RX_RRRD "add halfword" esa
-5e al RX_RRRD "add logical" esa
-1e alr RR_RR "add logical" esa
-fa ap SS_LLRDRD "add decimal" esa
-1a ar RR_RR "add" esa
-7e au RX_FRRD "add unnormalized (short)" esa
-3e aur RR_FF "add unnormalized (short)" esa
-6e aw RX_FRRD "add unnormalized (long)" esa
-2e awr RR_FF "add unnormalized (long)" esa
-36 axr RR_FF "add normalized" esa
-b240 bakr RRE_RR "branch and stack" esa
-45 bal RX_RRRD "branch and link" esa
-05 balr RR_RR "branch and link" esa
-4d bas RX_RRRD "branch and save" esa
-0d basr RR_RR "branch and save" esa
-0c bassm RR_RR "branch and save and set mode" esa
-47 bc RX_URRD "branch on condition" esa
-07 bcr RR_UR "branch on condition" esa
-46 bct RX_RRRD "branch on count" esa
-06 bctr RR_RR "branch on count" esa
-b258 bsg RRE_RR "branch in subspace group" esa
-0b bsm RR_RR "branch and set mode" esa
-86 bxh RS_RRRD "branch on index high" esa
-87 bxle RS_RRRD "branch on index low or equal" esa
-59 c RX_RRRD "compare" esa
-69 cd RX_FRRD "compare (long)" esa
-29 cdr RR_FF "compare (long)" esa
-bb cds RS_RRRD "compare double and swap" esa
-79 ce RX_FRRD "compare (short)" esa
-39 cer RR_FF "compare (short)" esa
-b21a cfc S_RD "compare and form codeword" esa
-49 ch RX_RRRD "compare halfword" esa
-55 cl RX_RRRD "compare logical" esa
-d5 clc SS_L0RDRD "compare logical" esa
-0f clcl RR_RR "compare logical long" esa
-95 cli SI_URD "compare logical" esa
-bd clm RS_RURD "compare logical characters under mask" esa
-15 clr RR_RR "compare logical" esa
-b25d clst RRE_RR "compare logical string" esa
-b263 cmpsc RRE_RR "compression call" esa
-f9 cp SS_LLRDRD "compare decimal" esa
-b24d cpya RRE_AA "copy access" esa
-19 cr RR_RR "compare" esa
-ba cs RS_RRRD "compare and swap" esa
-b230 csch S_00 "clear subchannel" esa
-b257 cuse RRE_RR "compare until substring equal" esa
-b250 csp RRE_RR "compare and swap and purge" esa
-4f cvb RX_RRRD "convert to binary" esa
-4e cvd RX_RRRD "convert to decimal" esa
-5d d RX_RRRD "divide" esa
-6d dd RX_FRRD "divide (long)" esa
-2d ddr RR_FF "divide (long)" esa
-7d de RX_FRRD "divide (short)" esa
-3d der RR_FF "divide (short)" esa
-83 diag RS_RRRD "diagnose" esa
-fd dp SS_LLRDRD "divide decimal" esa
-1d dr RR_RR "divide" esa
-b22d dxr RRE_F0 "divide (ext.)" esa
-b24f ear RRE_RA "extract access" esa
-de ed SS_L0RDRD "edit" esa
-df edmk SS_L0RDRD "edit and mark" esa
-b226 epar RRE_R0 "extract primary ASN" esa
-b249 ereg RRE_RR "extract stacked registers" esa
-b227 esar RRE_R0 "extract secondary ASN" esa
-b24a esta RRE_RR "extract stacked state" esa
-44 ex RX_RRRD "execute" esa
-24 hdr RR_FF "halve (long)" esa
-34 her RR_FF "halve (short)" esa
-b231 hsch S_00 "halt subchannel" esa
-b224 iac RRE_R0 "insert address space control" esa
-43 ic RX_RRRD "insert character" esa
-bf icm RS_RURD "insert characters under mask" esa
-b20b ipk S_00 "insert PSW key" esa
-b222 ipm RRE_R0 "insert program mask" esa
-b221 ipte RRE_RR "invalidate page table entry" esa
-b229 iske RRE_RR "insert storage key extended" esa
-b223 ivsk RRE_RR "insert virtual storage key" esa
-58 l RX_RRRD "load" esa
-41 la RX_RRRD "load address" esa
-51 lae RX_RRRD "load address extended" esa
-9a lam RS_AARD "load access multiple" esa
-e500 lasp SSE_RDRD "load address space parameters" esa
-23 lcdr RR_FF "load complement (long)" esa
-33 lcer RR_FF "load complement (short)" esa
-13 lcr RR_RR "load complement" esa
-b7 lctl RS_CCRD "load control" esa
-68 ld RX_FRRD "load (long)" esa
-28 ldr RR_FF "load (long)" esa
-78 le RX_FRRD "load (short)" esa
-38 ler RR_FF "load (short)" esa
-48 lh RX_RRRD "load halfword" esa
-98 lm RS_RRRD "load multiple" esa
-21 lndr RR_FF "load negative (long)" esa
-31 lner RR_FF "load negative (short)" esa
-11 lnr RR_RR "load negative" esa
-20 lpdr RR_FF "load positive (long)" esa
-30 lper RR_FF "load positive (short)" esa
-10 lpr RR_RR "load positive" esa
-82 lpsw S_RD "load PSW" esa
-18 lr RR_RR "load" esa
-b1 lra RX_RRRD "load real address" esa
-25 lrdr RR_FF "load rounded (ext. to long)" esa
-35 lrer RR_FF "load rounded (long to short)" esa
-22 ltdr RR_FF "load and test (long)" esa
-32 lter RR_FF "load and test (short)" esa
-12 ltr RR_RR "load and test" esa
-b24b lura RRE_RR "load using real address" esa
-5c m RX_RRRD "multiply" esa
-af mc SI_URD "monitor call" esa
-6c md RX_FRRD "multiply (long)" esa
-2c mdr RR_FF "multiply (long)" esa
-7c me RX_FRRD "multiply (short to long)" esa
-3c mer RR_FF "multiply (short to long)" esa
-4c mh RX_RRRD "multiply halfword" esa
-fc mp SS_LLRDRD "multiply decimal" esa
-1c mr RR_RR "multiply" esa
-b232 msch S_RD "modify subchannel" esa
-b247 msta RRE_R0 "modify stacked state" esa
-d2 mvc SS_L0RDRD "move" esa
-e50f mvcdk SSE_RDRD "move with destination key" esa
-e8 mvcin SS_L0RDRD "move inverse" esa
-d9 mvck SS_RRRDRD "move with key" esa
-0e mvcl RR_RR "move long" esa
-da mvcp SS_RRRDRD "move to primary" esa
-db mvcs SS_RRRDRD "move to secondary" esa
-e50e mvcsk SSE_RDRD "move with source key" esa
-92 mvi SI_URD "move" esa
-d1 mvn SS_L0RDRD "move numerics" esa
-f1 mvo SS_LLRDRD "move with offset" esa
-b254 mvpg RRE_RR "move page" esa
-b255 mvst RRE_RR "move string" esa
-d3 mvz SS_L0RDRD "move zones" esa
-67 mxd RX_FRRD "multiply (long to ext.)" esa
-27 mxdr RR_FF "multiply (long to ext.)" esa
-26 mxr RR_FF "multiply (ext.)" esa
-54 n RX_RRRD "AND" esa
-d4 nc SS_L0RDRD "AND" esa
-94 ni SI_URD "AND" esa
-14 nr RR_RR "AND" esa
-56 o RX_RRRD "OR" esa
-d6 oc SS_L0RDRD "OR" esa
-96 oi SI_URD "OR" esa
-16 or RR_RR "OR" esa
-f2 pack SS_LLRDRD "pack" esa
-b248 palb RRE_00 "purge ALB" esa
-b218 pc S_RD "program call" esa
-0101 pr E "program return" esa
-b228 pt RRE_RR "program transfer" esa
-b20d ptlb S_00 "purge TLB" esa
-b23b rchp S_00 "reset channel path" esa
-b22a rrbe RRE_RR "reset reference bit extended" esa
-b238 rsch S_00 "resume subchannel" esa
-5b s RX_RRRD "subtract" esa
-b219 sac S_RD "set address space control" esa
-b279 sacf S_RD "set address space control fast" esa
-b237 sal S_00 "set address limit" esa
-b24e sar RRE_AR "set access" esa
-b23c schm S_00 "set channel monitor" esa
-b204 sck S_RD "set clock" esa
-b206 sckc S_RD "set clock comparator" esa
-6b sd RX_FRRD "subtract normalized (long)" esa
-2b sdr RR_FF "subtract normalized (long)" esa
-7b se RX_FRRD "subtract normalized (short)" esa
-3b ser RR_FF "subtract normalized (short)" esa
-4b sh RX_RRRD "subtract halfword" esa
-b214 sie S_RD "start interpretive execution" esa
-ae sigp RS_RRRD "signal processor" esa
-5f sl RX_RRRD "subtract logical" esa
-8b sla RS_R0RD "shift left single" esa
-8f slda RS_R0RD "shift left double (long)" esa
-8d sldl RS_R0RD "shift left double logical (long)" esa
-89 sll RS_R0RD "shift left single logical" esa
-1f slr RR_RR "subtract logical" esa
-fb sp SS_LLRDRD "subtract decimal" esa
-b20a spka S_RD "set PSW key from address" esa
-04 spm RR_R0 "set program mask" esa
-b208 spt S_RD "set CPU timer" esa
-b210 spx S_RD "set prefix" esa
-b244 sqdr RRE_F0 "square root (long)" esa
-b245 sqer RRE_F0 "square root (short)" esa
-1b sr RR_RR "subtract" esa
-8a sra RS_R0RD "shift right single" esa
-8e srda RS_R0RD "shift right double (long)" esa
-8c srdl RS_R0RD "shift right double logical (long)" esa
-88 srl RS_R0RD "shift right single logical" esa
-f0 srp SS_LIRDRD "shift and round decimal" esa
-b25e srst RRE_RR "search string" esa
-b225 ssar RRE_R0 "set secondary ASN" esa
-b233 ssch S_RD "start subchannel" esa
-b22b sske RRE_RR "set storage key extended" esa
-80 ssm S_RD "set system mask" esa
-50 st RX_RRRD "store" esa
-9b stam RS_AARD "store access multiple" esa
-b212 stap S_RD "store CPU address" esa
-42 stc RX_RRRD "store character" esa
-b205 stck S_RD "store clock" esa
-b207 stckc S_RD "store clock comparator" esa
-be stcm RS_RURD "store characters under mask" esa
-b23a stcps S_RD "store channel path status" esa
-b239 stcrw S_RD "store channel report word" esa
-b6 stctl RS_CCRD "store control" esa
-60 std RX_FRRD "store (long)" esa
-70 ste RX_FRRD "store (short)" esa
-40 sth RX_RRRD "store halfword" esa
-b202 stidp S_RD "store CPU id" esa
-90 stm RS_RRRD "store multiple" esa
-ac stnsm SI_URD "store then AND system mask" esa
-ad stosm SI_URD "store then OR system mask" esa
-b209 stpt S_RD "store CPU timer" esa
-b211 stpx S_RD "store prefix" esa
-b234 stsch S_RD "store subchannel" esa
-b246 stura RRE_RR "store using real address" esa
-7f su RX_FRRD "subtract unnormalized (short)" esa
-3f sur RR_FF "subtract unnormalized (short)" esa
-0a svc RR_U0 "supervisor call" esa
-6f sw RX_FRRD "subtract unnormalized (long)" esa
-2f swr RR_FF "subtract unnormalized (long)" esa
-37 sxr RR_FF "subtract normalized (ext.)" esa
-b24c tar RRE_AR "test access" esa
-b22c tb RRE_0R "test block" esa
-91 tm SI_URD "test under mask" esa
-b236 tpi S_RD "test pending interruption" esa
-e501 tprot SSE_RDRD "test protection" esa
-dc tr SS_L0RDRD "translate" esa
-99 trace RS_RRRD "trace" esa
-dd trt SS_L0RDRD "translate and test" esa
-93 ts S_RD "test and set" esa
-b235 tsch S_RD "test subchannel" esa
-f3 unpk SS_LLRDRD "unpack" esa
-0102 upt E "update tree" esa
-57 x RX_RRRD "exclusive OR" esa
-d7 xc SS_L0RDRD "exclusive OR" esa
-97 xi SI_URD "exclusive OR" esa
-17 xr RR_RR "exclusive OR" esa
-f8 zap SS_LLRDRD "zero and add" esa
-a70a ahi RI_RI "add halfword immediate" esa
-84 brxh RSI_RRP "branch relative on index high" esa
-85 brxle RSI_RRP "branch relative on index low or equal" esa
-a705 bras RI_RP "branch relative and save" esa
-a704 brc RI_UP "branch relative on condition" esa
-a706 brct RI_RP "branch relative on count" esa
-b241 cksm RRE_RR "checksum" esa
-a70e chi RI_RI "compare halfword immediate" esa
-a9 clcle RS_RRRD "compare logical long extended" esa
-a708 lhi RI_RI "load halfword immediate" esa
-a8 mvcle RS_RRRD "move long extended" esa
-a70c mhi RI_RI "multiply halfword immediate" esa
-b252 msr RRE_RR "multiply single" esa
-71 ms RX_RRRD "multiply single" esa
-a700 tmh RI_RU "test under mask high" esa
-a701 tml RI_RU "test under mask low" esa
-0700 nopr RR_0R "no operation" esa
-0710 bor RR_0R "branch on overflow / if ones" esa
-0720 bhr RR_0R "branch on high" esa
-0720 bpr RR_0R "branch on plus" esa
-0730 bnler RR_0R "branch on not low or equal" esa
-0740 blr RR_0R "branch on low" esa
-0740 bmr RR_0R "branch on minus / if mixed" esa
-0750 bnher RR_0R "branch on not high or equal" esa
-0760 blhr RR_0R "branch on low or high" esa
-0770 bner RR_0R "branch on not equal" esa
-0770 bnzr RR_0R "branch on not zero / if not zeros" esa
-0780 ber RR_0R "branch on equal" esa
-0780 bzr RR_0R "branch on zero / if zeros" esa
-0790 bnlhr RR_0R "branch on not low or high" esa
-07a0 bher RR_0R "branch on high or equal" esa
-07b0 bnlr RR_0R "branch on not low" esa
-07b0 bnmr RR_0R "branch on not minus / if not mixed" esa
-07c0 bler RR_0R "brach on low or equal" esa
-07d0 bnhr RR_0R "branch on not high" esa
-07d0 bnpr RR_0R "branch on not plus" esa
-07e0 bnor RR_0R "branch on not overflow / if not ones" esa
-07f0 br RR_0R "unconditional branch" esa
-4700 nop RX_0RRD "no operation" esa
-4710 bo RX_0RRD "branch on overflow / if ones" esa
-4720 bh RX_0RRD "branch on high" esa
-4720 bp RX_0RRD "branch on plus" esa
-4730 bnle RX_0RRD "branch on not low or equal" esa
-4740 bl RX_0RRD "branch on low" esa
-4740 bm RX_0RRD "branch on minus / if mixed" esa
-4750 bnhe RX_0RRD "branch on not high or equal" esa
-4760 blh RX_0RRD "branch on low or high" esa
-4770 bne RX_0RRD "branch on not equal" esa
-4770 bnz RX_0RRD "branch on not zero / if not zeros" esa
-4780 be RX_0RRD "branch on equal" esa
-4780 bz RX_0RRD "branch on zero / if zeros" esa
-4790 bnlh RX_0RRD "branch on not low or high" esa
-47a0 bhe RX_0RRD "branch on high or equal" esa
-47b0 bnl RX_0RRD "branch on not low" esa
-47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa
-47c0 ble RX_0RRD "branch on low or equal" esa
-47d0 bnh RX_0RRD "branch on not high" esa
-47d0 bnp RX_0RRD "branch on not plus" esa
-47e0 bno RX_0RRD "branch on not overflow / if not ones" esa
-47f0 b RX_0RRD "unconditional branch" esa
-a714 jo RI_0P "jump on overflow / if ones" esa
-a724 jh RI_0P "jump on A high" esa
-a724 jp RI_0P "jump on plus" esa
-a734 jnle RI_0P "jump on not low or equal" esa
-a744 jl RI_0P "jump on A low" esa
-a744 jm RI_0P "jump on minus / if mixed" esa
-a754 jnhe RI_0P "jump on not high or equal" esa
-a764 jlh RI_0P "jump on low or high" esa
-a774 jne RI_0P "jump on A not equal B" esa
-a774 jnz RI_0P "jump on not zero / if not zeros" esa
-a784 je RI_0P "jump on A equal B" esa
-a784 jz RI_0P "jump on zero / if zeros" esa
-a794 jnlh RI_0P "jump on not low or high" esa
-a7a4 jhe RI_0P "jump on high or equal" esa
-a7b4 jnl RI_0P "jump on A not low" esa
-a7b4 jnm RI_0P "jump on not minus / if not mixed" esa
-a7c4 jle RI_0P "jump on low or equal" esa
-a7d4 jnh RI_0P "jump on A not high" esa
-a7d4 jnp RI_0P "jump on not plus" esa
-a7e4 jno RI_0P "jump on not overflow / if not ones" esa
-a7f4 j RI_0P "jump" esa
-b34a axbr RRE_FF "add extended bfp" esa
-b31a adbr RRE_FF "add long bfp" esa
-ed000000001a adb RXE_FRRD "add long bfp" esa
-b30a aebr RRE_FF "add short bfp" esa
-ed000000000a aeb RXE_FRRD "add short bfp" esa
-b349 cxbr RRE_FF "compare extended bfp" esa
-b319 cdbr RRE_FF "compare long bfp" esa
-ed0000000019 cdb RXE_FRRD "compare long bfp" esa
-b309 cebr RRE_FF "compare short bfp" esa
-ed0000000009 ceb RXE_FRRD "compare short bfp" esa
-b348 kxbr RRE_FF "compare and signal extended bfp" esa
-b318 kdbr RRE_FF "compare and signal long bfp" esa
-ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa
-b308 kebr RRE_FF "compare and signal short bfp" esa
-ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa
-b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa
-b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa
-b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa
-b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa
-b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa
-b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa
-b34d dxbr RRE_FF "divide extended bfp" esa
-b31d ddbr RRE_FF "divide long bfp" esa
-ed000000001d ddb RXE_FRRD "divide long bfp" esa
-b30d debr RRE_FF "divide short bfp" esa
-ed000000000d deb RXE_FRRD "divide short bfp" esa
-b35b didbr RRF_FUFF "divide to integer long bfp" esa
-b353 diebr RRF_FUFF "divide to integer short bfp" esa
-b38c efpc RRE_RR "extract fpc" esa
-b342 ltxbr RRE_FF "load and test extended bfp" esa
-b312 ltdbr RRE_FF "load and test long bfp" esa
-b302 ltebr RRE_FF "load and test short bfp" esa
-b343 lcxbr RRE_FF "load complement extended bfp" esa
-b313 lcdbr RRE_FF "load complement long bfp" esa
-b303 lcebr RRE_FF "load complement short bfp" esa
-b347 fixbr RRF_U0FF "load fp integer extended bfp" esa
-b35f fidbr RRF_U0FF "load fp integer long bfp" esa
-b357 fiebr RRF_U0FF "load fp integer short bfp" esa
-b29d lfpc S_RD "load fpc" esa
-b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa
-ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa
-b306 lxebr RRE_FF "load lengthened short to extended bfp" esa
-ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa
-b304 ldebr RRE_FF "load lengthened short to long bfp" esa
-ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa
-b341 lnxbr RRE_FF "load negative extended bfp" esa
-b311 lndbr RRE_FF "load negative long bfp" esa
-b301 lnebr RRE_FF "load negative short bfp" esa
-b340 lpxbr RRE_FF "load positive extended bfp" esa
-b310 lpdbr RRE_FF "load positive long bfp" esa
-b300 lpebr RRE_FF "load positive short bfp" esa
-b345 ldxbr RRE_FF "load rounded extended to long bfp" esa
-b346 lexbr RRE_FF "load rounded extended to short bfp" esa
-b344 ledbr RRE_FF "load rounded long to short bfp" esa
-b34c mxbr RRE_FF "multiply extended bfp" esa
-b31c mdbr RRE_FF "multiply long bfp" esa
-ed000000001c mdb RXE_FRRD "multiply long bfp" esa
-b307 mxdbr RRE_FF "multiply long to extended bfp" esa
-ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa
-b317 meebr RRE_FF "multiply short bfp" esa
-ed0000000017 meeb RXE_FRRD "multiply short bfp" esa
-b30c mdebr RRE_FF "multiply short to long bfp" esa
-ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa
-b31e madbr RRF_F0FF "multiply and add long bfp" esa
-ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa
-b30e maebr RRF_F0FF "multiply and add short bfp" esa
-ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa
-b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa
-ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa
-b30f msebr RRF_F0FF "multiply and subtract short bfp" esa
-ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa
-b384 sfpc RRE_RR "set fpc" esa
-b299 srnm S_RD "set rounding mode" esa
-b316 sqxbr RRE_FF "square root extended bfp" esa
-b315 sqdbr RRE_FF "square root long bfp" esa
-ed0000000015 sqdb RXE_FRRD "square root long bfp" esa
-b314 sqebr RRE_FF "square root short bfp" esa
-ed0000000014 sqeb RXE_FRRD "square root short bfp" esa
-b29c stfpc S_RD "store fpc" esa
-b34b sxbr RRE_FF "subtract extended bfp" esa
-b31b sdbr RRE_FF "subtract long bfp" esa
-ed000000001b sdb RXE_FRRD "subtract long bfp" esa
-b30b sebr RRE_FF "subtract short bfp" esa
-ed000000000b seb RXE_FRRD "subtract short bfp" esa
-ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa
-ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa
-ed0000000010 tceb RXE_FRRD "test data class short bfp" esa
-b274 siga S_RD "signal adapter" esa
-# are the following instructions confidential ??
-b2a6 cuutf RRE_RR "convert unicode to utf-8" esa
-b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa
-ee plo SS_RRRDRD2 "perform locked operation" esa
-b25a bsa RRE_RR "branch and set authority" esa
-b277 rp S_RD "resume program" esa
-0107 sckpf E "set clock programmable field" esa
-b27d stsi S_RD "store system information" esa
-01ff trap2 E "trap" esa
-b2ff trap4 S_RD "trap4" esa
+5a a RX_RRRD "add" g5 esa,zarch
+6a ad RX_FRRD "add normalized (long)" g5 esa,zarch
+2a adr RR_FF "add normalized (long)" g5 esa,zarch
+7a ae RX_FRRD "add normalized (short)" g5 esa,zarch
+3a aer RR_FF "add normalized (short)" g5 esa,zarch
+4a ah RX_RRRD "add halfword" g5 esa,zarch
+5e al RX_RRRD "add logical" g5 esa,zarch
+1e alr RR_RR "add logical" g5 esa,zarch
+fa ap SS_LLRDRD "add decimal" g5 esa,zarch
+1a ar RR_RR "add" g5 esa,zarch
+7e au RX_FRRD "add unnormalized (short)" g5 esa,zarch
+3e aur RR_FF "add unnormalized (short)" g5 esa,zarch
+6e aw RX_FRRD "add unnormalized (long)" g5 esa,zarch
+2e awr RR_FF "add unnormalized (long)" g5 esa,zarch
+36 axr RR_FF "add normalized" g5 esa,zarch
+b240 bakr RRE_RR "branch and stack" g5 esa,zarch
+45 bal RX_RRRD "branch and link" g5 esa,zarch
+05 balr RR_RR "branch and link" g5 esa,zarch
+4d bas RX_RRRD "branch and save" g5 esa,zarch
+0d basr RR_RR "branch and save" g5 esa,zarch
+0c bassm RR_RR "branch and save and set mode" g5 esa,zarch
+47 bc RX_URRD "branch on condition" g5 esa,zarch
+07 bcr RR_UR "branch on condition" g5 esa,zarch
+46 bct RX_RRRD "branch on count" g5 esa,zarch
+06 bctr RR_RR "branch on count" g5 esa,zarch
+b258 bsg RRE_RR "branch in subspace group" g5 esa,zarch
+0b bsm RR_RR "branch and set mode" g5 esa,zarch
+86 bxh RS_RRRD "branch on index high" g5 esa,zarch
+87 bxle RS_RRRD "branch on index low or equal" g5 esa,zarch
+59 c RX_RRRD "compare" g5 esa,zarch
+69 cd RX_FRRD "compare (long)" g5 esa,zarch
+29 cdr RR_FF "compare (long)" g5 esa,zarch
+bb cds RS_RRRD "compare double and swap" g5 esa,zarch
+79 ce RX_FRRD "compare (short)" g5 esa,zarch
+39 cer RR_FF "compare (short)" g5 esa,zarch
+b21a cfc S_RD "compare and form codeword" g5 esa,zarch
+49 ch RX_RRRD "compare halfword" g5 esa,zarch
+55 cl RX_RRRD "compare logical" g5 esa,zarch
+d5 clc SS_L0RDRD "compare logical" g5 esa,zarch
+0f clcl RR_RR "compare logical long" g5 esa,zarch
+95 cli SI_URD "compare logical" g5 esa,zarch
+bd clm RS_RURD "compare logical characters under mask" g5 esa,zarch
+15 clr RR_RR "compare logical" g5 esa,zarch
+b25d clst RRE_RR "compare logical string" g5 esa,zarch
+b263 cmpsc RRE_RR "compression call" g5 esa,zarch
+f9 cp SS_LLRDRD "compare decimal" g5 esa,zarch
+b24d cpya RRE_AA "copy access" g5 esa,zarch
+19 cr RR_RR "compare" g5 esa,zarch
+ba cs RS_RRRD "compare and swap" g5 esa,zarch
+b230 csch S_00 "clear subchannel" g5 esa,zarch
+b257 cuse RRE_RR "compare until substring equal" g5 esa,zarch
+b250 csp RRE_RR "compare and swap and purge" g5 esa,zarch
+4f cvb RX_RRRD "convert to binary" g5 esa,zarch
+4e cvd RX_RRRD "convert to decimal" g5 esa,zarch
+5d d RX_RRRD "divide" g5 esa,zarch
+6d dd RX_FRRD "divide (long)" g5 esa,zarch
+2d ddr RR_FF "divide (long)" g5 esa,zarch
+7d de RX_FRRD "divide (short)" g5 esa,zarch
+3d der RR_FF "divide (short)" g5 esa,zarch
+83 diag RS_RRRD "diagnose" g5 esa,zarch
+fd dp SS_LLRDRD "divide decimal" g5 esa,zarch
+1d dr RR_RR "divide" g5 esa,zarch
+b22d dxr RRE_F0 "divide (ext.)" g5 esa,zarch
+b24f ear RRE_RA "extract access" g5 esa,zarch
+de ed SS_L0RDRD "edit" g5 esa,zarch
+df edmk SS_L0RDRD "edit and mark" g5 esa,zarch
+b226 epar RRE_R0 "extract primary ASN" g5 esa,zarch
+b249 ereg RRE_RR "extract stacked registers" g5 esa,zarch
+b227 esar RRE_R0 "extract secondary ASN" g5 esa,zarch
+b24a esta RRE_RR "extract stacked state" g5 esa,zarch
+44 ex RX_RRRD "execute" g5 esa,zarch
+24 hdr RR_FF "halve (long)" g5 esa,zarch
+34 her RR_FF "halve (short)" g5 esa,zarch
+b231 hsch S_00 "halt subchannel" g5 esa,zarch
+b224 iac RRE_R0 "insert address space control" g5 esa,zarch
+43 ic RX_RRRD "insert character" g5 esa,zarch
+bf icm RS_RURD "insert characters under mask" g5 esa,zarch
+b20b ipk S_00 "insert PSW key" g5 esa,zarch
+b222 ipm RRE_R0 "insert program mask" g5 esa,zarch
+b221 ipte RRE_RR "invalidate page table entry" g5 esa,zarch
+b229 iske RRE_RR "insert storage key extended" g5 esa,zarch
+b223 ivsk RRE_RR "insert virtual storage key" g5 esa,zarch
+58 l RX_RRRD "load" g5 esa,zarch
+41 la RX_RRRD "load address" g5 esa,zarch
+51 lae RX_RRRD "load address extended" g5 esa,zarch
+9a lam RS_AARD "load access multiple" g5 esa,zarch
+e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
+23 lcdr RR_FF "load complement (long)" g5 esa,zarch
+33 lcer RR_FF "load complement (short)" g5 esa,zarch
+13 lcr RR_RR "load complement" g5 esa,zarch
+b7 lctl RS_CCRD "load control" g5 esa,zarch
+68 ld RX_FRRD "load (long)" g5 esa,zarch
+28 ldr RR_FF "load (long)" g5 esa,zarch
+78 le RX_FRRD "load (short)" g5 esa,zarch
+38 ler RR_FF "load (short)" g5 esa,zarch
+48 lh RX_RRRD "load halfword" g5 esa,zarch
+98 lm RS_RRRD "load multiple" g5 esa,zarch
+21 lndr RR_FF "load negative (long)" g5 esa,zarch
+31 lner RR_FF "load negative (short)" g5 esa,zarch
+11 lnr RR_RR "load negative" g5 esa,zarch
+20 lpdr RR_FF "load positive (long)" g5 esa,zarch
+30 lper RR_FF "load positive (short)" g5 esa,zarch
+10 lpr RR_RR "load positive" g5 esa,zarch
+82 lpsw S_RD "load PSW" g5 esa,zarch
+18 lr RR_RR "load" g5 esa,zarch
+b1 lra RX_RRRD "load real address" g5 esa,zarch
+25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
+35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
+22 ltdr RR_FF "load and test (long)" g5 esa,zarch
+32 lter RR_FF "load and test (short)" g5 esa,zarch
+12 ltr RR_RR "load and test" g5 esa,zarch
+b24b lura RRE_RR "load using real address" g5 esa,zarch
+5c m RX_RRRD "multiply" g5 esa,zarch
+af mc SI_URD "monitor call" g5 esa,zarch
+6c md RX_FRRD "multiply (long)" g5 esa,zarch
+2c mdr RR_FF "multiply (long)" g5 esa,zarch
+7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
+3c mer RR_FF "multiply (short to long)" g5 esa,zarch
+4c mh RX_RRRD "multiply halfword" g5 esa,zarch
+fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch
+1c mr RR_RR "multiply" g5 esa,zarch
+b232 msch S_RD "modify subchannel" g5 esa,zarch
+b247 msta RRE_R0 "modify stacked state" g5 esa,zarch
+d2 mvc SS_L0RDRD "move" g5 esa,zarch
+e50f mvcdk SSE_RDRD "move with destination key" g5 esa,zarch
+e8 mvcin SS_L0RDRD "move inverse" g5 esa,zarch
+d9 mvck SS_RRRDRD "move with key" g5 esa,zarch
+0e mvcl RR_RR "move long" g5 esa,zarch
+da mvcp SS_RRRDRD "move to primary" g5 esa,zarch
+db mvcs SS_RRRDRD "move to secondary" g5 esa,zarch
+e50e mvcsk SSE_RDRD "move with source key" g5 esa,zarch
+92 mvi SI_URD "move" g5 esa,zarch
+d1 mvn SS_L0RDRD "move numerics" g5 esa,zarch
+f1 mvo SS_LLRDRD "move with offset" g5 esa,zarch
+b254 mvpg RRE_RR "move page" g5 esa,zarch
+b255 mvst RRE_RR "move string" g5 esa,zarch
+d3 mvz SS_L0RDRD "move zones" g5 esa,zarch
+67 mxd RX_FRRD "multiply (long to ext.)" g5 esa,zarch
+27 mxdr RR_FF "multiply (long to ext.)" g5 esa,zarch
+26 mxr RR_FF "multiply (ext.)" g5 esa,zarch
+54 n RX_RRRD "AND" g5 esa,zarch
+d4 nc SS_L0RDRD "AND" g5 esa,zarch
+94 ni SI_URD "AND" g5 esa,zarch
+14 nr RR_RR "AND" g5 esa,zarch
+56 o RX_RRRD "OR" g5 esa,zarch
+d6 oc SS_L0RDRD "OR" g5 esa,zarch
+96 oi SI_URD "OR" g5 esa,zarch
+16 or RR_RR "OR" g5 esa,zarch
+f2 pack SS_LLRDRD "pack" g5 esa,zarch
+b248 palb RRE_00 "purge ALB" g5 esa,zarch
+b218 pc S_RD "program call" g5 esa,zarch
+0101 pr E "program return" g5 esa,zarch
+b228 pt RRE_RR "program transfer" g5 esa,zarch
+b20d ptlb S_00 "purge TLB" g5 esa,zarch
+b23b rchp S_00 "reset channel path" g5 esa,zarch
+b22a rrbe RRE_RR "reset reference bit extended" g5 esa,zarch
+b238 rsch S_00 "resume subchannel" g5 esa,zarch
+5b s RX_RRRD "subtract" g5 esa,zarch
+b219 sac S_RD "set address space control" g5 esa,zarch
+b279 sacf S_RD "set address space control fast" g5 esa,zarch
+b237 sal S_00 "set address limit" g5 esa,zarch
+b24e sar RRE_AR "set access" g5 esa,zarch
+b23c schm S_00 "set channel monitor" g5 esa,zarch
+b204 sck S_RD "set clock" g5 esa,zarch
+b206 sckc S_RD "set clock comparator" g5 esa,zarch
+6b sd RX_FRRD "subtract normalized (long)" g5 esa,zarch
+2b sdr RR_FF "subtract normalized (long)" g5 esa,zarch
+7b se RX_FRRD "subtract normalized (short)" g5 esa,zarch
+3b ser RR_FF "subtract normalized (short)" g5 esa,zarch
+4b sh RX_RRRD "subtract halfword" g5 esa,zarch
+b214 sie S_RD "start interpretive execution" g5 esa,zarch
+ae sigp RS_RRRD "signal processor" g5 esa,zarch
+5f sl RX_RRRD "subtract logical" g5 esa,zarch
+8b sla RS_R0RD "shift left single" g5 esa,zarch
+8f slda RS_R0RD "shift left double (long)" g5 esa,zarch
+8d sldl RS_R0RD "shift left double logical (long)" g5 esa,zarch
+89 sll RS_R0RD "shift left single logical" g5 esa,zarch
+1f slr RR_RR "subtract logical" g5 esa,zarch
+fb sp SS_LLRDRD "subtract decimal" g5 esa,zarch
+b20a spka S_RD "set PSW key from address" g5 esa,zarch
+04 spm RR_R0 "set program mask" g5 esa,zarch
+b208 spt S_RD "set CPU timer" g5 esa,zarch
+b210 spx S_RD "set prefix" g5 esa,zarch
+b244 sqdr RRE_F0 "square root (long)" g5 esa,zarch
+b245 sqer RRE_F0 "square root (short)" g5 esa,zarch
+1b sr RR_RR "subtract" g5 esa,zarch
+8a sra RS_R0RD "shift right single" g5 esa,zarch
+8e srda RS_R0RD "shift right double (long)" g5 esa,zarch
+8c srdl RS_R0RD "shift right double logical (long)" g5 esa,zarch
+88 srl RS_R0RD "shift right single logical" g5 esa,zarch
+f0 srp SS_LIRDRD "shift and round decimal" g5 esa,zarch
+b25e srst RRE_RR "search string" g5 esa,zarch
+b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch
+b233 ssch S_RD "start subchannel" g5 esa,zarch
+b22b sske RRE_RR "set storage key extended" g5 esa,zarch
+80 ssm S_RD "set system mask" g5 esa,zarch
+50 st RX_RRRD "store" g5 esa,zarch
+9b stam RS_AARD "store access multiple" g5 esa,zarch
+b212 stap S_RD "store CPU address" g5 esa,zarch
+42 stc RX_RRRD "store character" g5 esa,zarch
+b205 stck S_RD "store clock" g5 esa,zarch
+b207 stckc S_RD "store clock comparator" g5 esa,zarch
+be stcm RS_RURD "store characters under mask" g5 esa,zarch
+b23a stcps S_RD "store channel path status" g5 esa,zarch
+b239 stcrw S_RD "store channel report word" g5 esa,zarch
+b6 stctl RS_CCRD "store control" g5 esa,zarch
+60 std RX_FRRD "store (long)" g5 esa,zarch
+70 ste RX_FRRD "store (short)" g5 esa,zarch
+40 sth RX_RRRD "store halfword" g5 esa,zarch
+b202 stidp S_RD "store CPU id" g5 esa,zarch
+90 stm RS_RRRD "store multiple" g5 esa,zarch
+ac stnsm SI_URD "store then AND system mask" g5 esa,zarch
+ad stosm SI_URD "store then OR system mask" g5 esa,zarch
+b209 stpt S_RD "store CPU timer" g5 esa,zarch
+b211 stpx S_RD "store prefix" g5 esa,zarch
+b234 stsch S_RD "store subchannel" g5 esa,zarch
+b246 stura RRE_RR "store using real address" g5 esa,zarch
+7f su RX_FRRD "subtract unnormalized (short)" g5 esa,zarch
+3f sur RR_FF "subtract unnormalized (short)" g5 esa,zarch
+0a svc RR_U0 "supervisor call" g5 esa,zarch
+6f sw RX_FRRD "subtract unnormalized (long)" g5 esa,zarch
+2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch
+37 sxr RR_FF "subtract normalized (ext.)" g5 esa,zarch
+b24c tar RRE_AR "test access" g5 esa,zarch
+b22c tb RRE_0R "test block" g5 esa,zarch
+91 tm SI_URD "test under mask" g5 esa,zarch
+b236 tpi S_RD "test pending interruption" g5 esa,zarch
+e501 tprot SSE_RDRD "test protection" g5 esa,zarch
+dc tr SS_L0RDRD "translate" g5 esa,zarch
+99 trace RS_RRRD "trace" g5 esa,zarch
+dd trt SS_L0RDRD "translate and test" g5 esa,zarch
+93 ts S_RD "test and set" g5 esa,zarch
+b235 tsch S_RD "test subchannel" g5 esa,zarch
+f3 unpk SS_LLRDRD "unpack" g5 esa,zarch
+0102 upt E "update tree" g5 esa,zarch
+57 x RX_RRRD "exclusive OR" g5 esa,zarch
+d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch
+97 xi SI_URD "exclusive OR" g5 esa,zarch
+17 xr RR_RR "exclusive OR" g5 esa,zarch
+f8 zap SS_LLRDRD "zero and add" g5 esa,zarch
+a70a ahi RI_RI "add halfword immediate" g5 esa,zarch
+84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch
+85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch
+a705 bras RI_RP "branch relative and save" g5 esa,zarch
+a704 brc RI_UP "branch relative on condition" g5 esa,zarch
+a706 brct RI_RP "branch relative on count" g5 esa,zarch
+b241 cksm RRE_RR "checksum" g5 esa,zarch
+a70e chi RI_RI "compare halfword immediate" g5 esa,zarch
+a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch
+a708 lhi RI_RI "load halfword immediate" g5 esa,zarch
+a8 mvcle RS_RRRD "move long extended" g5 esa,zarch
+a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch
+b252 msr RRE_RR "multiply single" g5 esa,zarch
+71 ms RX_RRRD "multiply single" g5 esa,zarch
+a700 tmh RI_RU "test under mask high" g5 esa,zarch
+a701 tml RI_RU "test under mask low" g5 esa,zarch
+0700 nopr RR_0R "no operation" g5 esa,zarch
+0710 bor RR_0R "branch on overflow / if ones" g5 esa,zarch
+0720 bhr RR_0R "branch on high" g5 esa,zarch
+0720 bpr RR_0R "branch on plus" g5 esa,zarch
+0730 bnler RR_0R "branch on not low or equal" g5 esa,zarch
+0740 blr RR_0R "branch on low" g5 esa,zarch
+0740 bmr RR_0R "branch on minus / if mixed" g5 esa,zarch
+0750 bnher RR_0R "branch on not high or equal" g5 esa,zarch
+0760 blhr RR_0R "branch on low or high" g5 esa,zarch
+0770 bner RR_0R "branch on not equal" g5 esa,zarch
+0770 bnzr RR_0R "branch on not zero / if not zeros" g5 esa,zarch
+0780 ber RR_0R "branch on equal" g5 esa,zarch
+0780 bzr RR_0R "branch on zero / if zeros" g5 esa,zarch
+0790 bnlhr RR_0R "branch on not low or high" g5 esa,zarch
+07a0 bher RR_0R "branch on high or equal" g5 esa,zarch
+07b0 bnlr RR_0R "branch on not low" g5 esa,zarch
+07b0 bnmr RR_0R "branch on not minus / if not mixed" g5 esa,zarch
+07c0 bler RR_0R "brach on low or equal" g5 esa,zarch
+07d0 bnhr RR_0R "branch on not high" g5 esa,zarch
+07d0 bnpr RR_0R "branch on not plus" g5 esa,zarch
+07e0 bnor RR_0R "branch on not overflow / if not ones" g5 esa,zarch
+07f0 br RR_0R "unconditional branch" g5 esa,zarch
+4700 nop RX_0RRD "no operation" g5 esa,zarch
+4710 bo RX_0RRD "branch on overflow / if ones" g5 esa,zarch
+4720 bh RX_0RRD "branch on high" g5 esa,zarch
+4720 bp RX_0RRD "branch on plus" g5 esa,zarch
+4730 bnle RX_0RRD "branch on not low or equal" g5 esa,zarch
+4740 bl RX_0RRD "branch on low" g5 esa,zarch
+4740 bm RX_0RRD "branch on minus / if mixed" g5 esa,zarch
+4750 bnhe RX_0RRD "branch on not high or equal" g5 esa,zarch
+4760 blh RX_0RRD "branch on low or high" g5 esa,zarch
+4770 bne RX_0RRD "branch on not equal" g5 esa,zarch
+4770 bnz RX_0RRD "branch on not zero / if not zeros" g5 esa,zarch
+4780 be RX_0RRD "branch on equal" g5 esa,zarch
+4780 bz RX_0RRD "branch on zero / if zeros" g5 esa,zarch
+4790 bnlh RX_0RRD "branch on not low or high" g5 esa,zarch
+47a0 bhe RX_0RRD "branch on high or equal" g5 esa,zarch
+47b0 bnl RX_0RRD "branch on not low" g5 esa,zarch
+47b0 bnm RX_0RRD "branch on not minus / if not mixed" g5 esa,zarch
+47c0 ble RX_0RRD "branch on low or equal" g5 esa,zarch
+47d0 bnh RX_0RRD "branch on not high" g5 esa,zarch
+47d0 bnp RX_0RRD "branch on not plus" g5 esa,zarch
+47e0 bno RX_0RRD "branch on not overflow / if not ones" g5 esa,zarch
+47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
+a714 jo RI_0P "jump on overflow / if ones" g5 esa,zarch
+a724 jh RI_0P "jump on A high" g5 esa,zarch
+a724 jp RI_0P "jump on plus" g5 esa,zarch
+a734 jnle RI_0P "jump on not low or equal" g5 esa,zarch
+a744 jl RI_0P "jump on A low" g5 esa,zarch
+a744 jm RI_0P "jump on minus / if mixed" g5 esa,zarch
+a754 jnhe RI_0P "jump on not high or equal" g5 esa,zarch
+a764 jlh RI_0P "jump on low or high" g5 esa,zarch
+a774 jne RI_0P "jump on A not equal B" g5 esa,zarch
+a774 jnz RI_0P "jump on not zero / if not zeros" g5 esa,zarch
+a784 je RI_0P "jump on A equal B" g5 esa,zarch
+a784 jz RI_0P "jump on zero / if zeros" g5 esa,zarch
+a794 jnlh RI_0P "jump on not low or high" g5 esa,zarch
+a7a4 jhe RI_0P "jump on high or equal" g5 esa,zarch
+a7b4 jnl RI_0P "jump on A not low" g5 esa,zarch
+a7b4 jnm RI_0P "jump on not minus / if not mixed" g5 esa,zarch
+a7c4 jle RI_0P "jump on low or equal" g5 esa,zarch
+a7d4 jnh RI_0P "jump on A not high" g5 esa,zarch
+a7d4 jnp RI_0P "jump on not plus" g5 esa,zarch
+a7e4 jno RI_0P "jump on not overflow / if not ones" g5 esa,zarch
+a7f4 j RI_0P "jump" g5 esa,zarch
+b34a axbr RRE_FF "add extended bfp" g5 esa,zarch
+b31a adbr RRE_FF "add long bfp" g5 esa,zarch
+ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch
+b30a aebr RRE_FF "add short bfp" g5 esa,zarch
+ed000000000a aeb RXE_FRRD "add short bfp" g5 esa,zarch
+b349 cxbr RRE_FF "compare extended bfp" g5 esa,zarch
+b319 cdbr RRE_FF "compare long bfp" g5 esa,zarch
+ed0000000019 cdb RXE_FRRD "compare long bfp" g5 esa,zarch
+b309 cebr RRE_FF "compare short bfp" g5 esa,zarch
+ed0000000009 ceb RXE_FRRD "compare short bfp" g5 esa,zarch
+b348 kxbr RRE_FF "compare and signal extended bfp" g5 esa,zarch
+b318 kdbr RRE_FF "compare and signal long bfp" g5 esa,zarch
+ed0000000018 kdb RXE_FRRD "compare and signal long bfp" g5 esa,zarch
+b308 kebr RRE_FF "compare and signal short bfp" g5 esa,zarch
+ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch
+b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" g5 esa,zarch
+b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" g5 esa,zarch
+b394 cefbr RRE_RF "convert from fixed 32 to short bfp" g5 esa,zarch
+b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" g5 esa,zarch
+b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" g5 esa,zarch
+b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" g5 esa,zarch
+b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch
+b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch
+ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch
+b30d debr RRE_FF "divide short bfp" g5 esa,zarch
+ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
+b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
+b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
+b38c efpc RRE_RR "extract fpc" g5 esa,zarch
+b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch
+b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
+b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch
+b343 lcxbr RRE_FF "load complement extended bfp" g5 esa,zarch
+b313 lcdbr RRE_FF "load complement long bfp" g5 esa,zarch
+b303 lcebr RRE_FF "load complement short bfp" g5 esa,zarch
+b347 fixbr RRF_U0FF "load fp integer extended bfp" g5 esa,zarch
+b35f fidbr RRF_U0FF "load fp integer long bfp" g5 esa,zarch
+b357 fiebr RRF_U0FF "load fp integer short bfp" g5 esa,zarch
+b29d lfpc S_RD "load fpc" g5 esa,zarch
+b305 lxdbr RRE_FF "load lengthened long to extended bfp" g5 esa,zarch
+ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" g5 esa,zarch
+b306 lxebr RRE_FF "load lengthened short to extended bfp" g5 esa,zarch
+ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" g5 esa,zarch
+b304 ldebr RRE_FF "load lengthened short to long bfp" g5 esa,zarch
+ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" g5 esa,zarch
+b341 lnxbr RRE_FF "load negative extended bfp" g5 esa,zarch
+b311 lndbr RRE_FF "load negative long bfp" g5 esa,zarch
+b301 lnebr RRE_FF "load negative short bfp" g5 esa,zarch
+b340 lpxbr RRE_FF "load positive extended bfp" g5 esa,zarch
+b310 lpdbr RRE_FF "load positive long bfp" g5 esa,zarch
+b300 lpebr RRE_FF "load positive short bfp" g5 esa,zarch
+b345 ldxbr RRE_FF "load rounded extended to long bfp" g5 esa,zarch
+b346 lexbr RRE_FF "load rounded extended to short bfp" g5 esa,zarch
+b344 ledbr RRE_FF "load rounded long to short bfp" g5 esa,zarch
+b34c mxbr RRE_FF "multiply extended bfp" g5 esa,zarch
+b31c mdbr RRE_FF "multiply long bfp" g5 esa,zarch
+ed000000001c mdb RXE_FRRD "multiply long bfp" g5 esa,zarch
+b307 mxdbr RRE_FF "multiply long to extended bfp" g5 esa,zarch
+ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" g5 esa,zarch
+b317 meebr RRE_FF "multiply short bfp" g5 esa,zarch
+ed0000000017 meeb RXE_FRRD "multiply short bfp" g5 esa,zarch
+b30c mdebr RRE_FF "multiply short to long bfp" g5 esa,zarch
+ed000000000c mdeb RXE_FRRD "multiply short to long bfp" g5 esa,zarch
+b31e madbr RRF_F0FF "multiply and add long bfp" g5 esa,zarch
+ed000000001e madb RXF_FRRDF "multiply and add long bfp" g5 esa,zarch
+b30e maebr RRF_F0FF "multiply and add short bfp" g5 esa,zarch
+ed000000000e maeb RXF_FRRDF "multiply and add short bfp" g5 esa,zarch
+b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch
+ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch
+b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
+ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
+b384 sfpc RRE_RR "set fpc" g5 esa,zarch
+b299 srnm S_RD "set rounding mode" g5 esa,zarch
+b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch
+b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch
+ed0000000015 sqdb RXE_FRRD "square root long bfp" g5 esa,zarch
+b314 sqebr RRE_FF "square root short bfp" g5 esa,zarch
+ed0000000014 sqeb RXE_FRRD "square root short bfp" g5 esa,zarch
+b29c stfpc S_RD "store fpc" g5 esa,zarch
+b34b sxbr RRE_FF "subtract extended bfp" g5 esa,zarch
+b31b sdbr RRE_FF "subtract long bfp" g5 esa,zarch
+ed000000001b sdb RXE_FRRD "subtract long bfp" g5 esa,zarch
+b30b sebr RRE_FF "subtract short bfp" g5 esa,zarch
+ed000000000b seb RXE_FRRD "subtract short bfp" g5 esa,zarch
+ed0000000012 tcxb RXE_FRRD "test data class extended bfp" g5 esa,zarch
+ed0000000011 tcdb RXE_FRRD "test data class long bfp" g5 esa,zarch
+ed0000000010 tceb RXE_FRRD "test data class short bfp" g5 esa,zarch
+b274 siga S_RD "signal adapter" g5 esa,zarch
+b2a6 cuutf RRE_RR "convert unicode to utf-8" g5 esa,zarch
+b2a7 cutfu RRE_RR "convert utf-8 to unicode" g5 esa,zarch
+ee plo SS_RRRDRD2 "perform locked operation" g5 esa,zarch
+b25a bsa RRE_RR "branch and set authority" g5 esa,zarch
+b277 rp S_RD "resume program" g5 esa,zarch
+0107 sckpf E "set clock programmable field" g5 esa,zarch
+b27d stsi S_RD "store system information" g5 esa,zarch
+01ff trap2 E "trap" g5 esa,zarch
+b2ff trap4 S_RD "trap4" g5 esa,zarch
+a700 tmlh RI_RU "test under mask low high" g5 esa,zarch
+a701 tmll RI_RU "test under mask low low" g5 esa,zarch
+b278 stcke S_RD "store clock extended" g5 esa,zarch
+b2a5 tre RRE_RR "translate extended" g5 esa,zarch
+eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch
+e9 pka SS_L0RDRD "pack ascii" g5 esa,zarch
+e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch
+b993 troo RRE_RR "translate one to one" g5 esa,zarch
+b992 trot RRE_RR "translate one to two" g5 esa,zarch
+b991 trto RRE_RR "translate two to one" g5 esa,zarch
+b990 trtt RRE_RR "translate two to two" g5 esa,zarch
+ea unpka SS_L0RDRD "unpack ascii" g5 esa,zarch
+e2 unpku SS_L0RDRD "unpack unicode" g5 esa,zarch
+b358 thder RRE_RR "convert short bfp to long hfp" g5 esa,zarch
+b359 thdr RRE_RR "convert long bfp to long hfp" g5 esa,zarch
+b350 tbedr RRF_U0FF "convert long hfp to short bfp" g5 esa,zarch
+b351 tbdr RRF_U0FF "convert long hfp to long bfp" g5 esa,zarch
+b374 lzer RRE_R0 "load short zero" g5 esa,zarch
+b375 lzdr RRE_R0 "load long zero" g5 esa,zarch
+b376 lzxr RRE_R0 "load extended zero" g5 esa,zarch
 # Here are the new esame instructions:
-b946 bctgr RRE_RR "branch on count 64" esame
-b900 lpgr RRE_RR "load positive 64" esame
-b910 lpgfr RRE_RR "load positive 64<32" esame
-b901 lngr RRE_RR "load negative 64" esame
-b911 lngfr RRE_RR "load negative 64<32" esame
-b902 ltgr RRE_RR "load and test 64" esame
-b912 ltgfr RRE_RR "load and test 64<32" esame
-b903 lcgr RRE_RR "load complement 64" esame
-b913 lcgfr RRE_RR "load complement 64<32" esame
-b980 ngr RRE_RR "and 64" esame
-b921 clgr RRE_RR "compare logical 64" esame
-b931 clgfr RRE_RR "compare logical 64<32" esame
-b981 ogr RRE_RR "or 64" esame
-b982 xgr RRE_RR "exclusive or 64" esame
-b904 lgr RRE_RR "load 64" esame
-b914 lgfr RRE_RR "load 64<32" esame
-b920 cgr RRE_RR "compare 64" esame
-b930 cgfr RRE_RR "compare 64<32" esame
-b908 agr RRE_RR "add 64" esame
-b918 agfr RRE_RR "add 64<32" esame
-b909 sgr RRE_RR "subtract 64" esame
-b919 sgfr RRE_RR "subtract 64<32" esame
-b90a algr RRE_RR "add logical 64" esame
-b91a algfr RRE_RR "add logical 64<32" esame
-b90b slgr RRE_RR "subtract logical 64" esame
-b91b slgfr RRE_RR "subtract logical 64<32" esame
-e30000000046 bctg RXE_RRRD "branch on count 64" esame
-e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame
-e3000000000e cvbg RXE_RRRD "convert to binary 64" esame
-e30000000024 stg RXE_RRRD "store 64" esame
-e30000000080 ng RXE_RRRD "and 64" esame
-e30000000021 clg RXE_RRRD "compare logical 64" esame
-e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame
-e30000000081 og RXE_RRRD "or 64" esame
-e30000000082 xg RXE_RRRD "exclusive or 64" esame
-e30000000004 lg RXE_RRRD "load 64" esame
-e30000000014 lgf RXE_RRRD "load 64<32" esame
-e30000000015 lgh RXE_RRRD "load halfword 64" esame
-e30000000020 cg RXE_RRRD "compare 64" esame
-e30000000030 cgf RXE_RRRD "compare 64<32" esame
-e30000000008 ag RXE_RRRD "add 64" esame
-e30000000018 agf RXE_RRRD "add 64<32" esame
-e30000000009 sg RXE_RRRD "subtract 64" esame
-e30000000019 sgf RXE_RRRD "subtract 64<32" esame
-e3000000000a alg RXE_RRRD "add logical 64" esame
-e3000000001a algf RXE_RRRD "add logical 64<32" esame
-e3000000000b slg RXE_RRRD "subtract logical 64" esame
-e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame
-e3000000000c msg RXE_RRRD "multiply single 64" esame
-e3000000001c msgf RXE_RRRD "multiply single 64<32" esame
-ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame
-ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame
-eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame
-eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame
-eb000000000c srlg RSE_RRRD "shift right single logical 64" esame
-eb000000000d sllg RSE_RRRD "shift left single logical 64" esame
-eb000000000a srag RSE_RRRD "shift right single 64" esame
-eb000000000b slag RSE_RRRD "shift left single 64" esame
-eb0000000024 stmg RSE_RRRD "store multiple 64" esame
-eb0000000026 stmh RSE_RRRD "store multiple high" esame
-eb0000000004 lmg RSE_RRRD "load multiple 64" esame
-eb0000000096 lmh RSE_RRRD "load multiple high" esame
-ef lmd SS_RRRDRD3 "load multiple disjoint" esame
-eb000000000f tracg RSE_RRRD "trace 64" esame
-e30000000003 lrag RXE_RRRD "load real address 64" esame
-e50000000002 strag SSE_RDRD "store read address" esame
-eb0000000025 stctg RSE_RRRD "store control 64" esame
-eb000000002f lctlg RSE_RRRD "load control 64" esame
-eb0000000030 csg RSE_RRRD "compare and swap 64" esame
-eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame
-eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame
-eb000000002c stcmh RSE_RURD "store characters under mask high" esame
-eb0000000080 icmh RSE_RURD "insert characters under mask high" esame
-a700 tmlh RI_RU "test under mask low high" esame
-a702 tmhh RI_RU "test under mask high high" esame
-a701 tmll RI_RU "test under mask low low" esame
-a703 tmhl RI_RU "test under mask high low" esame
-c004 brcl RIL_UP "branch relative on condition long" esame
-c014 jgo RIL_0P "jump long on overflow / if ones" esame
-c024 jgh RIL_0P "jump long on high" esame
-c024 jgp RIL_0P "jump long on plus" esame
-c034 jgnle RIL_0P "jump long on not low or equal" esame
-c044 jgl RIL_0P "jump long on low" esame
-c044 jgm RIL_0P "jump long on minus / if mixed" esame
-c054 jgnhe RIL_0P "jump long on not high or equal" esame
-c064 jglh RIL_0P "jump long on low or high" esame
-c074 jgne RIL_0P "jump long on not equal" esame
-c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame
-c084 jge RIL_0P "jump long on equal" esame
-c084 jgz RIL_0P "jump long on zero / if zeros" esame
-c094 jgnlh RIL_0P "jump long on not low or high" esame
-c0a4 jghe RIL_0P "jump long on high or equal" esame
-c0b4 jgnl RIL_0P "jump long on not low" esame
-c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame
-c0c4 jgle RIL_0P "jump long on low or equal" esame
-c0d4 jgnh RIL_0P "jump long on not high" esame
-c0d4 jgnp RIL_0P "jump long on not plus" esame
-c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame
-c0f4 jg RIL_0P "jump long" esame
-c005 brasl RIL_RP "branch relative and save long" esame
-a707 brctg RI_RP "branch relative on count 64" esame
-a709 lghi RI_RI "load halfword immediate 64" esame
-a70b aghi RI_RI "add halfword immediate 64" esame
-a70d mghi RI_RI "multiply halfword immediate 64" esame
-a70f cghi RI_RI "compare halfword immediate 64" esame
-b925 sturg RRE_RR "store using real address 64" esame
-b90e eregg RRE_RR "extract stacked registers 64" esame
-b905 lurag RRE_RR "load using real address 64" esame
-b90c msgr RRE_RR "multiply single 64" esame
-b91c msgfr RRE_RR "multiply single 64<32" esame
-b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame
-b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame
-b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame
-b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame
-b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame
-b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame
-b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame
-b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame
-b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame
-b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame
-b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame
-b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame
-010b tam E "test addressing mode" esame
-010c sam24 E "set addressing mode 24" esame
-010d sam31 E "set addressing mode 31" esame
-010e sam64 E "set addressing mode 64" esame
-a500 iihh RI_RU "insert immediate high high" esame
-a501 iihl RI_RU "insert immediate high low" esame
-a502 iilh RI_RU "insert immediate low high" esame
-a503 iill RI_RU "insert immediate low low" esame
-a504 nihh RI_RU "and immediate high high" esame
-a505 nihl RI_RU "and immediate high low" esame
-a506 nilh RI_RU "and immediate low high" esame
-a507 nill RI_RU "and immediate low low" esame
-a508 oihh RI_RU "or immediate high high" esame
-a509 oihl RI_RU "or immediate high low" esame
-a50a oilh RI_RU "or immediate low high" esame
-a50b oill RI_RU "or immediate low low" esame
-a50c llihh RI_RU "load logical immediate high high" esame
-a50d llihl RI_RU "load logical immediate high low" esame
-a50e llilh RI_RU "load logical immediate low high" esame
-a50f llill RI_RU "load logical immediate low low" esame
-b2b1 stfl S_RD "store facility list" esame
-b2b2 lpswe S_RD "load psw extended" esame
-b90d dsgr RRE_RR "divide single 64" esame
-b90f lrvgr RRE_RR "load reversed 64" esame
-b916 llgfr RRE_RR "load logical 64<32" esame
-b917 llgtr RRE_RR "load logical thirty one bits" esame
-b91d dsgfr RRE_RR "divide single 64<32" esame
-b91f lrvr RRE_RR "load reversed 32" esame
-b986 mlgr RRE_RR "multiply logical 64" esame
-b987 dlgr RRE_RR "divide logical 64" esame
-b988 alcgr RRE_RR "add logical with carry 64" esame
-b989 slbgr RRE_RR "subtract logical with borrow 64" esame
-b98d epsw RRE_RR "extract psw" esame
-b996 mlr RRE_RR "multiply logical 32" esame
-b997 dlr RRE_RR "divide logical 32" esame
-b998 alcr RRE_RR "add logical with carry 32" esame
-b999 slbr RRE_RR "subtract logical with borrow 32" esame
-b99d esea RRE_R0 "extract and set extended authority" esame
-c000 larl RIL_RP "load address relative long" esame
-e3000000000d dsg RXE_RRRD "divide single 64" esame
-e3000000000f lrvg RXE_RRRD "load reversed 64" esame
-e30000000016 llgf RXE_RRRD "load logical 64<32" esame
-e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame
-e3000000001d dsgf RXE_RRRD "divide single 64<32" esame
-e3000000001e lrv RXE_RRRD "load reversed 32" esame
-e3000000001f lrvh RXE_RRRD "load reversed 16" esame
-e3000000002f strvg RXE_RRRD "store reversed 64" esame
-e3000000003e strv RXE_RRRD "store reversed 32" esame
-e3000000003f strvh RXE_RRRD "store reversed 64" esame
-e30000000086 mlg RXE_RRRD "multiply logical 64" esame
-e30000000087 dlg RXE_RRRD "divide logical 64" esame
-e30000000088 alcg RXE_RRRD "add logical with carry 64" esame
-e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame
-e3000000008e stpq RXE_RRRD "store pair to quadword" esame
-e3000000008f lpq RXE_RRRD "load pair from quadword" esame
-e30000000096 ml RXE_RRRD "multiply logical 32" esame
-e30000000097 dl RXE_RRRD "divide logical 32" esame
-e30000000098 alc RXE_RRRD "add logical with carry 32" esame
-e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame
-e30000000090 llgc RXE_RRRD "load logical character" esame
-e30000000091 llgh RXE_RRRD "load logical halfword" esame
-eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame
-eb000000001d rll RSE_RRRD "rotate left single logical 32" esame
-b278 stcke S_RD "store clock extended" esame
-b2a5 tre RRE_RR "translate extended" esame
-eb000000008e mvclu RSE_RRRD "move long unicode" esame
-e9 pka SS_L0RDRD "pack ascii" esame
-e1 pku SS_L0RDRD "pack unicode" esame
-b993 troo RRE_RR "translate one to one" esame
-b992 trot RRE_RR "translate one to two" esame
-b991 trto RRE_RR "translate two to one" esame
-b990 trtt RRE_RR "translate two to two" esame
-ea unpka SS_L0RDRD "unpack ascii" esame
-e2 unpku SS_L0RDRD "unpack unicode" esame
-b358 thder RRE_RR "convert short bfp to long hfp" esame
-b359 thdr RRE_RR "convert long bfp to long hfp" esame
-b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame
-b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame
-b374 lzer RRE_R0 "load short zero" esame
-b375 lzdr RRE_R0 "load long zero" esame
-b376 lzxr RRE_R0 "load extended zero" esame
+b946 bctgr RRE_RR "branch on count 64" z900 zarch
+b900 lpgr RRE_RR "load positive 64" z900 zarch
+b910 lpgfr RRE_RR "load positive 64<32" z900 zarch
+b901 lngr RRE_RR "load negative 64" z900 zarch
+b911 lngfr RRE_RR "load negative 64<32" z900 zarch
+b902 ltgr RRE_RR "load and test 64" z900 zarch
+b912 ltgfr RRE_RR "load and test 64<32" z900 zarch
+b903 lcgr RRE_RR "load complement 64" z900 zarch
+b913 lcgfr RRE_RR "load complement 64<32" z900 zarch
+b980 ngr RRE_RR "and 64" z900 zarch
+b921 clgr RRE_RR "compare logical 64" z900 zarch
+b931 clgfr RRE_RR "compare logical 64<32" z900 zarch
+b981 ogr RRE_RR "or 64" z900 zarch
+b982 xgr RRE_RR "exclusive or 64" z900 zarch
+b904 lgr RRE_RR "load 64" z900 zarch
+b914 lgfr RRE_RR "load 64<32" z900 zarch
+b920 cgr RRE_RR "compare 64" z900 zarch
+b930 cgfr RRE_RR "compare 64<32" z900 zarch
+b908 agr RRE_RR "add 64" z900 zarch
+b918 agfr RRE_RR "add 64<32" z900 zarch
+b909 sgr RRE_RR "subtract 64" z900 zarch zarch
+b919 sgfr RRE_RR "subtract 64<32" z900 zarch
+b90a algr RRE_RR "add logical 64" z900 zarch
+b91a algfr RRE_RR "add logical 64<32" z900 zarch
+b90b slgr RRE_RR "subtract logical 64" z900 zarch
+b91b slgfr RRE_RR "subtract logical 64<32" z900 zarch
+e30000000046 bctg RXE_RRRD "branch on count 64" z900 zarch
+e3000000002e cvdg RXE_RRRD "convert to decimal 64" z900 zarch
+e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch
+e30000000024 stg RXE_RRRD "store 64" z900 zarch
+e30000000080 ng RXE_RRRD "and 64" z900 zarch
+e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch
+e30000000031 clgf RXE_RRRD "comparee logical 64<32" z900 zarch
+e30000000081 og RXE_RRRD "or 64" z900 zarch
+e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch
+e30000000004 lg RXE_RRRD "load 64" z900 zarch
+e30000000014 lgf RXE_RRRD "load 64<32" z900 zarch
+e30000000015 lgh RXE_RRRD "load halfword 64" z900 zarch
+e30000000020 cg RXE_RRRD "compare 64" z900 zarch
+e30000000030 cgf RXE_RRRD "compare 64<32" z900 zarch
+e30000000008 ag RXE_RRRD "add 64" z900 zarch
+e30000000018 agf RXE_RRRD "add 64<32" z900 zarch
+e30000000009 sg RXE_RRRD "subtract 64" z900 zarch
+e30000000019 sgf RXE_RRRD "subtract 64<32" z900 zarch
+e3000000000a alg RXE_RRRD "add logical 64" z900 zarch
+e3000000001a algf RXE_RRRD "add logical 64<32" z900 zarch
+e3000000000b slg RXE_RRRD "subtract logical 64" z900 zarch
+e3000000001b slgf RXE_RRRD "subtract logical 64<32" z900 zarch
+e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch
+e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch
+ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch
+ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch
+eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch
+eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch
+eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch
+eb000000000d sllg RSE_RRRD "shift left single logical 64" z900 zarch
+eb000000000a srag RSE_RRRD "shift right single 64" z900 zarch
+eb000000000b slag RSE_RRRD "shift left single 64" z900 zarch
+eb0000000024 stmg RSE_RRRD "store multiple 64" z900 zarch
+eb0000000026 stmh RSE_RRRD "store multiple high" z900 zarch
+eb0000000004 lmg RSE_RRRD "load multiple 64" z900 zarch
+eb0000000096 lmh RSE_RRRD "load multiple high" z900 zarch
+ef lmd SS_RRRDRD3 "load multiple disjoint" z900 zarch
+eb000000000f tracg RSE_RRRD "trace 64" z900 zarch
+e30000000003 lrag RXE_RRRD "load real address 64" z900 zarch
+e50000000002 strag SSE_RDRD "store read address" z900 zarch
+eb0000000025 stctg RSE_RRRD "store control 64" z900 zarch
+eb000000002f lctlg RSE_RRRD "load control 64" z900 zarch
+eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch
+eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch
+eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch
+eb000000002c stcmh RSE_RURD "store characters under mask high" z900 zarch
+eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch
+a702 tmhh RI_RU "test under mask high high" z900 zarch
+a703 tmhl RI_RU "test under mask high low" z900 zarch
+c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
+c014 jgo RIL_0P "jump long on overflow / if ones" z900 esa,zarch
+c024 jgh RIL_0P "jump long on high" z900 esa,zarch
+c024 jgp RIL_0P "jump long on plus" z900 esa,zarch
+c034 jgnle RIL_0P "jump long on not low or equal" z900 esa,zarch
+c044 jgl RIL_0P "jump long on low" z900 esa,zarch
+c044 jgm RIL_0P "jump long on minus / if mixed" z900 esa,zarch
+c054 jgnhe RIL_0P "jump long on not high or equal" z900 esa,zarch
+c064 jglh RIL_0P "jump long on low or high" z900 esa,zarch
+c074 jgne RIL_0P "jump long on not equal" z900 esa,zarch
+c074 jgnz RIL_0P "jump long on not zero / if not zeros" z900 esa,zarch
+c084 jge RIL_0P "jump long on equal" z900 esa,zarch
+c084 jgz RIL_0P "jump long on zero / if zeros" z900 esa,zarch
+c094 jgnlh RIL_0P "jump long on not low or high" z900 esa,zarch
+c0a4 jghe RIL_0P "jump long on high or equal" z900 esa,zarch
+c0b4 jgnl RIL_0P "jump long on not low" z900 esa,zarch
+c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" z900 esa,zarch
+c0c4 jgle RIL_0P "jump long on low or equal" z900 esa,zarch
+c0d4 jgnh RIL_0P "jump long on not high" z900 esa,zarch
+c0d4 jgnp RIL_0P "jump long on not plus" z900 esa,zarch
+c0e4 jgno RIL_0P "jump long on not overflow / if not ones" z900 esa,zarch
+c0f4 jg RIL_0P "jump long" z900 esa,zarch
+c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch
+a707 brctg RI_RP "branch relative on count 64" z900 zarch
+a709 lghi RI_RI "load halfword immediate 64" z900 zarch
+a70b aghi RI_RI "add halfword immediate 64" z900 zarch
+a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch
+a70f cghi RI_RI "compare halfword immediate 64" z900 zarch
+b925 sturg RRE_RR "store using real address 64" z900 zarch
+b90e eregg RRE_RR "extract stacked registers 64" z900 zarch
+b905 lurag RRE_RR "load using real address 64" z900 zarch
+b90c msgr RRE_RR "multiply single 64" z900 zarch
+b91c msgfr RRE_RR "multiply single 64<32" z900 zarch
+b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" z900 zarch
+b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" z900 zarch
+b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" z900 zarch
+b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" z900 zarch
+b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" z900 zarch
+b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" z900 zarch
+b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" z900 zarch
+b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" z900 zarch
+b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" z900 zarch
+b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" z900 zarch
+b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" z900 zarch
+b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" z900 zarch
+010b tam E "test addressing mode" z900 esa,zarch
+010c sam24 E "set addressing mode 24" z900 esa,zarch
+010d sam31 E "set addressing mode 31" z900 esa,zarch
+010e sam64 E "set addressing mode 64" z900 zarch
+a500 iihh RI_RU "insert immediate high high" z900 zarch
+a501 iihl RI_RU "insert immediate high low" z900 zarch
+a502 iilh RI_RU "insert immediate low high" z900 zarch
+a503 iill RI_RU "insert immediate low low" z900 zarch
+a504 nihh RI_RU "and immediate high high" z900 zarch
+a505 nihl RI_RU "and immediate high low" z900 zarch
+a506 nilh RI_RU "and immediate low high" z900 zarch
+a507 nill RI_RU "and immediate low low" z900 zarch
+a508 oihh RI_RU "or immediate high high" z900 zarch
+a509 oihl RI_RU "or immediate high low" z900 zarch
+a50a oilh RI_RU "or immediate low high" z900 zarch
+a50b oill RI_RU "or immediate low low" z900 zarch
+a50c llihh RI_RU "load logical immediate high high" z900 zarch
+a50d llihl RI_RU "load logical immediate high low" z900 zarch
+a50e llilh RI_RU "load logical immediate low high" z900 zarch
+a50f llill RI_RU "load logical immediate low low" z900 zarch
+b2b1 stfl S_RD "store facility list" z900 esa,zarch
+b2b2 lpswe S_RD "load psw extended" z900 zarch
+b90d dsgr RRE_RR "divide single 64" z900 zarch
+b90f lrvgr RRE_RR "load reversed 64" z900 zarch
+b916 llgfr RRE_RR "load logical 64<32" z900 zarch
+b917 llgtr RRE_RR "load logical thirty one bits" z900 zarch
+b91d dsgfr RRE_RR "divide single 64<32" z900 zarch
+b91f lrvr RRE_RR "load reversed 32" z900 esa,zarch
+b986 mlgr RRE_RR "multiply logical 64" z900 zarch
+b987 dlgr RRE_RR "divide logical 64" z900 zarch
+b988 alcgr RRE_RR "add logical with carry 64" z900 zarch
+b989 slbgr RRE_RR "subtract logical with borrow 64" z900 zarch
+b98d epsw RRE_RR "extract psw" z900 esa,zarch
+b996 mlr RRE_RR "multiply logical 32" z900 esa,zarch
+b997 dlr RRE_RR "divide logical 32" z900 esa,zarch
+b998 alcr RRE_RR "add logical with carry 32" z900 esa,zarch
+b999 slbr RRE_RR "subtract logical with borrow 32" z900 esa,zarch
+b99d esea RRE_R0 "extract and set extended authority" z900 zarch
+c000 larl RIL_RP "load address relative long" z900 esa,zarch
+e3000000000d dsg RXE_RRRD "divide single 64" z900 zarch
+e3000000000f lrvg RXE_RRRD "load reversed 64" z900 zarch
+e30000000016 llgf RXE_RRRD "load logical 64<32" z900 zarch
+e30000000017 llgt RXE_RRRD "load logical thirty one bits" z900 zarch
+e3000000001d dsgf RXE_RRRD "divide single 64<32" z900 zarch
+e3000000001e lrv RXE_RRRD "load reversed 32" z900 esa,zarch
+e3000000001f lrvh RXE_RRRD "load reversed 16" z900 esa,zarch
+e3000000002f strvg RXE_RRRD "store reversed 64" z900 zarch
+e3000000003e strv RXE_RRRD "store reversed 32" z900 esa,zarch
+e3000000003f strvh RXE_RRRD "store reversed 64" z900 esa,zarch
+e30000000086 mlg RXE_RRRD "multiply logical 64" z900 zarch
+e30000000087 dlg RXE_RRRD "divide logical 64" z900 zarch
+e30000000088 alcg RXE_RRRD "add logical with carry 64" z900 zarch
+e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" z900 zarch
+e3000000008e stpq RXE_RRRD "store pair to quadword" z900 zarch
+e3000000008f lpq RXE_RRRD "load pair from quadword" z900 zarch
+e30000000096 ml RXE_RRRD "multiply logical 32" z900 esa,zarch
+e30000000097 dl RXE_RRRD "divide logical 32" z900 esa,zarch
+e30000000098 alc RXE_RRRD "add logical with carry 32" z900 esa,zarch
+e30000000099 slb RXE_RRRD "subtract logical with borrow 32" z900 esa,zarch
+e30000000090 llgc RXE_RRRD "load logical character" z900 zarch
+e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch
+eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch
+eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch