This commit was manufactured by cvs2svn to create branchezannoni_pie-20040323-branchpoint

'ezannoni_pie-20040323-branch'.

Sprout from gdb_6_1-branch 2004-03-12 17:46:28 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_1-branch'.'
Cherrypick from gdb_6_1-branch 2004-03-09 17:34:40 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_1-branch'.':
    gdb/testsuite/gdb.cp/classes.cc
Cherrypick from master 2004-03-23 23:05:52 UTC Paul Brook <paul@codesourcery.com> '	* bfd/elf32-arm.h (arm_print_private_bfd_data): Add EABI v3.':
    ChangeLog
    Makefile.in
    Makefile.tpl
    bfd/ChangeLog
    bfd/Makefile.am
    bfd/Makefile.in
    bfd/aclocal.m4
    bfd/aix386-core.c
    bfd/archive.c
    bfd/archures.c
    bfd/bfd-in.h
    bfd/bfd-in2.h
    bfd/coff-tic54x.c
    bfd/config.bfd
    bfd/config.in
    bfd/configure
    bfd/configure.in
    bfd/cpu-frv.c
    bfd/cpu-sh.c
    bfd/doc/ChangeLog
    bfd/doc/Makefile.in
    bfd/dwarf2.c
    bfd/elf-bfd.h
    bfd/elf-hppa.h
    bfd/elf-m10200.c
    bfd/elf-m10300.c
    bfd/elf.c
    bfd/elf32-arm.h
    bfd/elf32-avr.c
    bfd/elf32-cris.c
    bfd/elf32-d10v.c
    bfd/elf32-fr30.c
    bfd/elf32-frv.c
    bfd/elf32-h8300.c
    bfd/elf32-hppa.c
    bfd/elf32-i370.c
    bfd/elf32-i386.c
    bfd/elf32-i860.c
    bfd/elf32-ip2k.c
    bfd/elf32-iq2000.c
    bfd/elf32-m32r.c
    bfd/elf32-m68hc1x.c
    bfd/elf32-m68k.c
    bfd/elf32-mcore.c
    bfd/elf32-msp430.c
    bfd/elf32-openrisc.c
    bfd/elf32-ppc.c
    bfd/elf32-s390.c
    bfd/elf32-sh.c
    bfd/elf32-sparc.c
    bfd/elf32-v850.c
    bfd/elf32-vax.c
    bfd/elf32-xstormy16.c
    bfd/elf32-xtensa.c
    bfd/elf64-alpha.c
    bfd/elf64-hppa.c
    bfd/elf64-mmix.c
    bfd/elf64-ppc.c
    bfd/elf64-s390.c
    bfd/elf64-sh64.c
    bfd/elf64-sparc.c
    bfd/elf64-x86-64.c
    bfd/elflink.c
    bfd/elflink.h
    bfd/elfxx-ia64.c
    bfd/elfxx-mips.c
    bfd/hppabsd-core.c
    bfd/hpux-core.c
    bfd/irix-core.c
    bfd/libaout.h
    bfd/libbfd.c
    bfd/linker.c
    bfd/mach-o.c
    bfd/netbsd-core.c
    bfd/osf-core.c
    bfd/pdp11.c
    bfd/po/bfd.pot
    bfd/ptrace-core.c
    bfd/sco5-core.c
    bfd/targets.c
    bfd/trad-core.c
    bfd/version.h
    config/ChangeLog
    config/accross.m4
    config/acx.m4
    configure
    configure.in
    cpu/ChangeLog
    cpu/frv.cpu
    cpu/frv.opc
    gdb/ChangeLog
    gdb/MAINTAINERS
    gdb/Makefile.in
    gdb/NEWS
    gdb/PROBLEMS
    gdb/alpha-linux-tdep.c
    gdb/alpha-osf1-tdep.c
    gdb/alpha-tdep.c
    gdb/alphafbsd-tdep.c
    gdb/alphanbsd-tdep.c
    gdb/amd64-linux-nat.c
    gdb/amd64-linux-tdep.c
    gdb/amd64-nat.c
    gdb/amd64-tdep.c
    gdb/amd64-tdep.h
    gdb/amd64bsd-nat.c
    gdb/amd64fbsd-nat.c
    gdb/amd64nbsd-tdep.c
    gdb/amd64obsd-tdep.c
    gdb/arch-utils.c
    gdb/arch-utils.h
    gdb/arm-tdep.c
    gdb/bcache.c
    gdb/blockframe.c
    gdb/breakpoint.c
    gdb/config/alpha/fbsd.mt
    gdb/config/alpha/nm-fbsd.h
    gdb/config/arm/tm-embed.h
    gdb/config/arm/tm-linux.h
    gdb/config/frv/frv.mt
    gdb/config/frv/tm-frv.h
    gdb/config/i386/nm-fbsd.h
    gdb/config/i386/nm-fbsd64.h
    gdb/config/i386/nm-obsd.h
    gdb/config/ia64/tm-aix.h
    gdb/config/ia64/tm-linux.h
    gdb/config/m68k/tm-nbsd.h
    gdb/config/mips/tm-irix5.h
    gdb/config/mips/tm-irix6.h
    gdb/config/mips/tm-linux.h
    gdb/config/mips/tm-nbsd.h
    gdb/config/nm-bsd.h
    gdb/config/pa/tm-hppa.h
    gdb/config/pa/tm-hppa64.h
    gdb/config/powerpc/tm-linux.h
    gdb/config/rs6000/tm-rs6000.h
    gdb/config/sparc/nm-fbsd.h
    gdb/config/vax/tm-vaxbsd.h
    gdb/cp-namespace.c
    gdb/cris-tdep.c
    gdb/doc/ChangeLog
    gdb/doc/gdb.texinfo
    gdb/doc/gdbint.texinfo
    gdb/dummy-frame.c
    gdb/dummy-frame.h
    gdb/dwarf2-frame.c
    gdb/dwarf2read.c
    gdb/frame-base.c
    gdb/frame-unwind.c
    gdb/frame-unwind.h
    gdb/frame.c
    gdb/frame.h
    gdb/frv-linux-tdep.c
    gdb/frv-tdep.c
    gdb/frv-tdep.h
    gdb/gdb_obstack.h
    gdb/gdbarch.c
    gdb/gdbarch.h
    gdb/gdbarch.sh
    gdb/gdbserver/ChangeLog
    gdb/gdbserver/Makefile.in
    gdb/gdbserver/gdbreplay.c
    gdb/gdbserver/linux-low.c
    gdb/gdbserver/server.c
    gdb/gdbserver/server.h
    gdb/gdbserver/target.c
    gdb/gdbserver/target.h
    gdb/gdbserver/utils.c
    gdb/gdbtypes.c
    gdb/gnu-v3-abi.c
    gdb/h8300-tdep.c
    gdb/hppa-hpux-tdep.c
    gdb/hppa-tdep.c
    gdb/i386-interix-tdep.c
    gdb/i386-linux-tdep.c
    gdb/i386-nat.c
    gdb/i386-nto-tdep.c
    gdb/i386-sol2-tdep.c
    gdb/i386-tdep.c
    gdb/i386-tdep.h
    gdb/i386bsd-nat.c
    gdb/i386bsd-tdep.c
    gdb/i386nbsd-tdep.c
    gdb/i386obsd-tdep.c
    gdb/i387-tdep.c
    gdb/i387-tdep.h
    gdb/ia64-tdep.c
    gdb/infcall.c
    gdb/infcmd.c
    gdb/inferior.h
    gdb/infrun.c
    gdb/libunwind-frame.c
    gdb/lin-lwp.c
    gdb/m68hc11-tdep.c
    gdb/m68k-tdep.c
    gdb/m68klinux-tdep.c
    gdb/mcore-tdep.c
    gdb/mips-linux-tdep.c
    gdb/mips-tdep.c
    gdb/mipsnbsd-tdep.c
    gdb/mn10300-tdep.c
    gdb/ppc-linux-nat.c
    gdb/ppc-linux-tdep.c
    gdb/ppc-tdep.h
    gdb/ppcnbsd-tdep.c
    gdb/regcache.c
    gdb/reggroups.c
    gdb/remote-m32r-sdi.c
    gdb/remote.c
    gdb/rs6000-tdep.c
    gdb/s390-tdep.c
    gdb/sh-tdep.c
    gdb/sh64-tdep.c
    gdb/shnbsd-tdep.c
    gdb/solib-frv.c
    gdb/solib-svr4.c
    gdb/solib-svr4.h
    gdb/solib.c
    gdb/solist.h
    gdb/sparc-linux-tdep.c
    gdb/sparc-sol2-tdep.c
    gdb/sparc-tdep.c
    gdb/sparc64-sol2-tdep.c
    gdb/sparc64fbsd-tdep.c
    gdb/sparc64nbsd-tdep.c
    gdb/sparc64obsd-tdep.c
    gdb/sparcnbsd-tdep.c
    gdb/sparcobsd-tdep.c
    gdb/stabsread.c
    gdb/stack.c
    gdb/symtab.h
    gdb/target.c
    gdb/testsuite/ChangeLog
    gdb/testsuite/gdb.asm/openbsd.inc
    gdb/testsuite/gdb.base/auxv.c
    gdb/testsuite/gdb.base/auxv.exp
    gdb/testsuite/gdb.base/pc-fp.exp
    gdb/testsuite/gdb.base/watchpoint.exp
    gdb/testsuite/gdb.cp/classes.exp
    gdb/testsuite/gdb.cp/local.exp
    gdb/testsuite/gdb.cp/misc.cc
    gdb/testsuite/gdb.cp/rtti.exp
    gdb/testsuite/gdb.cp/rtti.h
    gdb/testsuite/gdb.cp/rtti1.cc
    gdb/testsuite/gdb.cp/rtti2.cc
    gdb/testsuite/gdb.cp/templates.exp
    gdb/trad-frame.c
    gdb/trad-frame.h
    gdb/tramp-frame.c
    gdb/tramp-frame.h
    gdb/tui/tui-data.c
    gdb/tui/tui-data.h
    gdb/tui/tui-layout.c
    gdb/tui/tui-regs.c
    gdb/tui/tui-regs.h
    gdb/tui/tui-win.c
    gdb/tui/tui-win.h
    gdb/user-regs.c
    gdb/v850-tdep.c
    gdb/version.in
    gdb/xstormy16-tdep.c
    include/ChangeLog
    include/bfdlink.h
    include/elf/ChangeLog
    include/elf/arm.h
    include/elf/frv.h
    include/elf/sh.h
    include/opcode/ChangeLog
    include/opcode/i386.h
    include/opcode/ppc.h
    libiberty/ChangeLog
    libiberty/Makefile.in
    libiberty/config.in
    libiberty/configure
    libiberty/configure.ac
    libiberty/pex-common.h
    libiberty/pex-unix.c
    libiberty/testsuite/test-demangle.c
    opcodes/ChangeLog
    opcodes/aclocal.m4
    opcodes/config.in
    opcodes/configure
    opcodes/frv-asm.c
    opcodes/frv-desc.c
    opcodes/frv-desc.h
    opcodes/frv-dis.c
    opcodes/frv-ibld.c
    opcodes/frv-opc.c
    opcodes/frv-opc.h
    opcodes/i386-dis.c
    opcodes/po/POTFILES.in
    opcodes/po/de.po
    opcodes/po/opcodes.pot
    opcodes/ppc-dis.c
    opcodes/ppc-opc.c
    opcodes/sh-dis.c
    opcodes/sh-opc.h
    opcodes/sparc-dis.c
    sim/ChangeLog
    sim/MAINTAINERS
    sim/frv/ChangeLog
    sim/frv/Makefile.in
    sim/frv/arch.c
    sim/frv/arch.h
    sim/frv/cache.c
    sim/frv/cpu.h
    sim/frv/cpuall.h
    sim/frv/decode.c
    sim/frv/decode.h
    sim/frv/frv-sim.h
    sim/frv/frv.c
    sim/frv/interrupts.c
    sim/frv/memory.c
    sim/frv/mloop.in
    sim/frv/model.c
    sim/frv/profile-fr450.c
    sim/frv/profile.c
    sim/frv/registers.c
    sim/frv/sem.c
    sim/frv/traps.c
    sim/testsuite/ChangeLog
    sim/testsuite/sim/frv/allinsn.exp
    sim/testsuite/sim/frv/fr400/addss.cgs
    sim/testsuite/sim/frv/fr400/allinsn.exp
    sim/testsuite/sim/frv/fr400/scutss.cgs
    sim/testsuite/sim/frv/fr400/slass.cgs
    sim/testsuite/sim/frv/fr400/smass.cgs
    sim/testsuite/sim/frv/fr400/smsss.cgs
    sim/testsuite/sim/frv/fr400/smu.cgs
    sim/testsuite/sim/frv/fr400/subss.cgs
    sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
    sim/testsuite/sim/frv/interrupts/fp_exception.cgs
    sim/testsuite/sim/frv/mqlclrhs.cgs
    sim/testsuite/sim/frv/mqlmths.cgs
    sim/testsuite/sim/frv/mqsllhi.cgs
    sim/testsuite/sim/frv/mqsrahi.cgs
Delete:
    gdb/amd64-linux-tdep.h
    gdb/config/alpha/tm-fbsd.h
    libiberty/acconfig.h

20 files changed, 2588 insertions, 1654 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 783165b..947ee4f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,95 @@
+2004-03-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
+	PPC_OPERANDS_GPR_0.
+	* ppc-opc.c (RA0): Define.
+	(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
+	(RAOPT): Rename from RAO.  Update all uses.
+	(powerpc_opcodes): Use RA0 as appropriate.
+
+2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
+
+2004-03-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* sparc-dis.c (print_insn_sparc): Update getword prototype.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* i386-dis.c (GRPPLOCK): Delete.
+	(grps): Delete GRPPLOCK entry.
+
+2004-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
+	(M, Mp): Use OP_M.
+	(None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
+	(GRPPADLCK): Define.
+	(dis386): Use NOP_Fixup on "nop".
+	(dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
+	(twobyte_has_modrm): Set for 0xa7.
+	(padlock_table): Delete.  Move to..
+	(grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
+	and clflush.
+	(print_insn): Revert PADLOCK_SPECIAL code.
+	(OP_E): Delete sfence, lfence, mfence checks.
+
+2004-03-12  Jakub Jelinek  <jakub@redhat.com>
+
+	* i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
+	(INVLPG_Fixup): New function.
+	(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
+	(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
+	(padlock_table): New struct with PadLock instructions.
+	(print_insn): Handle PADLOCK_SPECIAL.
+
+2004-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (grps): Use clflush by default for 0x0fae/7.
+	(OP_E): Twiddle clflush to sfence here.
+
+2004-03-08  Nick Clifton  <nickc@redhat.com>
+
+	* po/de.po: Updated German translation.
+
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
+	nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
+	* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
+	accordingly.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frv-asm.c: Regenerate.
+	* frv-desc.c: Regenerate.
+	* frv-desc.h: Regenerate.
+	* frv-dis.c: Regenerate.
+	* frv-ibld.c: Regenerate.
+	* frv-opc.c: Regenerate.
+	* frv-opc.h: Regenerate.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frv-desc.c, frv-opc.c: Regenerate.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
+
 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 
 	* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
@@ -17,8 +109,8 @@
 	Adjust the bit patterns in a few comments.
 
 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
-                                                                                
-        * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
+
+	* ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 
 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 
@@ -29,13 +121,13 @@
 	* ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 
 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
- 
-        * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
-        mtivor32, mtivor33, mtivor34.
+
+	* ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
+	mtivor32, mtivor33, mtivor34.
 
 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
- 
-        * ppc-opc.c (powerpc_opcodes): Add mfmcar.
+
+	* ppc-opc.c (powerpc_opcodes): Add mfmcar.
 
 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 
diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4
index 92732d3..a9b0b29 100644
--- a/opcodes/aclocal.m4
+++ b/opcodes/aclocal.m4
@@ -1,4 +1,4 @@
-dnl aclocal.m4 generated automatically by aclocal 1.4-p5
+dnl aclocal.m4 generated automatically by aclocal 1.4-p6
 
 dnl Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc.
 dnl This file is free software; the Free Software Foundation
@@ -35,7 +35,16 @@ AC_SUBST(bfdlibdir)
 AC_SUBST(bfdincludedir)
 ])
 
-#serial 1
+# isc-posix.m4 serial 2 (gettext-0.11.2)
+dnl Copyright (C) 1995-2002 Free Software Foundation, Inc.
+dnl This file is free software, distributed under the terms of the GNU
+dnl General Public License.  As a special exception to the GNU General
+dnl Public License, this file may be distributed as part of a program
+dnl that contains a configuration script generated by Autoconf, under
+dnl the same distribution terms as the rest of that program.
+
+# This file is not needed with autoconf-2.53 and newer.  Remove it in 2005.
+
 # This test replaces the one in autoconf.
 # Currently this macro should have the same name as the autoconf macro
 # because gettext's gettext.m4 (distributed in the automake package)
@@ -63,7 +72,8 @@ dnl Usage:
 dnl AM_INIT_AUTOMAKE(package,version, [no-define])
 
 AC_DEFUN([AM_INIT_AUTOMAKE],
-[AC_REQUIRE([AC_PROG_INSTALL])
+[AC_REQUIRE([AM_SET_CURRENT_AUTOMAKE_VERSION])dnl
+AC_REQUIRE([AC_PROG_INSTALL])
 PACKAGE=[$1]
 AC_SUBST(PACKAGE)
 VERSION=[$2]
@@ -79,13 +89,42 @@ AC_REQUIRE([AM_SANITY_CHECK])
 AC_REQUIRE([AC_ARG_PROGRAM])
 dnl FIXME This is truly gross.
 missing_dir=`cd $ac_aux_dir && pwd`
-AM_MISSING_PROG(ACLOCAL, aclocal, $missing_dir)
+AM_MISSING_PROG(ACLOCAL, aclocal-${am__api_version}, $missing_dir)
 AM_MISSING_PROG(AUTOCONF, autoconf, $missing_dir)
-AM_MISSING_PROG(AUTOMAKE, automake, $missing_dir)
+AM_MISSING_PROG(AUTOMAKE, automake-${am__api_version}, $missing_dir)
 AM_MISSING_PROG(AUTOHEADER, autoheader, $missing_dir)
 AM_MISSING_PROG(MAKEINFO, makeinfo, $missing_dir)
 AC_REQUIRE([AC_PROG_MAKE_SET])])
 
+# Copyright 2002  Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+
+# AM_AUTOMAKE_VERSION(VERSION)
+# ----------------------------
+# Automake X.Y traces this macro to ensure aclocal.m4 has been
+# generated from the m4 files accompanying Automake X.Y.
+AC_DEFUN([AM_AUTOMAKE_VERSION],[am__api_version="1.4"])
+
+# AM_SET_CURRENT_AUTOMAKE_VERSION
+# -------------------------------
+# Call AM_AUTOMAKE_VERSION so it can be traced.
+# This function is AC_REQUIREd by AC_INIT_AUTOMAKE.
+AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION],
+	 [AM_AUTOMAKE_VERSION([1.4-p6])])
+
 #
 # Check to make sure that the build environment is sane.
 #
diff --git a/opcodes/config.in b/opcodes/config.in
index 5caef55..1185e89 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -106,6 +106,12 @@
 /* Define if you have the <sys/param.h> header file.  */
 #undef HAVE_SYS_PARAM_H
 
+/* Define if you have the <sys/stat.h> header file.  */
+#undef HAVE_SYS_STAT_H
+
+/* Define if you have the <sys/types.h> header file.  */
+#undef HAVE_SYS_TYPES_H
+
 /* Define if you have the <unistd.h> header file.  */
 #undef HAVE_UNISTD_H
 
diff --git a/opcodes/configure b/opcodes/configure
index 4a95a9a..6cff4e7 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -57,7 +57,6 @@ program_suffix=NONE
 program_transform_name=s,x,x,
 silent=
 site=
-sitefile=
 srcdir=
 target=NONE
 verbose=
@@ -172,7 +171,6 @@ Configuration:
   --help                  print this message
   --no-create             do not create output files
   --quiet, --silent       do not print \`checking...' messages
-  --site-file=FILE        use FILE as the site file
   --version               print the version of autoconf that created configure
 Directory and file names:
   --prefix=PREFIX         install architecture-independent files in PREFIX
@@ -343,11 +341,6 @@ EOF
   -site=* | --site=* | --sit=*)
     site="$ac_optarg" ;;
 
-  -site-file | --site-file | --site-fil | --site-fi | --site-f)
-    ac_prev=sitefile ;;
-  -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*)
-    sitefile="$ac_optarg" ;;
-
   -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
     ac_prev=srcdir ;;
   -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
@@ -513,16 +506,12 @@ fi
 srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
 
 # Prefer explicitly selected file to automatically selected ones.
-if test -z "$sitefile"; then
-  if test -z "$CONFIG_SITE"; then
-    if test "x$prefix" != xNONE; then
-      CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
-    else
-      CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
-    fi
+if test -z "$CONFIG_SITE"; then
+  if test "x$prefix" != xNONE; then
+    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+  else
+    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
   fi
-else
-  CONFIG_SITE="$sitefile"
 fi
 for ac_site_file in $CONFIG_SITE; do
   if test -r "$ac_site_file"; then
@@ -561,12 +550,12 @@ else
 fi
 
 echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:565: checking for Cygwin environment" >&5
+echo "configure:554: checking for Cygwin environment" >&5
 if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 570 "configure"
+#line 559 "configure"
 #include "confdefs.h"
 
 int main() {
@@ -577,7 +566,7 @@ int main() {
 return __CYGWIN__;
 ; return 0; }
 EOF
-if { (eval echo configure:581: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:570: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_cygwin=yes
 else
@@ -594,19 +583,19 @@ echo "$ac_t""$ac_cv_cygwin" 1>&6
 CYGWIN=
 test "$ac_cv_cygwin" = yes && CYGWIN=yes
 echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:598: checking for mingw32 environment" >&5
+echo "configure:587: checking for mingw32 environment" >&5
 if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 603 "configure"
+#line 592 "configure"
 #include "confdefs.h"
 
 int main() {
 return __MINGW32__;
 ; return 0; }
 EOF
-if { (eval echo configure:610: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:599: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_mingw32=yes
 else
@@ -671,7 +660,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
 fi
 
 echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:675: checking host system type" >&5
+echo "configure:664: checking host system type" >&5
 
 host_alias=$host
 case "$host_alias" in
@@ -692,7 +681,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$host" 1>&6
 
 echo $ac_n "checking target system type""... $ac_c" 1>&6
-echo "configure:696: checking target system type" >&5
+echo "configure:685: checking target system type" >&5
 
 target_alias=$target
 case "$target_alias" in
@@ -710,7 +699,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$target" 1>&6
 
 echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:714: checking build system type" >&5
+echo "configure:703: checking build system type" >&5
 
 build_alias=$build
 case "$build_alias" in
@@ -734,7 +723,7 @@ test "$host_alias" != "$target_alias" &&
 
 
         echo $ac_n "checking for strerror in -lcposix""... $ac_c" 1>&6
-echo "configure:738: checking for strerror in -lcposix" >&5
+echo "configure:727: checking for strerror in -lcposix" >&5
 ac_lib_var=`echo cposix'_'strerror | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -742,7 +731,7 @@ else
   ac_save_LIBS="$LIBS"
 LIBS="-lcposix  $LIBS"
 cat > conftest.$ac_ext <<EOF
-#line 746 "configure"
+#line 735 "configure"
 #include "confdefs.h"
 /* Override any gcc2 internal prototype to avoid an error.  */
 /* We use char because int might match the return type of a gcc2
@@ -753,7 +742,7 @@ int main() {
 strerror()
 ; return 0; }
 EOF
-if { (eval echo configure:757: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:746: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_lib_$ac_lib_var=yes"
 else
@@ -781,6 +770,7 @@ fi
 # number that BFD is using.
 BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ 	]*\([^ 	]*\)[ 	]*).*/\1/p' < ${srcdir}/../bfd/configure.in`
 
+am__api_version="1.4"
 # Find a good install program.  We prefer a C program (faster),
 # so one script is as good as another.  But avoid the broken or
 # incompatible versions:
@@ -793,7 +783,7 @@ BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ 	]*\([^ 	]*\)[ 	]*).*/\1/p' < ${
 # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
 # ./install, which can be erroneously created by make from ./install.sh.
 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:797: checking for a BSD compatible install" >&5
+echo "configure:787: checking for a BSD compatible install" >&5
 if test -z "$INSTALL"; then
 if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -846,7 +836,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
 test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
 
 echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6
-echo "configure:850: checking whether build environment is sane" >&5
+echo "configure:840: checking whether build environment is sane" >&5
 # Just in case
 sleep 1
 echo timestamp > conftestfile
@@ -903,7 +893,7 @@ test "$program_suffix" != NONE &&
 test "$program_transform_name" = "" && program_transform_name="s,x,x,"
 
 echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
-echo "configure:907: checking whether ${MAKE-make} sets \${MAKE}" >&5
+echo "configure:897: checking whether ${MAKE-make} sets \${MAKE}" >&5
 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -948,21 +938,21 @@ EOF
 
 
 missing_dir=`cd $ac_aux_dir && pwd`
-echo $ac_n "checking for working aclocal""... $ac_c" 1>&6
-echo "configure:953: checking for working aclocal" >&5
+echo $ac_n "checking for working aclocal-${am__api_version}""... $ac_c" 1>&6
+echo "configure:943: checking for working aclocal-${am__api_version}" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
-if (aclocal --version) < /dev/null > /dev/null 2>&1; then
-   ACLOCAL=aclocal
+if (aclocal-${am__api_version} --version) < /dev/null > /dev/null 2>&1; then
+   ACLOCAL=aclocal-${am__api_version}
    echo "$ac_t""found" 1>&6
 else
-   ACLOCAL="$missing_dir/missing aclocal"
+   ACLOCAL="$missing_dir/missing aclocal-${am__api_version}"
    echo "$ac_t""missing" 1>&6
 fi
 
 echo $ac_n "checking for working autoconf""... $ac_c" 1>&6
-echo "configure:966: checking for working autoconf" >&5
+echo "configure:956: checking for working autoconf" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -974,21 +964,21 @@ else
    echo "$ac_t""missing" 1>&6
 fi
 
-echo $ac_n "checking for working automake""... $ac_c" 1>&6
-echo "configure:979: checking for working automake" >&5
+echo $ac_n "checking for working automake-${am__api_version}""... $ac_c" 1>&6
+echo "configure:969: checking for working automake-${am__api_version}" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
-if (automake --version) < /dev/null > /dev/null 2>&1; then
-   AUTOMAKE=automake
+if (automake-${am__api_version} --version) < /dev/null > /dev/null 2>&1; then
+   AUTOMAKE=automake-${am__api_version}
    echo "$ac_t""found" 1>&6
 else
-   AUTOMAKE="$missing_dir/missing automake"
+   AUTOMAKE="$missing_dir/missing automake-${am__api_version}"
    echo "$ac_t""missing" 1>&6
 fi
 
 echo $ac_n "checking for working autoheader""... $ac_c" 1>&6
-echo "configure:992: checking for working autoheader" >&5
+echo "configure:982: checking for working autoheader" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1001,7 +991,7 @@ else
 fi
 
 echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6
-echo "configure:1005: checking for working makeinfo" >&5
+echo "configure:995: checking for working makeinfo" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1024,7 +1014,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ar; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1028: checking for $ac_word" >&5
+echo "configure:1018: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1056,7 +1046,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1060: checking for $ac_word" >&5
+echo "configure:1050: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1088,7 +1078,7 @@ if test -n "$ac_tool_prefix"; then
   # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1092: checking for $ac_word" >&5
+echo "configure:1082: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1194,7 +1184,7 @@ fi
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1198: checking for $ac_word" >&5
+echo "configure:1188: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1224,7 +1214,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1228: checking for $ac_word" >&5
+echo "configure:1218: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1275,7 +1265,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1279: checking for $ac_word" >&5
+echo "configure:1269: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1307,7 +1297,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:1311: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:1301: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -1318,12 +1308,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 1322 "configure"
+#line 1312 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:1327: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1317: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -1349,12 +1339,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:1353: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:1343: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:1358: checking whether we are using GNU C" >&5
+echo "configure:1348: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1363,7 +1353,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1367: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1357: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -1382,7 +1372,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:1386: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:1376: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1425,7 +1415,7 @@ ac_prog=ld
 if test "$GCC" = yes; then
   # Check if gcc -print-prog-name=ld gives a path.
   echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6
-echo "configure:1429: checking for ld used by GCC" >&5
+echo "configure:1419: checking for ld used by GCC" >&5
   case $host in
   *-*-mingw*)
     # gcc leaves a trailing carriage return which upsets mingw
@@ -1455,10 +1445,10 @@ echo "configure:1429: checking for ld used by GCC" >&5
   esac
 elif test "$with_gnu_ld" = yes; then
   echo $ac_n "checking for GNU ld""... $ac_c" 1>&6
-echo "configure:1459: checking for GNU ld" >&5
+echo "configure:1449: checking for GNU ld" >&5
 else
   echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6
-echo "configure:1462: checking for non-GNU ld" >&5
+echo "configure:1452: checking for non-GNU ld" >&5
 fi
 if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -1493,7 +1483,7 @@ else
 fi
 test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; }
 echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6
-echo "configure:1497: checking if the linker ($LD) is GNU ld" >&5
+echo "configure:1487: checking if the linker ($LD) is GNU ld" >&5
 if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1510,7 +1500,7 @@ with_gnu_ld=$lt_cv_prog_gnu_ld
 
 
 echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6
-echo "configure:1514: checking for $LD option to reload object files" >&5
+echo "configure:1504: checking for $LD option to reload object files" >&5
 if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1522,7 +1512,7 @@ reload_flag=$lt_cv_ld_reload_flag
 test -n "$reload_flag" && reload_flag=" $reload_flag"
 
 echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6
-echo "configure:1526: checking for BSD-compatible nm" >&5
+echo "configure:1516: checking for BSD-compatible nm" >&5
 if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1560,7 +1550,7 @@ NM="$lt_cv_path_NM"
 echo "$ac_t""$NM" 1>&6
 
 echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6
-echo "configure:1564: checking whether ln -s works" >&5
+echo "configure:1554: checking whether ln -s works" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1581,7 +1571,7 @@ else
 fi
 
 echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6
-echo "configure:1585: checking how to recognise dependant libraries" >&5
+echo "configure:1575: checking how to recognise dependant libraries" >&5
 if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1754,13 +1744,13 @@ file_magic_cmd=$lt_cv_file_magic_cmd
 deplibs_check_method=$lt_cv_deplibs_check_method
 
 echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1758: checking for object suffix" >&5
+echo "configure:1748: checking for object suffix" >&5
 if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   rm -f conftest*
 echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1764: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1754: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   for ac_file in conftest.*; do
     case $ac_file in
     *.c) ;;
@@ -1780,7 +1770,7 @@ ac_objext=$ac_cv_objext
 
 
 echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1784: checking for executable suffix" >&5
+echo "configure:1774: checking for executable suffix" >&5
 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1790,10 +1780,10 @@ else
   rm -f conftest*
   echo 'int main () { return 0; }' > conftest.$ac_ext
   ac_cv_exeext=
-  if { (eval echo configure:1794: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+  if { (eval echo configure:1784: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
     for file in conftest.*; do
       case $file in
-      *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+      *.c | *.o | *.obj) ;;
       *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
       esac
     done
@@ -1817,7 +1807,7 @@ case $deplibs_check_method in
 file_magic*)
   if test "$file_magic_cmd" = '$MAGIC_CMD'; then
     echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6
-echo "configure:1821: checking for ${ac_tool_prefix}file" >&5
+echo "configure:1811: checking for ${ac_tool_prefix}file" >&5
 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1879,7 +1869,7 @@ fi
 if test -z "$lt_cv_path_MAGIC_CMD"; then
   if test -n "$ac_tool_prefix"; then
     echo $ac_n "checking for file""... $ac_c" 1>&6
-echo "configure:1883: checking for file" >&5
+echo "configure:1873: checking for file" >&5
 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1950,7 +1940,7 @@ esac
 # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1954: checking for $ac_word" >&5
+echo "configure:1944: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1982,7 +1972,7 @@ if test -n "$ac_tool_prefix"; then
   # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1986: checking for $ac_word" >&5
+echo "configure:1976: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2017,7 +2007,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
 set dummy ${ac_tool_prefix}strip; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2021: checking for $ac_word" >&5
+echo "configure:2011: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2049,7 +2039,7 @@ if test -n "$ac_tool_prefix"; then
   # Extract the first word of "strip", so it can be a program name with args.
 set dummy strip; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2053: checking for $ac_word" >&5
+echo "configure:2043: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2116,8 +2106,8 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
 case $host in
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 2120 "configure"' > conftest.$ac_ext
-  if { (eval echo configure:2121: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  echo '#line 2110 "configure"' > conftest.$ac_ext
+  if { (eval echo configure:2111: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
    if test "$lt_cv_prog_gnu_ld" = yes; then
     case `/usr/bin/file conftest.$ac_objext` in
     *32-bit*)
@@ -2150,7 +2140,7 @@ case $host in
 ia64-*-hpux*)
   # Find out which ABI we are using.
   echo 'int i;' > conftest.$ac_ext
-  if { (eval echo configure:2154: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  if { (eval echo configure:2144: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
     case "`/usr/bin/file conftest.o`" in
     *ELF-32*)
       HPUX_IA64_MODE="32"
@@ -2168,7 +2158,7 @@ ia64-*-hpux*)
   SAVE_CFLAGS="$CFLAGS"
   CFLAGS="$CFLAGS -belf"
   echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6
-echo "configure:2172: checking whether the C compiler needs -belf" >&5
+echo "configure:2162: checking whether the C compiler needs -belf" >&5
 if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2181,14 +2171,14 @@ ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$a
 cross_compiling=$ac_cv_prog_cc_cross
 
      cat > conftest.$ac_ext <<EOF
-#line 2185 "configure"
+#line 2175 "configure"
 #include "confdefs.h"
 
 int main() {
 
 ; return 0; }
 EOF
-if { (eval echo configure:2192: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2182: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   lt_cv_cc_needs_belf=yes
 else
@@ -2356,7 +2346,7 @@ if test -z "$target" ; then
 fi
 
 echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6
-echo "configure:2360: checking whether to enable maintainer-specific portions of Makefiles" >&5
+echo "configure:2350: checking whether to enable maintainer-specific portions of Makefiles" >&5
     # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
 if test "${enable_maintainer_mode+set}" = set; then
   enableval="$enable_maintainer_mode"
@@ -2379,7 +2369,7 @@ fi
   
 
 echo $ac_n "checking whether to install libbfd""... $ac_c" 1>&6
-echo "configure:2383: checking whether to install libbfd" >&5
+echo "configure:2373: checking whether to install libbfd" >&5
   # Check whether --enable-install-libbfd or --disable-install-libbfd was given.
 if test "${enable_install_libbfd+set}" = set; then
   enableval="$enable_install_libbfd"
@@ -2416,7 +2406,7 @@ fi
 
 
 echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:2420: checking for executable suffix" >&5
+echo "configure:2410: checking for executable suffix" >&5
 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2426,10 +2416,10 @@ else
   rm -f conftest*
   echo 'int main () { return 0; }' > conftest.$ac_ext
   ac_cv_exeext=
-  if { (eval echo configure:2430: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+  if { (eval echo configure:2420: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
     for file in conftest.*; do
       case $file in
-      *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+      *.c | *.o | *.obj) ;;
       *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
       esac
     done
@@ -2452,7 +2442,7 @@ ac_exeext=$EXEEXT
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2456: checking for $ac_word" >&5
+echo "configure:2446: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2482,7 +2472,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2486: checking for $ac_word" >&5
+echo "configure:2476: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2533,7 +2523,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2537: checking for $ac_word" >&5
+echo "configure:2527: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2565,7 +2555,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:2569: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:2559: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -2576,12 +2566,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 2580 "configure"
+#line 2570 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:2585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2575: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -2607,12 +2597,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:2611: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:2601: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:2616: checking whether we are using GNU C" >&5
+echo "configure:2606: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2621,7 +2611,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2625: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2615: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -2640,7 +2630,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:2644: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:2634: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2674,7 +2664,7 @@ fi
 
 ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl"
 echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
-echo "configure:2678: checking how to run the C preprocessor" >&5
+echo "configure:2668: checking how to run the C preprocessor" >&5
 # On Suns, sometimes $CPP names a directory.
 if test -n "$CPP" && test -d "$CPP"; then
   CPP=
@@ -2689,13 +2679,13 @@ else
   # On the NeXT, cc -E runs the code through the compiler's parser,
   # not just through cpp.
   cat > conftest.$ac_ext <<EOF
-#line 2693 "configure"
+#line 2683 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2699: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2689: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2706,13 +2696,13 @@ else
   rm -rf conftest*
   CPP="${CC-cc} -E -traditional-cpp"
   cat > conftest.$ac_ext <<EOF
-#line 2710 "configure"
+#line 2700 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2706: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2723,13 +2713,13 @@ else
   rm -rf conftest*
   CPP="${CC-cc} -nologo -E"
   cat > conftest.$ac_ext <<EOF
-#line 2727 "configure"
+#line 2717 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2723: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2756,7 +2746,7 @@ echo "$ac_t""$CPP" 1>&6
 # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2760: checking for $ac_word" >&5
+echo "configure:2750: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2784,12 +2774,12 @@ else
 fi
 
 echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
-echo "configure:2788: checking for ANSI C header files" >&5
+echo "configure:2778: checking for ANSI C header files" >&5
 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2793 "configure"
+#line 2783 "configure"
 #include "confdefs.h"
 #include <stdlib.h>
 #include <stdarg.h>
@@ -2797,7 +2787,7 @@ else
 #include <float.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2801: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2791: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -2814,7 +2804,7 @@ rm -f conftest*
 if test $ac_cv_header_stdc = yes; then
   # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
 cat > conftest.$ac_ext <<EOF
-#line 2818 "configure"
+#line 2808 "configure"
 #include "confdefs.h"
 #include <string.h>
 EOF
@@ -2832,7 +2822,7 @@ fi
 if test $ac_cv_header_stdc = yes; then
   # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
 cat > conftest.$ac_ext <<EOF
-#line 2836 "configure"
+#line 2826 "configure"
 #include "confdefs.h"
 #include <stdlib.h>
 EOF
@@ -2853,7 +2843,7 @@ if test "$cross_compiling" = yes; then
   :
 else
   cat > conftest.$ac_ext <<EOF
-#line 2857 "configure"
+#line 2847 "configure"
 #include "confdefs.h"
 #include <ctype.h>
 #define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
@@ -2864,7 +2854,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
 exit (0); }
 
 EOF
-if { (eval echo configure:2868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:2858: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   :
 else
@@ -2888,12 +2878,12 @@ EOF
 fi
 
 echo $ac_n "checking for working const""... $ac_c" 1>&6
-echo "configure:2892: checking for working const" >&5
+echo "configure:2882: checking for working const" >&5
 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2897 "configure"
+#line 2887 "configure"
 #include "confdefs.h"
 
 int main() {
@@ -2942,7 +2932,7 @@ ccp = (char const *const *) p;
 
 ; return 0; }
 EOF
-if { (eval echo configure:2946: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2936: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_c_const=yes
 else
@@ -2963,21 +2953,21 @@ EOF
 fi
 
 echo $ac_n "checking for inline""... $ac_c" 1>&6
-echo "configure:2967: checking for inline" >&5
+echo "configure:2957: checking for inline" >&5
 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   ac_cv_c_inline=no
 for ac_kw in inline __inline__ __inline; do
   cat > conftest.$ac_ext <<EOF
-#line 2974 "configure"
+#line 2964 "configure"
 #include "confdefs.h"
 
 int main() {
 } $ac_kw foo() {
 ; return 0; }
 EOF
-if { (eval echo configure:2981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2971: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_c_inline=$ac_kw; break
 else
@@ -3003,12 +2993,12 @@ EOF
 esac
 
 echo $ac_n "checking for off_t""... $ac_c" 1>&6
-echo "configure:3007: checking for off_t" >&5
+echo "configure:2997: checking for off_t" >&5
 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3012 "configure"
+#line 3002 "configure"
 #include "confdefs.h"
 #include <sys/types.h>
 #if STDC_HEADERS
@@ -3036,12 +3026,12 @@ EOF
 fi
 
 echo $ac_n "checking for size_t""... $ac_c" 1>&6
-echo "configure:3040: checking for size_t" >&5
+echo "configure:3030: checking for size_t" >&5
 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3045 "configure"
+#line 3035 "configure"
 #include "confdefs.h"
 #include <sys/types.h>
 #if STDC_HEADERS
@@ -3071,19 +3061,19 @@ fi
 # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
 # for constant arguments.  Useless!
 echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
-echo "configure:3075: checking for working alloca.h" >&5
+echo "configure:3065: checking for working alloca.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3080 "configure"
+#line 3070 "configure"
 #include "confdefs.h"
 #include <alloca.h>
 int main() {
 char *p = alloca(2 * sizeof(int));
 ; return 0; }
 EOF
-if { (eval echo configure:3087: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3077: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   ac_cv_header_alloca_h=yes
 else
@@ -3104,12 +3094,12 @@ EOF
 fi
 
 echo $ac_n "checking for alloca""... $ac_c" 1>&6
-echo "configure:3108: checking for alloca" >&5
+echo "configure:3098: checking for alloca" >&5
 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3113 "configure"
+#line 3103 "configure"
 #include "confdefs.h"
 
 #ifdef __GNUC__
@@ -3137,7 +3127,7 @@ int main() {
 char *p = (char *) alloca(1);
 ; return 0; }
 EOF
-if { (eval echo configure:3141: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3131: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   ac_cv_func_alloca_works=yes
 else
@@ -3169,12 +3159,12 @@ EOF
 
 
 echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:3173: checking whether alloca needs Cray hooks" >&5
+echo "configure:3163: checking whether alloca needs Cray hooks" >&5
 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3178 "configure"
+#line 3168 "configure"
 #include "confdefs.h"
 #if defined(CRAY) && ! defined(CRAY2)
 webecray
@@ -3199,12 +3189,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6
 if test $ac_cv_os_cray = yes; then
 for ac_func in _getb67 GETB67 getb67; do
   echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3203: checking for $ac_func" >&5
+echo "configure:3193: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3208 "configure"
+#line 3198 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3227,7 +3217,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3231: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3221: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3254,7 +3244,7 @@ done
 fi
 
 echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:3258: checking stack direction for C alloca" >&5
+echo "configure:3248: checking stack direction for C alloca" >&5
 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3262,7 +3252,7 @@ else
   ac_cv_c_stack_direction=0
 else
   cat > conftest.$ac_ext <<EOF
-#line 3266 "configure"
+#line 3256 "configure"
 #include "confdefs.h"
 find_stack_direction ()
 {
@@ -3281,7 +3271,7 @@ main ()
   exit (find_stack_direction() < 0);
 }
 EOF
-if { (eval echo configure:3285: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3275: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   ac_cv_c_stack_direction=1
 else
@@ -3302,21 +3292,21 @@ EOF
 
 fi
 
-for ac_hdr in unistd.h
+for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3310: checking for $ac_hdr" >&5
+echo "configure:3300: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3315 "configure"
+#line 3305 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3320: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3310: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3345,12 +3335,12 @@ done
 for ac_func in getpagesize
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3349: checking for $ac_func" >&5
+echo "configure:3339: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3354 "configure"
+#line 3344 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3373,7 +3363,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3377: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3367: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3398,7 +3388,7 @@ fi
 done
 
 echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:3402: checking for working mmap" >&5
+echo "configure:3392: checking for working mmap" >&5
 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3406,7 +3396,7 @@ else
   ac_cv_func_mmap_fixed_mapped=no
 else
   cat > conftest.$ac_ext <<EOF
-#line 3410 "configure"
+#line 3400 "configure"
 #include "confdefs.h"
 
 /* Thanks to Mike Haertel and Jim Avera for this test.
@@ -3434,11 +3424,24 @@ else
 #include <fcntl.h>
 #include <sys/mman.h>
 
+#if HAVE_SYS_TYPES_H
+# include <sys/types.h>
+#endif
+
+#if HAVE_STDLIB_H
+# include <stdlib.h>
+#endif
+
+#if HAVE_SYS_STAT_H
+# include <sys/stat.h>
+#endif
+
+#if HAVE_UNISTD_H
+# include <unistd.h>
+#endif
+
 /* This mess was copied from the GNU getpagesize.h.  */
 #ifndef HAVE_GETPAGESIZE
-# ifdef HAVE_UNISTD_H
-#  include <unistd.h>
-# endif
 
 /* Assume that all systems that can run configure have sys/param.h.  */
 # ifndef HAVE_SYS_PARAM_H
@@ -3546,7 +3549,7 @@ main()
 }
 
 EOF
-if { (eval echo configure:3550: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3553: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   ac_cv_func_mmap_fixed_mapped=yes
 else
@@ -3574,17 +3577,17 @@ unistd.h values.h sys/param.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3578: checking for $ac_hdr" >&5
+echo "configure:3581: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3583 "configure"
+#line 3586 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3588: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3591: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3614,12 +3617,12 @@ done
 __argz_count __argz_stringify __argz_next
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3618: checking for $ac_func" >&5
+echo "configure:3621: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3623 "configure"
+#line 3626 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3642,7 +3645,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3646: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3649: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3671,12 +3674,12 @@ done
      for ac_func in stpcpy
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3675: checking for $ac_func" >&5
+echo "configure:3678: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3680 "configure"
+#line 3683 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3699,7 +3702,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3703: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3706: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3733,19 +3736,19 @@ EOF
 
    if test $ac_cv_header_locale_h = yes; then
     echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
-echo "configure:3737: checking for LC_MESSAGES" >&5
+echo "configure:3740: checking for LC_MESSAGES" >&5
 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3742 "configure"
+#line 3745 "configure"
 #include "confdefs.h"
 #include <locale.h>
 int main() {
 return LC_MESSAGES
 ; return 0; }
 EOF
-if { (eval echo configure:3749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3752: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   am_cv_val_LC_MESSAGES=yes
 else
@@ -3766,7 +3769,7 @@ EOF
     fi
   fi
    echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
-echo "configure:3770: checking whether NLS is requested" >&5
+echo "configure:3773: checking whether NLS is requested" >&5
         # Check whether --enable-nls or --disable-nls was given.
 if test "${enable_nls+set}" = set; then
   enableval="$enable_nls"
@@ -3786,7 +3789,7 @@ fi
 EOF
 
       echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
-echo "configure:3790: checking whether included gettext is requested" >&5
+echo "configure:3793: checking whether included gettext is requested" >&5
       # Check whether --with-included-gettext or --without-included-gettext was given.
 if test "${with_included_gettext+set}" = set; then
   withval="$with_included_gettext"
@@ -3805,17 +3808,17 @@ fi
 
 	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
-echo "configure:3809: checking for libintl.h" >&5
+echo "configure:3812: checking for libintl.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3814 "configure"
+#line 3817 "configure"
 #include "confdefs.h"
 #include <libintl.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3819: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3822: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3832,19 +3835,19 @@ fi
 if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
   echo "$ac_t""yes" 1>&6
   echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
-echo "configure:3836: checking for gettext in libc" >&5
+echo "configure:3839: checking for gettext in libc" >&5
 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3841 "configure"
+#line 3844 "configure"
 #include "confdefs.h"
 #include <libintl.h>
 int main() {
 return (int) gettext ("")
 ; return 0; }
 EOF
-if { (eval echo configure:3848: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3851: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   gt_cv_func_gettext_libc=yes
 else
@@ -3860,7 +3863,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
 
 	   if test "$gt_cv_func_gettext_libc" != "yes"; then
 	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
-echo "configure:3864: checking for bindtextdomain in -lintl" >&5
+echo "configure:3867: checking for bindtextdomain in -lintl" >&5
 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -3868,7 +3871,7 @@ else
   ac_save_LIBS="$LIBS"
 LIBS="-lintl  $LIBS"
 cat > conftest.$ac_ext <<EOF
-#line 3872 "configure"
+#line 3875 "configure"
 #include "confdefs.h"
 /* Override any gcc2 internal prototype to avoid an error.  */
 /* We use char because int might match the return type of a gcc2
@@ -3879,7 +3882,7 @@ int main() {
 bindtextdomain()
 ; return 0; }
 EOF
-if { (eval echo configure:3883: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3886: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_lib_$ac_lib_var=yes"
 else
@@ -3895,19 +3898,19 @@ fi
 if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
   echo "$ac_t""yes" 1>&6
   echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
-echo "configure:3899: checking for gettext in libintl" >&5
+echo "configure:3902: checking for gettext in libintl" >&5
 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3904 "configure"
+#line 3907 "configure"
 #include "confdefs.h"
 
 int main() {
 return (int) gettext ("")
 ; return 0; }
 EOF
-if { (eval echo configure:3911: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3914: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   gt_cv_func_gettext_libintl=yes
 else
@@ -3935,7 +3938,7 @@ EOF
 	      # Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3939: checking for $ac_word" >&5
+echo "configure:3942: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3969,12 +3972,12 @@ fi
 		for ac_func in dcgettext
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3973: checking for $ac_func" >&5
+echo "configure:3976: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3978 "configure"
+#line 3981 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3997,7 +4000,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:4001: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4004: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -4024,7 +4027,7 @@ done
 		# Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4028: checking for $ac_word" >&5
+echo "configure:4031: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4060,7 +4063,7 @@ fi
 		# Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4064: checking for $ac_word" >&5
+echo "configure:4067: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4092,7 +4095,7 @@ else
 fi
 
 		cat > conftest.$ac_ext <<EOF
-#line 4096 "configure"
+#line 4099 "configure"
 #include "confdefs.h"
 
 int main() {
@@ -4100,7 +4103,7 @@ extern int _nl_msg_cat_cntr;
 			       return _nl_msg_cat_cntr
 ; return 0; }
 EOF
-if { (eval echo configure:4104: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4107: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   CATOBJEXT=.gmo
 		   DATADIRNAME=share
@@ -4132,7 +4135,7 @@ fi
         # Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4136: checking for $ac_word" >&5
+echo "configure:4139: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4166,7 +4169,7 @@ fi
         # Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4170: checking for $ac_word" >&5
+echo "configure:4173: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4202,7 +4205,7 @@ fi
         # Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4206: checking for $ac_word" >&5
+echo "configure:4209: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4292,7 +4295,7 @@ fi
        LINGUAS=
      else
        echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
-echo "configure:4296: checking for catalogs to be installed" >&5
+echo "configure:4299: checking for catalogs to be installed" >&5
        NEW_LINGUAS=
        for lang in ${LINGUAS=$ALL_LINGUAS}; do
          case "$ALL_LINGUAS" in
@@ -4320,17 +4323,17 @@ echo "configure:4296: checking for catalogs to be installed" >&5
       if test "$CATOBJEXT" = ".cat"; then
 	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
-echo "configure:4324: checking for linux/version.h" >&5
+echo "configure:4327: checking for linux/version.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 4329 "configure"
+#line 4332 "configure"
 #include "confdefs.h"
 #include <linux/version.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4334: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4337: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -4408,7 +4411,7 @@ if test "x$cross_compiling" = "xno"; then
   EXEEXT_FOR_BUILD='$(EXEEXT)'
 else
   echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6
-echo "configure:4412: checking for build system executable suffix" >&5
+echo "configure:4415: checking for build system executable suffix" >&5
 if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -4445,7 +4448,7 @@ fi
 # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
 # ./install, which can be erroneously created by make from ./install.sh.
 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:4449: checking for a BSD compatible install" >&5
+echo "configure:4452: checking for a BSD compatible install" >&5
 if test -z "$INSTALL"; then
 if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -4502,17 +4505,17 @@ for ac_hdr in string.h strings.h stdlib.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:4506: checking for $ac_hdr" >&5
+echo "configure:4509: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 4511 "configure"
+#line 4514 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4516: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4519: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c
index 145b56a..98df36b 100644
--- a/opcodes/frv-asm.c
+++ b/opcodes/frv-asm.c
@@ -860,6 +860,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
     case FRV_OPERAND_LI :
       errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI);
       break;
+    case FRV_OPERAND_LRAD :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAD, &fields->f_LRAD);
+      break;
+    case FRV_OPERAND_LRAE :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAE, &fields->f_LRAE);
+      break;
+    case FRV_OPERAND_LRAS :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAS, &fields->f_LRAS);
+      break;
+    case FRV_OPERAND_TLBPRL :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPRL, &fields->f_TLBPRL);
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPROPX, &fields->f_TLBPRopx);
+      break;
     case FRV_OPERAND_AE :
       errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae);
       break;
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index 35659c7..7e0b3b4 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -49,6 +49,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
   { "frv", MACH_FRV },
   { "fr550", MACH_FR550 },
   { "fr500", MACH_FR500 },
+  { "fr450", MACH_FR450 },
   { "fr400", MACH_FR400 },
   { "tomcat", MACH_TOMCAT },
   { "simple", MACH_SIMPLE },
@@ -90,6 +91,7 @@ static const CGEN_ATTR_ENTRY UNIT_attr[] =
   { "SCAN", UNIT_SCAN },
   { "DCPL", UNIT_DCPL },
   { "MDUALACC", UNIT_MDUALACC },
+  { "MDCUTSSI", UNIT_MDCUTSSI },
   { "MCLRACC_1", UNIT_MCLRACC_1 },
   { "NUM_UNITS", UNIT_NUM_UNITS },
   { 0, 0 }
@@ -116,6 +118,31 @@ static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
   { 0, 0 }
 };
 
+static const CGEN_ATTR_ENTRY FR450_MAJOR_attr[] =
+{
+  { "NONE", FR450_MAJOR_NONE },
+  { "I_1", FR450_MAJOR_I_1 },
+  { "I_2", FR450_MAJOR_I_2 },
+  { "I_3", FR450_MAJOR_I_3 },
+  { "I_4", FR450_MAJOR_I_4 },
+  { "I_5", FR450_MAJOR_I_5 },
+  { "B_1", FR450_MAJOR_B_1 },
+  { "B_2", FR450_MAJOR_B_2 },
+  { "B_3", FR450_MAJOR_B_3 },
+  { "B_4", FR450_MAJOR_B_4 },
+  { "B_5", FR450_MAJOR_B_5 },
+  { "B_6", FR450_MAJOR_B_6 },
+  { "C_1", FR450_MAJOR_C_1 },
+  { "C_2", FR450_MAJOR_C_2 },
+  { "M_1", FR450_MAJOR_M_1 },
+  { "M_2", FR450_MAJOR_M_2 },
+  { "M_3", FR450_MAJOR_M_3 },
+  { "M_4", FR450_MAJOR_M_4 },
+  { "M_5", FR450_MAJOR_M_5 },
+  { "M_6", FR450_MAJOR_M_6 },
+  { 0, 0 }
+};
+
 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
 {
   { "NONE", FR500_MAJOR_NONE },
@@ -225,6 +252,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
   { "MACH", & MACH_attr[0], & MACH_attr[0] },
   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
+  { "FR450-MAJOR", & FR450_MAJOR_attr[0], & FR450_MAJOR_attr[0] },
   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
   { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] },
   { "ALIAS", &bool_attr[0], &bool_attr[0] },
@@ -242,6 +270,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
   { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
   { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
   { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
+  { "AUDIO", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
 };
 
@@ -260,6 +289,7 @@ static const CGEN_MACH frv_cgen_mach_table[] = {
   { "fr500", "fr500", MACH_FR500, 0 },
   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
   { "fr400", "fr400", MACH_FR400, 0 },
+  { "fr450", "fr450", MACH_FR450, 0 },
   { "simple", "simple", MACH_SIMPLE, 0 },
   { 0, 0, 0, 0 }
 };
@@ -804,6 +834,10 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
   { "sr1", 769, {0, {0}}, 0, 0 },
   { "sr2", 770, {0, {0}}, 0, 0 },
   { "sr3", 771, {0, {0}}, 0, 0 },
+  { "scr0", 832, {0, {0}}, 0, 0 },
+  { "scr1", 833, {0, {0}}, 0, 0 },
+  { "scr2", 834, {0, {0}}, 0, 0 },
+  { "scr3", 835, {0, {0}}, 0, 0 },
   { "fsr0", 1024, {0, {0}}, 0, 0 },
   { "fsr1", 1025, {0, {0}}, 0, 0 },
   { "fsr2", 1026, {0, {0}}, 0, 0 },
@@ -1449,9 +1483,20 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
   { "amcr", 1920, {0, {0}}, 0, 0 },
   { "stbar", 1921, {0, {0}}, 0, 0 },
   { "mmcr", 1922, {0, {0}}, 0, 0 },
+  { "iamvr1", 1925, {0, {0}}, 0, 0 },
+  { "damvr1", 1927, {0, {0}}, 0, 0 },
+  { "cxnr", 1936, {0, {0}}, 0, 0 },
+  { "ttbr", 1937, {0, {0}}, 0, 0 },
+  { "tplr", 1938, {0, {0}}, 0, 0 },
+  { "tppr", 1939, {0, {0}}, 0, 0 },
+  { "tpxr", 1940, {0, {0}}, 0, 0 },
+  { "timerh", 1952, {0, {0}}, 0, 0 },
+  { "timerl", 1953, {0, {0}}, 0, 0 },
+  { "timerd", 1954, {0, {0}}, 0, 0 },
   { "dcr", 2048, {0, {0}}, 0, 0 },
   { "brr", 2049, {0, {0}}, 0, 0 },
   { "nmar", 2050, {0, {0}}, 0, 0 },
+  { "btbr", 2051, {0, {0}}, 0, 0 },
   { "ibar0", 2052, {0, {0}}, 0, 0 },
   { "ibar1", 2053, {0, {0}}, 0, 0 },
   { "ibar2", 2054, {0, {0}}, 0, 0 },
@@ -1505,7 +1550,7 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 CGEN_KEYWORD frv_cgen_opval_spr_names =
 {
   & frv_cgen_opval_spr_names_entries[0],
-  1007,
+  1022,
   0, 0, 0, 0, ""
 };
 
@@ -1817,7 +1862,7 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] =
   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400) } } },
+  { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400)|(1<<MACH_FR450) } } },
   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
@@ -1906,6 +1951,11 @@ const CGEN_IFLD frv_cgen_ifld_table[] =
   { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
   { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
   { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+  { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
   { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
@@ -1935,6 +1985,8 @@ const CGEN_IFLD frv_cgen_ifld_table[] =
   { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
   { 0, 0, 0, 0, 0, 0, {0, {0}} }
@@ -2231,6 +2283,26 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, 
     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+/* LRAE: Load Real Address E flag */
+  { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* LRAD: Load Real Address D flag */
+  { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* LRAS: Load Real Address S flag */
+  { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* TLBPRopx: TLB Probe operation number */
+  { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* TLBPRL: TLB Probe L flag */
+  { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
 /* A0: A==0 operand of mclracc */
   { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
@@ -2338,3732 +2410,3717 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* add$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_ADD, "add", "add", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sub$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SUB, "sub", "sub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* and$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_AND, "and", "and", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* or$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_OR, "or", "or", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xor$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_XOR, "xor", "xor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* not$pack $GRj,$GRk */
   {
     FRV_INSN_NOT, "not", "not", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nsdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* udiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_UDIV, "udiv", "udiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nudiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* smul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_SMUL, "smul", "smul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_UMUL, "umul", "umul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* smu$pack $GRi,$GRj */
   {
     FRV_INSN_SMU, "smu", "smu", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* smass$pack $GRi,$GRj */
   {
     FRV_INSN_SMASS, "smass", "smass", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* smsss$pack $GRi,$GRj */
   {
     FRV_INSN_SMSSS, "smsss", "smsss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* sll$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SLL, "sll", "sll", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srl$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRL, "srl", "srl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sra$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRA, "sra", "sra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* slass$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SLASS, "slass", "slass", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* scutss$pack $GRj,$GRk */
   {
     FRV_INSN_SCUTSS, "scutss", "scutss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_I0, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* scan$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SCAN, "scan", "scan", 32,
-    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADD, "cadd", "cadd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUB, "csub", "csub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CAND, "cand", "cand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_COR, "cor", "cor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXOR, "cxor", "cxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cnot$pack $GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CNOT, "cnot", "cnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMUL, "csmul", "csmul", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLL, "csll", "csll", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRL, "csrl", "csrl", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRA, "csra", "csra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSCAN, "cscan", "cscan", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDCC, "addcc", "addcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBCC, "subcc", "subcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDCC, "andcc", "andcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORCC, "orcc", "orcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRACC, "sracc", "sracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CANDCC, "candcc", "candcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CORCC, "corcc", "corcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRACC, "csracc", "csracc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDX, "addx", "addx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBX, "subx", "subx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addss$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_ADDSS, "addss", "addss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* subss$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SUBSS, "subss", "subss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* addi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ADDI, "addi", "addi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SUBI, "subi", "subi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ANDI, "andi", "andi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* ori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ORI, "ori", "ori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_XORI, "xori", "xori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nsdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* udivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_UDIVI, "udivi", "udivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nudivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* smuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_SMULI, "smuli", "smuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_UMULI, "umuli", "umuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* slli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SLLI, "slli", "slli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRLI, "srli", "srli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srai$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRAI, "srai", "srai", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* scani$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SCANI, "scani", "scani", 32,
-    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDICC, "addicc", "addicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBICC, "subicc", "subicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDICC, "andicc", "andicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORICC, "oricc", "oricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXI, "addxi", "addxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXI, "subxi", "subxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
   },
 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
   },
 /* setlo$pack $ulo16,$GRklo */
   {
     FRV_INSN_SETLO, "setlo", "setlo", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sethi$pack $uhi16,$GRkhi */
   {
     FRV_INSN_SETHI, "sethi", "sethi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* setlos$pack $slo16,$GRk */
   {
     FRV_INSN_SETLOS, "setlos", "setlos", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* ldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUB, "ldub", "ldub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUH, "lduh", "lduh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ld$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LD, "ld", "ld", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDF, "ldf", "ldf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDC, "ldc", "ldc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUB, "nldub", "nldub", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nld$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLD, "nld", "nld", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDF, "nldf", "nldf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldd$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDD, "ldd", "ldd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDF, "lddf", "lddf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDC, "lddc", "lddc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldd$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDD, "nldd", "nldd", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQ, "ldq", "ldq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQ, "nldq", "nldq", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDU, "ldu", "ldu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDU, "nldu", "nldu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDDU, "lddu", "lddu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDI, "ldi", "ldi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDI, "nldi", "nldi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_LDDI, "lddi", "lddi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldqi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* stb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STB, "stb", "stb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sth$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STH, "sth", "sth", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* st$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_ST, "st", "st", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBF, "stbf", "stbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHF, "sthf", "sthf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STF, "stf", "stf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STC, "stc", "stc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
-  },
-/* rstb$pack $GRk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTB, "rstb", "rstb", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rsth$pack $GRk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTH, "rsth", "rsth", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rst$pack $GRk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RST, "rst", "rst", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rstbf$pack $FRintk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rsthf$pack $FRintk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rstf$pack $FRintk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTF, "rstf", "rstf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* std$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STD, "std", "std", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDF, "stdf", "stdf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdc$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDC, "stdc", "stdc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
-  },
-/* rstd$pack $GRdoublek,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTD, "rstd", "rstd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stq$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQ, "stq", "stq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQF, "stqf", "stqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQC, "stqc", "stqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rstq$pack $GRk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTQ, "rstq", "rstq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
-  },
-/* rstqf$pack $FRintk,@($GRi,$GRj) */
-  {
-    FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stbu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STBU, "stbu", "stbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STHU, "sthu", "sthu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STU, "stu", "stu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STFU, "stfu", "stfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STCU, "stcu", "stcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdu$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDU, "stdu", "stdu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdfu$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stqu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQU, "stqu", "stqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUB, "cldub", "cldub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUH, "clduh", "clduh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLD, "cld", "cld", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDF, "cldf", "cldf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDD, "cldd", "cldd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDF, "clddf", "clddf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQ, "cldq", "cldq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDU, "cldu", "cldu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDU, "clddu", "clddu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTB, "cstb", "cstb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTH, "csth", "csth", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CST, "cst", "cst", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHF, "csthf", "csthf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTF, "cstf", "cstf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTD, "cstd", "cstd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTQ, "cstq", "cstq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHU, "csthu", "csthu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTU, "cstu", "cstu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STBI, "stbi", "stbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STHI, "sthi", "sthi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sti$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STI, "sti", "sti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STFI, "stfi", "stfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdi$pack $GRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDI, "stdi", "stdi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stdfi$pack $FRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stqi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STQI, "stqi", "stqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* swap$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_SWAP, "swap", "swap", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* swapi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_SWAPI, "swapi", "swapi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CSWAP, "cswap", "cswap", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* movgf$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGF, "movgf", "movgf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movfg$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFG, "movfg", "movfg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgfd$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movfgd$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgfq$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
   },
 /* movfgq$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
   },
 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgs$pack $GRj,$spr */
   {
     FRV_INSN_MOVGS, "movgs", "movgs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* movsg$pack $spr,$GRj */
   {
     FRV_INSN_MOVSG, "movsg", "movsg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* bra$pack $hint_taken$label16 */
   {
     FRV_INSN_BRA, "bra", "bra", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bno$pack$hint_not_taken */
   {
     FRV_INSN_BNO, "bno", "bno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* beq$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bne$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* ble$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLE, "ble", "ble", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bgt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGT, "bgt", "bgt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* blt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLT, "blt", "blt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bge$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGE, "bge", "bge", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bls$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLS, "bls", "bls", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bhi$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BHI, "bhi", "bhi", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BC, "bc", "bc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bnc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNC, "bnc", "bnc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bn$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BN, "bn", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bp$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BP, "bp", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BV, "bv", "bv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bnv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNV, "bnv", "bnv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbra$pack $hint_taken$label16 */
   {
     FRV_INSN_FBRA, "fbra", "fbra", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbno$pack$hint_not_taken */
   {
     FRV_INSN_FBNO, "fbno", "fbno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbne$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBNE, "fbne", "fbne", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbeq$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fblg$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLG, "fblg", "fblg", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbue$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUE, "fbue", "fbue", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbul$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUL, "fbul", "fbul", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGE, "fbge", "fbge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fblt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLT, "fblt", "fblt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbuge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbug$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUG, "fbug", "fbug", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fble$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLE, "fble", "fble", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbgt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbule$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBULE, "fbule", "fbule", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbu$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBU, "fbu", "fbu", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbo$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBO, "fbo", "fbo", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bctrlr$pack $ccond,$hint */
   {
     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bralr$pack$hint_taken */
   {
     FRV_INSN_BRALR, "bralr", "bralr", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnolr$pack$hint_not_taken */
   {
     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* beqlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* blelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLELR, "blelr", "blelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bgtlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bltlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bgelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* blslr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLSLR, "blslr", "blslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bhilr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BCLR, "bclr", "bclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bplr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BPLR, "bplr", "bplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbralr$pack$hint_taken */
   {
     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbeqlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbnelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fblglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbuelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbullr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbgelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbltlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbugelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbuglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fblelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbgtlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbulelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbulr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbolr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bcralr$pack $ccond$hint_taken */
   {
     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnolr$pack$hint_not_taken */
   {
     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bceqlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bclelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcltlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcgelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bclslr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bchilr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcplr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbralr$pack $ccond$hint_taken */
   {
     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcblglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbullr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcblelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbulr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbolr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* jmpl$pack @($GRi,$GRj) */
   {
     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* calll$pack @($GRi,$GRj) */
   {
     FRV_INSN_CALLL, "calll", "calll", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* jmpil$pack @($GRi,$s12) */
   {
     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* callil$pack @($GRi,$s12) */
   {
     FRV_INSN_CALLIL, "callil", "callil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* call$pack $label24 */
   {
     FRV_INSN_CALL, "call", "call", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR450_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
   },
 /* rett$pack $debug */
   {
     FRV_INSN_RETT, "rett", "rett", 32,
-    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* rei$pack $eir */
   {
     FRV_INSN_REI, "rei", "rei", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
   },
 /* tra$pack $GRi,$GRj */
   {
     FRV_INSN_TRA, "tra", "tra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tno$pack */
   {
     FRV_INSN_TNO, "tno", "tno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* teq$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TEQ, "teq", "teq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tne$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNE, "tne", "tne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tle$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLE, "tle", "tle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tgt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGT, "tgt", "tgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tlt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLT, "tlt", "tlt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tge$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGE, "tge", "tge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tls$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLS, "tls", "tls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* thi$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_THI, "thi", "thi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TC, "tc", "tc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tnc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNC, "tnc", "tnc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tn$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TN, "tn", "tn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tp$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TP, "tp", "tp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TV, "tv", "tv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tnv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNV, "tnv", "tnv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftra$pack $GRi,$GRj */
   {
     FRV_INSN_FTRA, "ftra", "ftra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftno$pack */
   {
     FRV_INSN_FTNO, "ftno", "ftno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftne$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTNE, "ftne", "ftne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* fteq$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTEQ, "fteq", "fteq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftlg$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftue$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUE, "ftue", "ftue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftul$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUL, "ftul", "ftul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGE, "ftge", "ftge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftlt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftuge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftug$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUG, "ftug", "ftug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftle$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLE, "ftle", "ftle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftgt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftule$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTULE, "ftule", "ftule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftu$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTU, "ftu", "ftu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* fto$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTO, "fto", "fto", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tira$pack $GRi,$s12 */
   {
     FRV_INSN_TIRA, "tira", "tira", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tino$pack */
   {
     FRV_INSN_TINO, "tino", "tino", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tieq$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIEQ, "tieq", "tieq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tine$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINE, "tine", "tine", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tile$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILE, "tile", "tile", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tigt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGT, "tigt", "tigt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tilt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILT, "tilt", "tilt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tige$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGE, "tige", "tige", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tils$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILS, "tils", "tils", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tihi$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIHI, "tihi", "tihi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tic$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIC, "tic", "tic", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tinc$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINC, "tinc", "tinc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tin$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIN, "tin", "tin", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tip$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIP, "tip", "tip", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tiv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIV, "tiv", "tiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tinv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINV, "tinv", "tinv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftira$pack $GRi,$s12 */
   {
     FRV_INSN_FTIRA, "ftira", "ftira", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftino$pack */
   {
     FRV_INSN_FTINO, "ftino", "ftino", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftine$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTINE, "ftine", "ftine", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftieq$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftilg$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiue$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiul$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftige$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGE, "ftige", "ftige", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftilt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiug$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftile$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILE, "ftile", "ftile", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftigt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiule$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiu$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftio$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIO, "ftio", "ftio", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* break$pack */
   {
     FRV_INSN_BREAK, "break", "break", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* mtrap$pack */
   {
     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* andcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDCR, "andcr", "andcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* orcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORCR, "orcr", "orcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* xorcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* nandcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* norcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORCR, "norcr", "norcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* andncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* orncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORNCR, "orncr", "orncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* nandncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* norncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORNCR, "norncr", "norncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* notcr$pack $CRj,$CRk */
   {
     FRV_INSN_NOTCR, "notcr", "notcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* ckra$pack $CRj_int */
   {
     FRV_INSN_CKRA, "ckra", "ckra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckno$pack $CRj_int */
   {
     FRV_INSN_CKNO, "ckno", "ckno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckeq$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckne$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNE, "ckne", "ckne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckle$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLE, "ckle", "ckle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckgt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cklt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLT, "cklt", "cklt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckge$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGE, "ckge", "ckge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckls$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLS, "ckls", "ckls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckhi$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKC, "ckc", "ckc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cknc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNC, "cknc", "cknc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckn$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKN, "ckn", "ckn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckp$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKP, "ckp", "ckp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKV, "ckv", "ckv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cknv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNV, "cknv", "cknv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckra$pack $CRj_float */
   {
     FRV_INSN_FCKRA, "fckra", "fckra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckno$pack $CRj_float */
   {
     FRV_INSN_FCKNO, "fckno", "fckno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckne$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKNE, "fckne", "fckne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckeq$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcklg$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckue$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUE, "fckue", "fckue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckul$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUL, "fckul", "fckul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGE, "fckge", "fckge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcklt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckuge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckug$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUG, "fckug", "fckug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckle$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLE, "fckle", "fckle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckgt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckule$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKULE, "fckule", "fckule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcku$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKU, "fcku", "fcku", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcko$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKO, "fcko", "fcko", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckra$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKRA, "cckra", "cckra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckno$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNO, "cckno", "cckno", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNE, "cckne", "cckne", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLE, "cckle", "cckle", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGE, "cckge", "cckge", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLS, "cckls", "cckls", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKC, "cckc", "cckc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKN, "cckn", "cckn", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKP, "cckp", "cckp", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKV, "cckv", "cckv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckra$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckno$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* ici$pack @($GRi,$GRj) */
   {
     FRV_INSN_ICI, "ici", "ici", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dci$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCI, "dci", "dci", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* icei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_ICEI, "icei", "icei", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* dcei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEI, "dcei", "dcei", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* dcf$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCF, "dcf", "dcf", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcef$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEF, "dcef", "dcef", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* witlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WITLB, "witlb", "witlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* wdtlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* itlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* dtlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* icpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_ICPL, "icpl", "icpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
+    { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR450_MAJOR_I_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
   },
 /* icul$pack $GRi */
   {
     FRV_INSN_ICUL, "icul", "icul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcul$pack $GRi */
   {
     FRV_INSN_DCUL, "dcul", "dcul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* bar$pack */
   {
     FRV_INSN_BAR, "bar", "bar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* membar$pack */
   {
     FRV_INSN_MEMBAR, "membar", "membar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+  },
+/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+  {
+    FRV_INSN_LRAI, "lrai", "lrai", 32,
+    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+  {
+    FRV_INSN_LRAD, "lrad", "lrad", 32,
+    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
+  {
+    FRV_INSN_TLBPR, "tlbpr", "tlbpr", 32,
+    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP1, "cop1", "cop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP2, "cop2", "cop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* clrgr$pack $GRk */
   {
     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrfr$pack $FRk */
   {
     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrga$pack */
   {
     FRV_INSN_CLRGA, "clrga", "clrga", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrfa$pack */
   {
     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitgr$pack $GRk */
   {
     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitfr$pack $FRk */
   {
     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitga$pack */
   {
     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitfa$pack */
   {
     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* fitos$pack $FRintj,$FRk */
   {
     FRV_INSN_FITOS, "fitos", "fitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fitod$pack $FRintj,$FRdoublek */
   {
     FRV_INSN_FITOD, "fitod", "fitod", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdtoi$pack $FRdoublej,$FRintk */
   {
     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fditos$pack $FRintj,$FRk */
   {
     FRV_INSN_FDITOS, "fditos", "fditos", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* nfditos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* nfdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* nfitos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* nfstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fmovd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fnegd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fabss$pack $FRj,$FRk */
   {
     FRV_INSN_FABSS, "fabss", "fabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fabsd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdabss$pack $FRj,$FRk */
   {
     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* nfdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* fsqrtd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* nfsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FADDS, "fadds", "fadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* fdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FADDD, "faddd", "faddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
   },
 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* nfadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* nfsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* nfmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* nfdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
   {
     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
   {
     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAS, "fmas", "fmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSS, "fmss", "fmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fmad$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAD, "fmad", "fmad", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsd$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* nfmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* fddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
   },
 /* fdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
   },
 /* nfdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
   },
 /* mhsetlos$pack $u12,$FRklo */
   {
     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsethis$pack $u12,$FRkhi */
   {
     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhdsets$pack $u12,$FRintk */
   {
     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsetloh$pack $s5,$FRklo */
   {
     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsethih$pack $s5,$FRkhi */
   {
     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhdseth$pack $s5,$FRintk */
   {
     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mand$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAND, "mand", "mand", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MOR, "mor", "mor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mxor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MXOR, "mxor", "mxor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMAND, "cmand", "cmand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOR, "cmor", "cmor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mnot$pack $FRintj,$FRintk */
   {
     FRV_INSN_MNOT, "mnot", "mnot", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mrotli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mrotri$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwcut$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwcuti$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUT, "mcut", "mcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcuti$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
   {
     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDCUTSSI, FR400_MAJOR_M_2, FR450_MAJOR_M_6, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* maveh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAVEH, "maveh", "maveh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msllhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* msrlhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* msrahi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mdrotli$pack $FRintieven,$s6,$FRintkeven */
   {
     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* mcplhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* mcpli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* msaths$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHS, "msaths", "msaths", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
   },
 /* msathu$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHU, "msathu", "msathu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mabshs$pack $FRintj,$FRintk */
   {
     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
   },
 /* maddhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* maddhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msubhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msubhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+  },
+/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
+  {
+    FRV_INSN_MQLCLRHS, "mqlclrhs", "mqlclrhs", 32,
+    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
+  {
+    FRV_INSN_MQLMTHS, "mqlmths", "mqlmths", 32,
+    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
+  {
+    FRV_INSN_MQSLLHI, "mqsllhi", "mqsllhi", 32,
+    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
+  {
+    FRV_INSN_MQSRAHI, "mqsrahi", "mqsrahi", 32,
+    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* maddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* msubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* masaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
   {
     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mexpdhw$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mexpdhd$pack $FRinti,$u6,$FRintkeven */
   {
     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mpackh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
   },
 /* munpackh$pack $FRinti,$FRintkeven */
   {
     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mdunpackh$pack $FRintieven,$FRintk */
   {
     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
   },
 /* mbtoh$pack $FRintj,$FRintkeven */
   {
     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mhtob$pack $FRintjeven,$FRintk */
   {
     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mbtohe$pack $FRintj,$FRintk */
   {
     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
   },
 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
   },
 /* mnop$pack */
   {
     FRV_INSN_MNOP, "mnop", "mnop", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
   },
 /* mclracc$pack $ACC40Sk,$A0 */
   {
     FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
 /* mclracc$pack $ACC40Sk,$A1 */
   {
     FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
   },
 /* mrdacc$pack $ACC40Si,$FRintk */
   {
     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mrdaccg$pack $ACCGi,$FRintk */
   {
     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwtacc$pack $FRinti,$ACC40Sk */
   {
     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
 /* mwtaccg$pack $FRinti,$ACCGk */
   {
     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
 /* mcop1$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
   },
 /* mcop2$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
   },
 /* fnop$pack */
   {
     FRV_INSN_FNOP, "fnop", "fnop", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
   },
 };
 
diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h
index f46c3f9..5a11f8d 100644
--- a/opcodes/frv-desc.h
+++ b/opcodes/frv-desc.h
@@ -292,7 +292,8 @@ typedef enum spr_names {
  , H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666
  , H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670
  , H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768
- , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_FSR0 = 1024
+ , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_SCR0 = 832
+ , H_SPR_SCR1 = 833, H_SPR_SCR2 = 834, H_SPR_SCR3 = 835, H_SPR_FSR0 = 1024
  , H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028
  , H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032
  , H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036
@@ -454,19 +455,22 @@ typedef enum spr_names {
  , H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914
  , H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918
  , H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922
- , H_SPR_DCR = 2048, H_SPR_BRR = 2049, H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052
- , H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056
- , H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060
- , H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064
- , H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068
- , H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072
- , H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076
- , H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080
- , H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084
- , H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088
- , H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092
- , H_SPR_CPCR = 2093, H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097
- , H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
+ , H_SPR_IAMVR1 = 1925, H_SPR_DAMVR1 = 1927, H_SPR_CXNR = 1936, H_SPR_TTBR = 1937
+ , H_SPR_TPLR = 1938, H_SPR_TPPR = 1939, H_SPR_TPXR = 1940, H_SPR_TIMERH = 1952
+ , H_SPR_TIMERL = 1953, H_SPR_TIMERD = 1954, H_SPR_DCR = 2048, H_SPR_BRR = 2049
+ , H_SPR_NMAR = 2050, H_SPR_BTBR = 2051, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053
+ , H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057
+ , H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061
+ , H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065
+ , H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069
+ , H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073
+ , H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077
+ , H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081
+ , H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085
+ , H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089
+ , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093
+ , H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098
+ , H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
 } SPR_NAMES;
 
 /* Enum declaration for .  */
@@ -535,7 +539,8 @@ typedef enum cccr_names {
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
   MACH_BASE, MACH_FRV, MACH_FR550, MACH_FR500
- , MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
+ , MACH_FR450, MACH_FR400, MACH_TOMCAT, MACH_SIMPLE
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -551,7 +556,7 @@ typedef enum unit_attr {
  , UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
  , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC
  , UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL
- , UNIT_MDUALACC, UNIT_MCLRACC_1, UNIT_NUM_UNITS
+ , UNIT_MDUALACC, UNIT_MDCUTSSI, UNIT_MCLRACC_1, UNIT_NUM_UNITS
 } UNIT_ATTR;
 
 /* Enum declaration for fr400 major insn categories.  */
@@ -562,6 +567,15 @@ typedef enum fr400_major_attr {
  , FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2
 } FR400_MAJOR_ATTR;
 
+/* Enum declaration for fr450 major insn categories.  */
+typedef enum fr450_major_attr {
+  FR450_MAJOR_NONE, FR450_MAJOR_I_1, FR450_MAJOR_I_2, FR450_MAJOR_I_3
+ , FR450_MAJOR_I_4, FR450_MAJOR_I_5, FR450_MAJOR_B_1, FR450_MAJOR_B_2
+ , FR450_MAJOR_B_3, FR450_MAJOR_B_4, FR450_MAJOR_B_5, FR450_MAJOR_B_6
+ , FR450_MAJOR_C_1, FR450_MAJOR_C_2, FR450_MAJOR_M_1, FR450_MAJOR_M_2
+ , FR450_MAJOR_M_3, FR450_MAJOR_M_4, FR450_MAJOR_M_5, FR450_MAJOR_M_6
+} FR450_MAJOR_ATTR;
+
 /* Enum declaration for fr500 major insn categories.  */
 typedef enum fr500_major_attr {
   FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3
@@ -623,15 +637,17 @@ typedef enum ifield_type {
  , FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK
  , FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H
  , FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6
- , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL
- , FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL
- , FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL
- , FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL
- , FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL
- , FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4
- , FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8
- , FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF
- , FRV_F_LI_ON, FRV_F_MAX
+ , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD
+ , FRV_F_LRAS, FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL
+ , FRV_F_ICCI_2_NULL, FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL
+ , FRV_F_FCCI_3_NULL, FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL
+ , FRV_F_GRK_NULL, FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL
+ , FRV_F_RD_NULL, FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL
+ , FRV_F_LABEL16_NULL, FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3
+ , FRV_F_MISC_NULL_4, FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7
+ , FRV_F_MISC_NULL_8, FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11
+ , FRV_F_LRA_NULL, FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON
+ , FRV_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) FRV_F_MAX)
@@ -696,16 +712,17 @@ typedef enum cgen_operand_type {
  , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
  , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
  , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16
- , FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN
- , FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12
- , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
- , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
- , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
- , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
+ , FRV_OPERAND_LABEL24, FRV_OPERAND_LRAE, FRV_OPERAND_LRAD, FRV_OPERAND_LRAS
+ , FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL, FRV_OPERAND_A0, FRV_OPERAND_A1
+ , FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12
+ , FRV_OPERAND_S12, FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16
+ , FRV_OPERAND_SLO16, FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S
+ , FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET
+ , FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 81
+#define MAX_OPERANDS 86
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
@@ -717,9 +734,10 @@ typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
- , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
- , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
- , CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO
+ , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT
+ , CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR
+ , CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index b0f51bc..81af343 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -289,6 +289,21 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case FRV_OPERAND_LI :
       print_normal (cd, info, fields->f_LI, 0, pc, length);
       break;
+    case FRV_OPERAND_LRAD :
+      print_normal (cd, info, fields->f_LRAD, 0, pc, length);
+      break;
+    case FRV_OPERAND_LRAE :
+      print_normal (cd, info, fields->f_LRAE, 0, pc, length);
+      break;
+    case FRV_OPERAND_LRAS :
+      print_normal (cd, info, fields->f_LRAS, 0, pc, length);
+      break;
+    case FRV_OPERAND_TLBPRL :
+      print_normal (cd, info, fields->f_TLBPRL, 0, pc, length);
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length);
+      break;
     case FRV_OPERAND_AE :
       print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
       break;
diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c
index 565f4f4..03686f8 100644
--- a/opcodes/frv-ibld.c
+++ b/opcodes/frv-ibld.c
@@ -713,6 +713,21 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case FRV_OPERAND_LI :
       errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer);
       break;
+    case FRV_OPERAND_LRAD :
+      errmsg = insert_normal (cd, fields->f_LRAD, 0, 0, 4, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_LRAE :
+      errmsg = insert_normal (cd, fields->f_LRAE, 0, 0, 5, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_LRAS :
+      errmsg = insert_normal (cd, fields->f_LRAS, 0, 0, 3, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_TLBPRL :
+      errmsg = insert_normal (cd, fields->f_TLBPRL, 0, 0, 25, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      errmsg = insert_normal (cd, fields->f_TLBPRopx, 0, 0, 28, 3, 32, total_length, buffer);
+      break;
     case FRV_OPERAND_AE :
       errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer);
       break;
@@ -1016,6 +1031,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case FRV_OPERAND_LI :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI);
       break;
+    case FRV_OPERAND_LRAD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_LRAD);
+      break;
+    case FRV_OPERAND_LRAE :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_LRAE);
+      break;
+    case FRV_OPERAND_LRAS :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 1, 32, total_length, pc, & fields->f_LRAS);
+      break;
+    case FRV_OPERAND_TLBPRL :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_TLBPRL);
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_TLBPRopx);
+      break;
     case FRV_OPERAND_AE :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae);
       break;
@@ -1302,6 +1332,21 @@ frv_cgen_get_int_operand (cd, opindex, fields)
     case FRV_OPERAND_LI :
       value = fields->f_LI;
       break;
+    case FRV_OPERAND_LRAD :
+      value = fields->f_LRAD;
+      break;
+    case FRV_OPERAND_LRAE :
+      value = fields->f_LRAE;
+      break;
+    case FRV_OPERAND_LRAS :
+      value = fields->f_LRAS;
+      break;
+    case FRV_OPERAND_TLBPRL :
+      value = fields->f_TLBPRL;
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      value = fields->f_TLBPRopx;
+      break;
     case FRV_OPERAND_AE :
       value = fields->f_ae;
       break;
@@ -1539,6 +1584,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
     case FRV_OPERAND_LI :
       value = fields->f_LI;
       break;
+    case FRV_OPERAND_LRAD :
+      value = fields->f_LRAD;
+      break;
+    case FRV_OPERAND_LRAE :
+      value = fields->f_LRAE;
+      break;
+    case FRV_OPERAND_LRAS :
+      value = fields->f_LRAS;
+      break;
+    case FRV_OPERAND_TLBPRL :
+      value = fields->f_TLBPRL;
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      value = fields->f_TLBPRopx;
+      break;
     case FRV_OPERAND_AE :
       value = fields->f_ae;
       break;
@@ -1785,6 +1845,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
     case FRV_OPERAND_LI :
       fields->f_LI = value;
       break;
+    case FRV_OPERAND_LRAD :
+      fields->f_LRAD = value;
+      break;
+    case FRV_OPERAND_LRAE :
+      fields->f_LRAE = value;
+      break;
+    case FRV_OPERAND_LRAS :
+      fields->f_LRAS = value;
+      break;
+    case FRV_OPERAND_TLBPRL :
+      fields->f_TLBPRL = value;
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      fields->f_TLBPRopx = value;
+      break;
     case FRV_OPERAND_AE :
       fields->f_ae = value;
       break;
@@ -2019,6 +2094,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
     case FRV_OPERAND_LI :
       fields->f_LI = value;
       break;
+    case FRV_OPERAND_LRAD :
+      fields->f_LRAD = value;
+      break;
+    case FRV_OPERAND_LRAE :
+      fields->f_LRAE = value;
+      break;
+    case FRV_OPERAND_LRAS :
+      fields->f_LRAS = value;
+      break;
+    case FRV_OPERAND_TLBPRL :
+      fields->f_TLBPRL = value;
+      break;
+    case FRV_OPERAND_TLBPROPX :
+      fields->f_TLBPRopx = value;
+      break;
     case FRV_OPERAND_AE :
       fields->f_ae = value;
       break;
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index 1560d20..2e307e0 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -44,6 +44,8 @@ static int find_major_in_vliw
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
 static int fr400_check_insn_major_constraints
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr450_check_insn_major_constraints
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
 static int fr500_check_insn_major_constraints
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
 static int fr550_check_insn_major_constraints
@@ -60,6 +62,10 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
       if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
 	return 1; /* is a branch */
       break;
+    case bfd_mach_fr450:
+      if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
+	return 1; /* is a branch */
+      break;
     default:
       if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
 	return 1; /* is a branch */
@@ -75,6 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
   switch (mach)
     {
     case bfd_mach_fr400:
+    case bfd_mach_fr450:
       return 0; /* No float insns */
     default:
       if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
@@ -94,6 +101,10 @@ frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
       if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
 	return 1; /* is a media insn */
       break;
+    case bfd_mach_fr450:
+      if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
+	return 1; /* is a media insn */
+      break;
     default:
       if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
 	return 1; /* is a media insn */
@@ -109,6 +120,9 @@ frv_is_branch_insn (const CGEN_INSN *insn)
   if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			   bfd_mach_fr400))
     return 1;
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+			   bfd_mach_fr450))
+    return 1;
   if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			   bfd_mach_fr500))
     return 1;
@@ -122,6 +136,9 @@ frv_is_float_insn (const CGEN_INSN *insn)
   if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			  bfd_mach_fr400))
     return 1;
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+			  bfd_mach_fr450))
+    return 1;
   if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			  bfd_mach_fr500))
     return 1;
@@ -135,6 +152,9 @@ frv_is_media_insn (const CGEN_INSN *insn)
   if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
 			  bfd_mach_fr400))
     return 1;
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+			  bfd_mach_fr450))
+    return 1;
   if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
 			  bfd_mach_fr500))
     return 1;
@@ -245,6 +265,42 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
 /* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
 /* DCPL     */     UNIT_C,   /* dcpl                only in C   unit.  */
 /* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM0, /* mdcutssi            only in FM0 unit.  */
+/* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
+};
+
+/* Some insns are assigned specialized implementation units which map to
+   different actual implementation units on different machines.  These
+   tables perform that mapping.  */
+static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M3 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
+/* B0       */     UNIT_B0,  /* branches only in B0 unit.  */
+/* B1       */     UNIT_B0,
+/* B01      */     UNIT_B0,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0  unit.  */
+/* IACC     */     UNIT_I01, /* iacc multiply       in I0 or I1 unit.  */
+/* LOAD     */     UNIT_I0,  /* load                only in I0  unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0  unit.  */
+/* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
+/* DCPL     */     UNIT_I0,  /* dcpl                only in I0  unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM01, /* mdcutssi           in FM0 or FM1.  */
 /* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
 };
 
@@ -276,6 +332,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
 /* SCAN     */     UNIT_I01, /* scan                in I0 or I1 unit.  */
 /* DCPL     */     UNIT_C,   /* dcpl                only in C unit.  */
 /* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MDCUTSSI */     UNIT_FM0, /* mdcutssi            only in FM0 unit.  */
 /* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
 };
 
@@ -307,6 +364,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
 /* SCAN     */     UNIT_IALL, /* scan                in any integer unit. */
 /* DCPL     */     UNIT_I0,   /* dcpl                only in I0 unit.     */
 /* MDUALACC */     UNIT_FMALL,/* media dual acc insn in all media units   */
+/* MDCUTSSI */     UNIT_FM01, /* mdcutssi            in FM0 or FM1 unit.  */
 /* MCLRACC-1*/     UNIT_FM01  /* mclracc,A==1 in FM0 or FM1 unit.         */
 };
 
@@ -324,6 +382,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
       vliw->current_vliw = fr400_allowed_vliw;
       vliw->unit_mapping = fr400_unit_mapping;
       break;
+    case bfd_mach_fr450:
+      vliw->current_vliw = fr400_allowed_vliw;
+      vliw->unit_mapping = fr450_unit_mapping;
+      break;
     case bfd_mach_fr550:
       vliw->current_vliw = fr550_allowed_vliw;
       vliw->unit_mapping = fr550_unit_mapping;
@@ -453,6 +515,8 @@ fr400_check_insn_major_constraints (
     case FR400_MAJOR_M_2:
       return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
 	&&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    case FR400_MAJOR_M_1:
+      return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
     default:
       break;
     }
@@ -460,6 +524,43 @@ fr400_check_insn_major_constraints (
 }
 
 static int
+fr450_check_insn_major_constraints (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+  CGEN_ATTR_VALUE_TYPE other_major;
+
+  /* Our caller guarantees there's at least one other instruction.  */
+  other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
+
+  /* (M4, M5) and (M4, M6) are allowed.  */
+  if (other_major == FR450_MAJOR_M_4)
+    if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
+      return 1;
+
+  /* Otherwise, instructions in even-numbered media categories cannot be
+     executed in parallel with other media instructions.  */
+  switch (major)
+    {
+    case FR450_MAJOR_M_2:
+    case FR450_MAJOR_M_4:
+    case FR450_MAJOR_M_6:
+      return !(other_major >= FR450_MAJOR_M_1
+	       && other_major <= FR450_MAJOR_M_6);
+
+    case FR450_MAJOR_M_1:
+    case FR450_MAJOR_M_3:
+    case FR450_MAJOR_M_5:
+      return !(other_major == FR450_MAJOR_M_2
+	       || other_major == FR450_MAJOR_M_4
+	       || other_major == FR450_MAJOR_M_6);
+
+    default:
+      return 1;
+    }
+}
+
+static int
 find_unit_in_vliw (
   FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
 )
@@ -696,6 +797,9 @@ check_insn_major_constraints (
     case bfd_mach_fr400:
       rc = fr400_check_insn_major_constraints (vliw, major);
       break;
+    case bfd_mach_fr450:
+      rc = fr450_check_insn_major_constraints (vliw, major);
+      break;
     case bfd_mach_fr550:
       rc = fr550_check_insn_major_constraints (vliw, major, insn);
       break;
@@ -736,6 +840,9 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
     case bfd_mach_fr400:
       major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
       break;
+    case bfd_mach_fr450:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
+      break;
     case bfd_mach_fr550:
       major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
       break;
@@ -1149,6 +1256,14 @@ static const CGEN_IFMT ifmt_bar = {
   32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_lrai = {
+  32, 32, 0x1fc0fc7, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_LRAE) }, { F (F_LRAD) }, { F (F_LRAS) }, { F (F_LRA_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tlbpr = {
+  32, 32, 0x61fc0fc0, { { F (F_PACK) }, { F (F_TLBPR_NULL) }, { F (F_TLBPROPX) }, { F (F_TLBPRL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_cop1 = {
   32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } }
 };
@@ -1297,6 +1412,10 @@ static const CGEN_IFMT ifmt_cmqaddhss = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mqsllhi = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_maddaccs = {
   32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } }
 };
@@ -2486,42 +2605,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
     & ifmt_ldc, { 0xc0940 }
   },
-/* rstb$pack $GRk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_slass, { 0xc0800 }
-  },
-/* rsth$pack $GRk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_slass, { 0xc0840 }
-  },
-/* rst$pack $GRk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_slass, { 0xc0880 }
-  },
-/* rstbf$pack $FRintk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldbf, { 0xc0a00 }
-  },
-/* rsthf$pack $FRintk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldbf, { 0xc0a40 }
-  },
-/* rstf$pack $FRintk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldbf, { 0xc0a80 }
-  },
 /* std$pack $GRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
@@ -2540,18 +2623,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
     & ifmt_lddc, { 0xc0980 }
   },
-/* rstd$pack $GRdoublek,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldd, { 0xc08c0 }
-  },
-/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_lddf, { 0xc0ac0 }
-  },
 /* stq$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
@@ -2570,18 +2641,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
     & ifmt_ldc, { 0xc09c0 }
   },
-/* rstq$pack $GRk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_slass, { 0xc0900 }
-  },
-/* rstqf$pack $FRintk,@($GRi,$GRj) */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldbf, { 0xc0b00 }
-  },
 /* stbu$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
@@ -4616,6 +4675,24 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), 0 } },
     & ifmt_bar, { 0xc0fc0 }
   },
+/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
+    & ifmt_lrai, { 0xc0800 }
+  },
+/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
+    & ifmt_lrai, { 0xc0840 }
+  },
+/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (TLBPROPX), ',', OP (TLBPRL), 0 } },
+    & ifmt_tlbpr, { 0xc0900 }
+  },
 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     { 0, 0, 0, 0 },
@@ -5498,6 +5575,30 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmqaddhss, { 0x1cc00c0 }
   },
+/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1e00400 }
+  },
+/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1e00500 }
+  },
+/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsllhi, { 0x1e00440 }
+  },
+/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsllhi, { 0x1e004c0 }
+  },
 /* maddaccs$pack $ACC40Si,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
@@ -5966,37 +6067,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
 /* nop$pack */
   {
     -1, "nop", "nop", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* ret$pack */
   {
     -1, "ret", "ret", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
   },
 /* cmp$pack $GRi,$GRj,$ICCi_1 */
   {
     -1, "cmp", "cmp", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* cmpi$pack $GRi,$s10,$ICCi_1 */
   {
     -1, "cmpi", "cmpi", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* ccmp$pack $GRi,$GRj,$CCi,$cond */
   {
     -1, "ccmp", "ccmp", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* mov$pack $GRi,$GRk */
   {
     -1, "mov", "mov", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* cmov$pack $GRi,$GRk,$CCi,$cond */
   {
     -1, "cmov", "cmov", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 };
 
diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h
index e166fa2..dd343de 100644
--- a/opcodes/frv-opc.h
+++ b/opcodes/frv-opc.h
@@ -108,149 +108,148 @@ typedef enum cgen_insn_type {
  , FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI, FRV_INSN_NLDDFI
  , FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQFI, FRV_INSN_STB
  , FRV_INSN_STH, FRV_INSN_ST, FRV_INSN_STBF, FRV_INSN_STHF
- , FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_RSTB, FRV_INSN_RSTH
- , FRV_INSN_RST, FRV_INSN_RSTBF, FRV_INSN_RSTHF, FRV_INSN_RSTF
- , FRV_INSN_STD, FRV_INSN_STDF, FRV_INSN_STDC, FRV_INSN_RSTD
- , FRV_INSN_RSTDF, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC
- , FRV_INSN_RSTQ, FRV_INSN_RSTQF, FRV_INSN_STBU, FRV_INSN_STHU
- , FRV_INSN_STU, FRV_INSN_STBFU, FRV_INSN_STHFU, FRV_INSN_STFU
- , FRV_INSN_STCU, FRV_INSN_STDU, FRV_INSN_STDFU, FRV_INSN_STDCU
- , FRV_INSN_STQU, FRV_INSN_STQFU, FRV_INSN_STQCU, FRV_INSN_CLDSB
- , FRV_INSN_CLDUB, FRV_INSN_CLDSH, FRV_INSN_CLDUH, FRV_INSN_CLD
- , FRV_INSN_CLDBF, FRV_INSN_CLDHF, FRV_INSN_CLDF, FRV_INSN_CLDD
- , FRV_INSN_CLDDF, FRV_INSN_CLDQ, FRV_INSN_CLDSBU, FRV_INSN_CLDUBU
- , FRV_INSN_CLDSHU, FRV_INSN_CLDUHU, FRV_INSN_CLDU, FRV_INSN_CLDBFU
- , FRV_INSN_CLDHFU, FRV_INSN_CLDFU, FRV_INSN_CLDDU, FRV_INSN_CLDDFU
- , FRV_INSN_CLDQU, FRV_INSN_CSTB, FRV_INSN_CSTH, FRV_INSN_CST
- , FRV_INSN_CSTBF, FRV_INSN_CSTHF, FRV_INSN_CSTF, FRV_INSN_CSTD
- , FRV_INSN_CSTDF, FRV_INSN_CSTQ, FRV_INSN_CSTBU, FRV_INSN_CSTHU
- , FRV_INSN_CSTU, FRV_INSN_CSTBFU, FRV_INSN_CSTHFU, FRV_INSN_CSTFU
- , FRV_INSN_CSTDU, FRV_INSN_CSTDFU, FRV_INSN_STBI, FRV_INSN_STHI
- , FRV_INSN_STI, FRV_INSN_STBFI, FRV_INSN_STHFI, FRV_INSN_STFI
- , FRV_INSN_STDI, FRV_INSN_STDFI, FRV_INSN_STQI, FRV_INSN_STQFI
- , FRV_INSN_SWAP, FRV_INSN_SWAPI, FRV_INSN_CSWAP, FRV_INSN_MOVGF
- , FRV_INSN_MOVFG, FRV_INSN_MOVGFD, FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ
- , FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF, FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD
- , FRV_INSN_CMOVFGD, FRV_INSN_MOVGS, FRV_INSN_MOVSG, FRV_INSN_BRA
- , FRV_INSN_BNO, FRV_INSN_BEQ, FRV_INSN_BNE, FRV_INSN_BLE
- , FRV_INSN_BGT, FRV_INSN_BLT, FRV_INSN_BGE, FRV_INSN_BLS
- , FRV_INSN_BHI, FRV_INSN_BC, FRV_INSN_BNC, FRV_INSN_BN
- , FRV_INSN_BP, FRV_INSN_BV, FRV_INSN_BNV, FRV_INSN_FBRA
- , FRV_INSN_FBNO, FRV_INSN_FBNE, FRV_INSN_FBEQ, FRV_INSN_FBLG
- , FRV_INSN_FBUE, FRV_INSN_FBUL, FRV_INSN_FBGE, FRV_INSN_FBLT
- , FRV_INSN_FBUGE, FRV_INSN_FBUG, FRV_INSN_FBLE, FRV_INSN_FBGT
- , FRV_INSN_FBULE, FRV_INSN_FBU, FRV_INSN_FBO, FRV_INSN_BCTRLR
- , FRV_INSN_BRALR, FRV_INSN_BNOLR, FRV_INSN_BEQLR, FRV_INSN_BNELR
- , FRV_INSN_BLELR, FRV_INSN_BGTLR, FRV_INSN_BLTLR, FRV_INSN_BGELR
- , FRV_INSN_BLSLR, FRV_INSN_BHILR, FRV_INSN_BCLR, FRV_INSN_BNCLR
- , FRV_INSN_BNLR, FRV_INSN_BPLR, FRV_INSN_BVLR, FRV_INSN_BNVLR
- , FRV_INSN_FBRALR, FRV_INSN_FBNOLR, FRV_INSN_FBEQLR, FRV_INSN_FBNELR
- , FRV_INSN_FBLGLR, FRV_INSN_FBUELR, FRV_INSN_FBULLR, FRV_INSN_FBGELR
- , FRV_INSN_FBLTLR, FRV_INSN_FBUGELR, FRV_INSN_FBUGLR, FRV_INSN_FBLELR
- , FRV_INSN_FBGTLR, FRV_INSN_FBULELR, FRV_INSN_FBULR, FRV_INSN_FBOLR
- , FRV_INSN_BCRALR, FRV_INSN_BCNOLR, FRV_INSN_BCEQLR, FRV_INSN_BCNELR
- , FRV_INSN_BCLELR, FRV_INSN_BCGTLR, FRV_INSN_BCLTLR, FRV_INSN_BCGELR
- , FRV_INSN_BCLSLR, FRV_INSN_BCHILR, FRV_INSN_BCCLR, FRV_INSN_BCNCLR
- , FRV_INSN_BCNLR, FRV_INSN_BCPLR, FRV_INSN_BCVLR, FRV_INSN_BCNVLR
- , FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR, FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR
- , FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR, FRV_INSN_FCBULLR, FRV_INSN_FCBGELR
- , FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR, FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR
- , FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR, FRV_INSN_FCBULR, FRV_INSN_FCBOLR
- , FRV_INSN_JMPL, FRV_INSN_CALLL, FRV_INSN_JMPIL, FRV_INSN_CALLIL
- , FRV_INSN_CALL, FRV_INSN_RETT, FRV_INSN_REI, FRV_INSN_TRA
- , FRV_INSN_TNO, FRV_INSN_TEQ, FRV_INSN_TNE, FRV_INSN_TLE
- , FRV_INSN_TGT, FRV_INSN_TLT, FRV_INSN_TGE, FRV_INSN_TLS
- , FRV_INSN_THI, FRV_INSN_TC, FRV_INSN_TNC, FRV_INSN_TN
- , FRV_INSN_TP, FRV_INSN_TV, FRV_INSN_TNV, FRV_INSN_FTRA
- , FRV_INSN_FTNO, FRV_INSN_FTNE, FRV_INSN_FTEQ, FRV_INSN_FTLG
- , FRV_INSN_FTUE, FRV_INSN_FTUL, FRV_INSN_FTGE, FRV_INSN_FTLT
- , FRV_INSN_FTUGE, FRV_INSN_FTUG, FRV_INSN_FTLE, FRV_INSN_FTGT
- , FRV_INSN_FTULE, FRV_INSN_FTU, FRV_INSN_FTO, FRV_INSN_TIRA
- , FRV_INSN_TINO, FRV_INSN_TIEQ, FRV_INSN_TINE, FRV_INSN_TILE
- , FRV_INSN_TIGT, FRV_INSN_TILT, FRV_INSN_TIGE, FRV_INSN_TILS
- , FRV_INSN_TIHI, FRV_INSN_TIC, FRV_INSN_TINC, FRV_INSN_TIN
- , FRV_INSN_TIP, FRV_INSN_TIV, FRV_INSN_TINV, FRV_INSN_FTIRA
- , FRV_INSN_FTINO, FRV_INSN_FTINE, FRV_INSN_FTIEQ, FRV_INSN_FTILG
- , FRV_INSN_FTIUE, FRV_INSN_FTIUL, FRV_INSN_FTIGE, FRV_INSN_FTILT
- , FRV_INSN_FTIUGE, FRV_INSN_FTIUG, FRV_INSN_FTILE, FRV_INSN_FTIGT
- , FRV_INSN_FTIULE, FRV_INSN_FTIU, FRV_INSN_FTIO, FRV_INSN_BREAK
- , FRV_INSN_MTRAP, FRV_INSN_ANDCR, FRV_INSN_ORCR, FRV_INSN_XORCR
- , FRV_INSN_NANDCR, FRV_INSN_NORCR, FRV_INSN_ANDNCR, FRV_INSN_ORNCR
- , FRV_INSN_NANDNCR, FRV_INSN_NORNCR, FRV_INSN_NOTCR, FRV_INSN_CKRA
- , FRV_INSN_CKNO, FRV_INSN_CKEQ, FRV_INSN_CKNE, FRV_INSN_CKLE
- , FRV_INSN_CKGT, FRV_INSN_CKLT, FRV_INSN_CKGE, FRV_INSN_CKLS
- , FRV_INSN_CKHI, FRV_INSN_CKC, FRV_INSN_CKNC, FRV_INSN_CKN
- , FRV_INSN_CKP, FRV_INSN_CKV, FRV_INSN_CKNV, FRV_INSN_FCKRA
- , FRV_INSN_FCKNO, FRV_INSN_FCKNE, FRV_INSN_FCKEQ, FRV_INSN_FCKLG
- , FRV_INSN_FCKUE, FRV_INSN_FCKUL, FRV_INSN_FCKGE, FRV_INSN_FCKLT
- , FRV_INSN_FCKUGE, FRV_INSN_FCKUG, FRV_INSN_FCKLE, FRV_INSN_FCKGT
- , FRV_INSN_FCKULE, FRV_INSN_FCKU, FRV_INSN_FCKO, FRV_INSN_CCKRA
- , FRV_INSN_CCKNO, FRV_INSN_CCKEQ, FRV_INSN_CCKNE, FRV_INSN_CCKLE
- , FRV_INSN_CCKGT, FRV_INSN_CCKLT, FRV_INSN_CCKGE, FRV_INSN_CCKLS
- , FRV_INSN_CCKHI, FRV_INSN_CCKC, FRV_INSN_CCKNC, FRV_INSN_CCKN
- , FRV_INSN_CCKP, FRV_INSN_CCKV, FRV_INSN_CCKNV, FRV_INSN_CFCKRA
- , FRV_INSN_CFCKNO, FRV_INSN_CFCKNE, FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG
- , FRV_INSN_CFCKUE, FRV_INSN_CFCKUL, FRV_INSN_CFCKGE, FRV_INSN_CFCKLT
- , FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG, FRV_INSN_CFCKLE, FRV_INSN_CFCKGT
- , FRV_INSN_CFCKULE, FRV_INSN_CFCKU, FRV_INSN_CFCKO, FRV_INSN_CJMPL
- , FRV_INSN_CCALLL, FRV_INSN_ICI, FRV_INSN_DCI, FRV_INSN_ICEI
- , FRV_INSN_DCEI, FRV_INSN_DCF, FRV_INSN_DCEF, FRV_INSN_WITLB
- , FRV_INSN_WDTLB, FRV_INSN_ITLBI, FRV_INSN_DTLBI, FRV_INSN_ICPL
- , FRV_INSN_DCPL, FRV_INSN_ICUL, FRV_INSN_DCUL, FRV_INSN_BAR
- , FRV_INSN_MEMBAR, FRV_INSN_COP1, FRV_INSN_COP2, FRV_INSN_CLRGR
- , FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA, FRV_INSN_COMMITGR
- , FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA, FRV_INSN_FITOS
- , FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI, FRV_INSN_FDITOS
- , FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI, FRV_INSN_CFITOS
- , FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI, FRV_INSN_FMOVS
- , FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS, FRV_INSN_FNEGS
- , FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS, FRV_INSN_FABSS
- , FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS, FRV_INSN_FSQRTS
- , FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS
- , FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS, FRV_INSN_FMULS
- , FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD, FRV_INSN_FMULD
- , FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS, FRV_INSN_CFMULS
- , FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS, FRV_INSN_NFMULS
- , FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD, FRV_INSN_CFCMPS
- , FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS, FRV_INSN_FMADDD
- , FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS
- , FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS, FRV_INSN_FMAS
- , FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS, FRV_INSN_NFDMAS
- , FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS, FRV_INSN_FMAD
- , FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS, FRV_INSN_FDADDS
- , FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS, FRV_INSN_FDSADS
- , FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS
- , FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS
- , FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH
- , FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND, FRV_INSN_MOR
- , FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR, FRV_INSN_CMXOR
- , FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI, FRV_INSN_MROTRI
- , FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT, FRV_INSN_MCUTI
- , FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH
- , FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI, FRV_INSN_MDROTLI
- , FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS, FRV_INSN_MQSATHS
- , FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH, FRV_INSN_MABSHS
- , FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS
- , FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS
- , FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS
- , FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS
- , FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS
- , FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS, FRV_INSN_MMULHU
- , FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS, FRV_INSN_CMMULHU
- , FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU
- , FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS, FRV_INSN_MMACHU
- , FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS, FRV_INSN_CMMACHU
- , FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU
- , FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS
- , FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS
- , FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS
- , FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW
- , FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH
- , FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH
- , FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE
- , FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1
- , FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG
- , FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
+ , FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_STD, FRV_INSN_STDF
+ , FRV_INSN_STDC, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC
+ , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU
+ , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU
+ , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU
+ , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH
+ , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF
+ , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ
+ , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU
+ , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU
+ , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB
+ , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF
+ , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ
+ , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU
+ , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU
+ , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI
+ , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI
+ , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI
+ , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD
+ , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF
+ , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS
+ , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ
+ , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT
+ , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC
+ , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV
+ , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE
+ , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL
+ , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG
+ , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU
+ , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR
+ , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR
+ , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR
+ , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR
+ , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR
+ , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR
+ , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR
+ , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR
+ , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR
+ , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR
+ , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR
+ , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR
+ , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR
+ , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR
+ , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR
+ , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR
+ , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL
+ , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT
+ , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ
+ , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT
+ , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC
+ , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV
+ , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE
+ , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL
+ , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG
+ , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU
+ , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ
+ , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT
+ , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC
+ , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV
+ , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE
+ , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL
+ , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG
+ , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU
+ , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR
+ , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR
+ , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR
+ , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ
+ , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT
+ , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC
+ , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV
+ , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE
+ , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL
+ , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG
+ , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU
+ , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ
+ , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT
+ , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC
+ , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV
+ , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE
+ , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL
+ , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG
+ , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU
+ , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI
+ , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
+ , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
+ , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
+ , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_LRAI
+ , FRV_INSN_LRAD, FRV_INSN_TLBPR, FRV_INSN_COP1, FRV_INSN_COP2
+ , FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA
+ , FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA
+ , FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI
+ , FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI
+ , FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI
+ , FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS
+ , FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS
+ , FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS
+ , FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD
+ , FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS
+ , FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD
+ , FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS
+ , FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS
+ , FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD
+ , FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS
+ , FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS
+ , FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS
+ , FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS
+ , FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS
+ , FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS
+ , FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS
+ , FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS
+ , FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS
+ , FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS
+ , FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND
+ , FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR
+ , FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI
+ , FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT
+ , FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI
+ , FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI
+ , FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS
+ , FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH
+ , FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS
+ , FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS
+ , FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS
+ , FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS
+ , FRV_INSN_CMQSUBHUS, FRV_INSN_MQLCLRHS, FRV_INSN_MQLMTHS, FRV_INSN_MQSLLHI
+ , FRV_INSN_MQSRAHI, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS
+ , FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS
+ , FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS
+ , FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS
+ , FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS
+ , FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS
+ , FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS
+ , FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS
+ , FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU
+ , FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU
+ , FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU
+ , FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD
+ , FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH
+ , FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB
+ , FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0
+ , FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC
+ , FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
@@ -329,6 +328,11 @@ struct cgen_fields
   long f_labelH6;
   long f_labelL18;
   long f_label24;
+  long f_LRAE;
+  long f_LRAD;
+  long f_LRAS;
+  long f_TLBPRopx;
+  long f_TLBPRL;
   long f_ICCi_1_null;
   long f_ICCi_2_null;
   long f_ICCi_3_null;
@@ -358,6 +362,8 @@ struct cgen_fields
   long f_misc_null_9;
   long f_misc_null_10;
   long f_misc_null_11;
+  long f_LRA_null;
+  long f_TLBPR_null;
   long f_LI_off;
   long f_LI_on;
 };
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f9a0a9b..a71eb0c 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1,6 +1,6 @@
 /* Print i386 instructions for GDB, the GNU debugger.
    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2001, 2002, 2003 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004 Free Software Foundation, Inc.
 
 This file is part of GDB.
 
@@ -23,6 +23,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  * July 1988
  *  modified by John Hassey (hassey@dg-rtp.dg.com)
  *  x86-64 support added by Jan Hubicka (jh@suse.cz)
+ *  VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
  */
 
 /*
@@ -90,10 +91,15 @@ static void OP_EM (int, int);
 static void OP_EX (int, int);
 static void OP_MS (int, int);
 static void OP_XS (int, int);
+static void OP_M (int, int);
+static void OP_0fae (int, int);
+static void OP_0f07 (int, int);
+static void NOP_Fixup (int, int);
 static void OP_3DNowSuffix (int, int);
 static void OP_SIMD_Suffix (int, int);
 static void SIMD_Fixup (int, int);
 static void PNI_Fixup (int, int);
+static void INVLPG_Fixup (int, int);
 static void BadOp (void);
 
 struct dis_private {
@@ -196,8 +202,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define indirEv OP_indirE, v_mode
 #define Ew OP_E, w_mode
 #define Ma OP_E, v_mode
-#define M OP_E, 0		/* lea, lgdt, etc. */
-#define Mp OP_E, 0		/* 32 or 48 bit memory operand for LDS, LES etc */
+#define M OP_M, 0		/* lea, lgdt, etc. */
+#define Mp OP_M, 0		/* 32 or 48 bit memory operand for LDS, LES etc */
 #define Gb OP_G, b_mode
 #define Gv OP_G, v_mode
 #define Gd OP_G, d_mode
@@ -290,7 +296,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define EX OP_EX, v_mode
 #define MS OP_MS, v_mode
 #define XS OP_XS, v_mode
-#define None OP_E, 0
 #define OPSUF OP_3DNowSuffix, 0
 #define OPSIMD OP_SIMD_Suffix, 0
 
@@ -388,6 +393,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define GRP13	  NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0
 #define GRP14	  NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0
 #define GRPAMD	  NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0
+#define GRPPADLCK NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0
 
 #define PREGRP0   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  0, NULL, 0
 #define PREGRP1   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  1, NULL, 0
@@ -631,8 +637,7 @@ static const struct dis386 dis386[] = {
   { "movQ",		Sw, Ev, XX },
   { "popU",		Ev, XX, XX },
   /* 90 */
-  { "nop",		XX, XX, XX },
-  /* FIXME: NOP with REPz prefix is called PAUSE.  */
+  { "nop",		NOP_Fixup, 0, XX, XX },
   { "xchgS",		RMeCX, eAX, XX },
   { "xchgS",		RMeDX, eAX, XX },
   { "xchgS",		RMeBX, eAX, XX },
@@ -948,7 +953,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "shldS",		Ev, Gv, Ib },
   { "shldS",		Ev, Gv, CL },
   { "(bad)",		XX, XX, XX },
-  { "(bad)",		XX, XX, XX },
+  { GRPPADLCK },
   /* a8 */
   { "pushT",		gs, XX, XX },
   { "popT",		gs, XX, XX },
@@ -1086,7 +1091,7 @@ static const unsigned char twobyte_has_modrm[256] = {
   /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */
   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
-  /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */
+  /* a0 */ 0,0,0,1,1,1,0,1,0,0,0,1,1,1,1,1, /* af */
   /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */
   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
@@ -1360,7 +1365,7 @@ static const struct dis386 grps[][8] = {
     { "smswQ",	Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "lmsw",	Ew, XX, XX },
-    { "invlpg",	Ew, XX, XX },
+    { "invlpg",	INVLPG_Fixup, w_mode, XX, XX },
   },
   /* GRP8 */
   {
@@ -1424,10 +1429,9 @@ static const struct dis386 grps[][8] = {
     { "ldmxcsr", Ev, XX, XX },
     { "stmxcsr", Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
-    { "lfence", None, XX, XX },
-    { "mfence", None, XX, XX },
-    { "sfence", None, XX, XX },
-    /* FIXME: the sfence with memory operand is clflush!  */
+    { "lfence", OP_0fae, 0, XX, XX },
+    { "mfence", OP_0fae, 0, XX, XX },
+    { "clflush", OP_0fae, 0, XX, XX },
   },
   /* GRP14 */
   {
@@ -1450,6 +1454,17 @@ static const struct dis386 grps[][8] = {
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
+  },
+  /* GRPPADLCK */
+  {
+    { "xstorerng", OP_0f07, 0, XX, XX },
+    { "xcryptecb", OP_0f07, 0, XX, XX },
+    { "xcryptcbc", OP_0f07, 0, XX, XX },
+    { "(bad)",	   OP_0f07, 0, XX, XX },
+    { "xcryptcfb", OP_0f07, 0, XX, XX },
+    { "xcryptofb", OP_0f07, 0, XX, XX },
+    { "(bad)",	   OP_0f07, 0, XX, XX },
+    { "(bad)",	   OP_0f07, 0, XX, XX },
   }
 };
 
@@ -3034,10 +3049,6 @@ OP_E (int bytemode, int sizeflag)
 	  used_prefixes |= (prefixes & PREFIX_DATA);
 	  break;
 	case 0:
-	  if (!(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */)
-	      && !(codep[-2] == 0xAE && codep[-1] == 0xF0 /* mfence */)
-	      && !(codep[-2] == 0xAE && codep[-1] == 0xe8 /* lfence */))
-	    BadOp ();	/* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
 	  break;
 	default:
 	  oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -3940,6 +3951,55 @@ OP_XS (int bytemode, int sizeflag)
     BadOp ();
 }
 
+static void
+OP_M (int bytemode, int sizeflag)
+{
+  if (mod == 3)
+    BadOp ();	/* bad lea,lds,les,lfs,lgs,lss modrm */
+  else
+    OP_E (bytemode, sizeflag);
+}
+
+static void
+OP_0f07 (int bytemode, int sizeflag)
+{
+  if (mod != 3 || rm != 0)
+    BadOp ();
+  else
+    OP_E (bytemode, sizeflag);
+}
+
+static void
+OP_0fae (int bytemode, int sizeflag)
+{
+  if (mod == 3)
+    {
+      if (reg == 7)
+	strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
+
+      if (reg < 5 || rm != 0)
+	{
+	  BadOp ();	/* bad sfence, mfence, or lfence */
+	  return;
+	}
+    }
+  else if (reg != 7)
+    {
+      BadOp ();		/* bad clflush */
+      return;
+    }
+
+  OP_E (bytemode, sizeflag);
+}
+
+static void
+NOP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+  /* NOP with REPZ prefix is called PAUSE.  */
+  if (prefixes == PREFIX_REPZ)
+    strcpy (obuf, "pause");
+}
+
 static const char *const Suffix3DNow[] = {
 /* 00 */	NULL,		NULL,		NULL,		NULL,
 /* 04 */	NULL,		NULL,		NULL,		NULL,
@@ -4100,7 +4160,7 @@ SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
 }
 
 static void
-PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
 {
   if (mod == 3 && reg == 1)
     {
@@ -4125,6 +4185,21 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
 }
 
 static void
+INVLPG_Fixup (int bytemode, int sizeflag)
+{
+  if (*codep == 0xf8)
+    {
+      char *p = obuf + strlen (obuf);
+
+      /* Override "invlpg".  */
+      strcpy (p - 6, "swapgs");
+      codep++;
+    }
+  else
+    OP_E (bytemode, sizeflag);
+}
+
+static void
 BadOp (void)
 {
   /* Throw away prefixes and 1st. opcode byte.  */
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index f16a87b..333c612 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -18,6 +18,7 @@ d30v-dis.c
 d30v-opc.c
 disassemble.c
 dis-buf.c
+dis-init.c
 dlx-dis.c
 fr30-asm.c
 fr30-desc.c
diff --git a/opcodes/po/de.po b/opcodes/po/de.po
index 2914776..e802823 100644
--- a/opcodes/po/de.po
+++ b/opcodes/po/de.po
@@ -4,10 +4,10 @@
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: opcodes 2.12.91\n"
-"POT-Creation-Date: 2002-07-23 15:55-0400\n"
-"PO-Revision-Date: 2002-09-24 07:13+0200\n"
-"Last-Translator: Martin v. Löwis <martin@v.loewis.de>\n"
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2004-02-28 12:30+0100\n"
+"Last-Translator: Roland Illig <roland.illig@gmx.de>\n"
 "Language-Team: German <de@li.org>\n"
 "MIME-Version: 1.0\n"
 "Content-Type: text/plain; charset=utf-8\n"
@@ -25,56 +25,60 @@ msgstr "Sprunghinweis ist nicht ausgerichtet (unaligned)."
 msgid "Illegal limm reference in last instruction!\n"
 msgstr "Ungültige limm-Referenz in der letzten Anweisung!\n"
 
-#: arm-dis.c:507
+#: arm-dis.c:554
 msgid "<illegal precision>"
-msgstr "<ungültige Präzision>"
+msgstr "<ungültige Genauigkeit>"
 
-#: arm-dis.c:1010
+#: arm-dis.c:1162
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr "Unbekannte Registernamensmenge: %s\n"
 
-#: arm-dis.c:1017
+#: arm-dis.c:1169
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr "Unbekannte Disassembler-Option: %s\n"
 
-#: arm-dis.c:1191
+#: arm-dis.c:1343
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
 "the -M switch:\n"
 msgstr ""
+"\n"
+"Die folgenden ARM-spezifischen Disassembleroptionen werden in Kombination\n"
+"mit dem Schalter »-M« unterstützt:\n"
 
-#: avr-dis.c:118 avr-dis.c:128
+#: avr-dis.c:117 avr-dis.c:127
 msgid "undefined"
 msgstr "undefiniert"
 
-#: avr-dis.c:180
+#: avr-dis.c:179
 msgid "Internal disassembler error"
 msgstr "Interner Disassemblerfehler."
 
-#: avr-dis.c:228
+#: avr-dis.c:227
 #, c-format
 msgid "unknown constraint `%c'"
-msgstr ""
+msgstr "Unbekannte Einschränkung »%c«"
 
-#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195
-#: openrisc-ibld.c:195 xstormy16-ibld.c:195
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
-msgstr ""
+msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %ld)"
 
-#: cgen-asm.c:367
+#: cgen-asm.c:369
 #, c-format
 msgid "operand out of range (%lu not between %lu and %lu)"
-msgstr ""
+msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen %lu und %lu)"
 
 #: d30v-dis.c:312
 #, c-format
 msgid "<unknown register %d>"
 msgstr "<unbekanntes Register %d>"
 
+#  Can't happen.
 #. Can't happen.
 #: dis-buf.c:57
 #, c-format
@@ -84,286 +88,641 @@ msgstr "Unbekannter Fehler %d\n"
 #: dis-buf.c:62
 #, c-format
 msgid "Address 0x%x is out of bounds.\n"
-msgstr ""
+msgstr "Adresse 0x%x ist außerhalb des gültigen Bereichs.\n"
 
-#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244
-#: xstormy16-asm.c:231
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Parsen entdeckt.\n"
 
-#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294
-#: xstormy16-asm.c:281
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
 msgid "missing mnemonic in syntax string"
-msgstr ""
+msgstr "Fehlender Mnemonic im Syntaxstring"
 
+#  We couldn't parse it.
 #. We couldn't parse it.
-#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781
-#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515
-#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434
-#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417
-#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
 msgid "unrecognized instruction"
-msgstr ""
+msgstr "Unbekannter Befehl"
 
-#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477
-#: xstormy16-asm.c:464
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr "Syntaxfehler (erwartetes Zeichen »%c«, gefunden »%c«)"
 
-#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487
-#: xstormy16-asm.c:474
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
-msgstr ""
+msgstr "Syntaxfehler (Zeichen »%c« erwartet, Befehlsende bekommen)"
 
-#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515
-#: xstormy16-asm.c:502
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
 msgid "junk at end of line"
-msgstr ""
+msgstr "Müll am Ende der Zeile"
 
-#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622
-#: xstormy16-asm.c:609
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
 msgid "unrecognized form of instruction"
-msgstr ""
+msgstr "Unbekannte Befehlsform"
 
-#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634
-#: xstormy16-asm.c:621
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
 #, c-format
 msgid "bad instruction `%.50s...'"
-msgstr ""
+msgstr "Falscher Befehl »%.50s...«"
 
-#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637
-#: xstormy16-asm.c:624
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
 #, c-format
 msgid "bad instruction `%.50s'"
-msgstr ""
+msgstr "Falscher Befehl »%.50s«"
 
+#  Default text to print if an instruction isn't recognized.
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
-#: xstormy16-dis.c:39
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
-msgstr ""
+msgstr "*unbekannt*"
 
-#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136
-#: xstormy16-dis.c:169
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Schreiben des Befehls.\n"
 
-#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166
-#: xstormy16-ibld.c:166
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
-msgstr ""
+msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %lu)"
 
-#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179
-#: xstormy16-ibld.c:179
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
 #, c-format
 msgid "operand out of range (%lu not between 0 and %lu)"
-msgstr ""
+msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen 0 und %lu)"
 
-#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633
-#: xstormy16-ibld.c:678
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Erzeugen des Befehls.\n"
 
-#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735
-#: xstormy16-ibld.c:826
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
-msgstr ""
+msgstr "Unbekannted Feld %d beim Decodieren des Befehls.\n"
 
-#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815
-#: xstormy16-ibld.c:939
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Holen des int-Operanden.\n"
 
-#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875
-#: xstormy16-ibld.c:1032
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n"
 
-#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944
-#: xstormy16-ibld.c:1134
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Setzen des int-Operanden.\n"
 
-#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001
-#: xstormy16-ibld.c:1224
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
-msgstr ""
+msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "Die Registernummer muss gerade sein."
 
-#: h8300-dis.c:385
+#: h8300-dis.c:377
 #, c-format
-msgid "Hmmmm %x"
-msgstr ""
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
 
-#: h8300-dis.c:396
+#: h8300-dis.c:760
 #, c-format
-msgid "Don't understand %x \n"
-msgstr ""
+msgid "Don't understand 0x%x \n"
+msgstr "Ich verstehe »0x%x« nicht.\n"
 
 #: h8500-dis.c:143
 #, c-format
 msgid "can't cope with insert %d\n"
-msgstr ""
+msgstr "Kann nicht mit »inserv %d« umgehen.\n"
 
+#  Couldn't understand anything.
 #. Couldn't understand anything.
 #: h8500-dis.c:350
 #, c-format
 msgid "%02x\t\t*unknown*"
-msgstr ""
+msgstr "%02x\t\t*unbekannt*"
 
-#: i386-dis.c:1649
+#: i386-dis.c:1699
 msgid "<internal disassembler error>"
-msgstr ""
+msgstr "<interner Disassemblerfehler>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Fehler:"
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Warnung:"
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "Mehrfache Bemerkung »%s« nicht verarbeitet.\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "Kann »ia64-ic.tbl« nicht zum Lesen finden\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "Kann »%s« nicht zum Lesen finden\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr "Das letzte Format »%s« scheint strenger zu sein als »%s«.\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "Überlappendes Feld »%s->%s«.\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "Überschreibe Bemerkung %d mit Bemerkung %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "Keine Ahnung, wie ich die Abhängigkeit »%% %s« angeben soll.\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "Keine Ahnung, wie ich die Abhängigkeit »# %s« angeben soll.\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] hat weder Terminale noch Unterklassen\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s hat weder Terminale noch Unterklassen\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "Kein Befehl ist dem Terminal-IC »%s [%s]« direkt zugeordnet"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "Kein Befehl ist dem Terminal-IC »%s« direkt zugeordnet.\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "Die Klasse »%s« wurde definiert, aber nicht benutzt.\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Warnung: Die Ressource »%s (%s)« hat keine »chks%s«.\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "Die Ressource »%s (%s)« hat keine Register\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC Bemerkung %d in Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC Bemerkung %d für Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "Opcode %s hat keine Klasse (Operanden %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "Kann nicht in das Verzeichnis »%s« wechseln, errno = %s\n"
+
+#  We've been passed a w.  Return with an error message so that
+#  cgen will try the next parsing option.
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "Schlüsselwort »W« ist im Operandenplatz »FR« ungültig."
+
+#  Invalid offset present.
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "»offset(IP)« ist keine gültige Form."
+
+#  Found something there in front of (DP) but it's out
+#  of range.
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) Offset außerhalb des gültigen Bereichs."
+
+#  Found something there in front of (SP) but it's out
+#  of range.
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) Offset außerhalb des gültigen Bereichs."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "Unerlaubte Benutzung von Klammern."
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "Operand außerhalb des gültigen Bereichs (1 bis 255)."
+
+#  Something is very wrong. opindex has to be one of the above.
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: Ungültiger Operatorindex."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Byteadresse benötigt -- muss gerade sein."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address: Gebe Symbol zurück. Sollte eigentlich ein Literal sein."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "Der Operand %operator muss ein Symbol sein."
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Versuch, ein gesetztes Bit von 0 zu bestimmen"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "Ein Direktoperand kann kein Register sein."
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "Direktoperand außerhalb des gültigen Bereichs."
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "21-Bit-Offset außerhalb des gültigen Bereichs"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "Fehlende »)«."
 
 #: m10200-dis.c:199
 #, c-format
 msgid "unknown\t0x%02x"
-msgstr ""
+msgstr "unbekannt\t0x%02x"
 
 #: m10200-dis.c:339
 #, c-format
 msgid "unknown\t0x%04lx"
-msgstr ""
+msgstr "unbekannt\t0x%04lx"
 
-#: m10300-dis.c:685
+#: m10300-dis.c:766
 #, c-format
 msgid "unknown\t0x%04x"
-msgstr ""
+msgstr "unbekannt\t0x%04x"
 
 #: m68k-dis.c:429
 #, c-format
 msgid "<internal error in opcode table: %s %s>\n"
-msgstr ""
+msgstr "<interner Fehler in der Opcode-Tabelle: %s %s>\n"
 
 #: m68k-dis.c:1007
 #, c-format
 msgid "<function code %d>"
-msgstr ""
+msgstr "<Funktionscode %d>"
 
-#: m88k-dis.c:255
+#: m88k-dis.c:746
 #, c-format
 msgid "# <dis error: %08x>"
-msgstr ""
+msgstr "# <Disassemblierungsfehler: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# Interner Fehler, unvollständige Erweiterungsfolge (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# Interner Fehler, undefinierte Erweiterungsfolge (+%c)"
 
-#: mips-dis.c:337
+#: mips-dis.c:1000
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
-msgstr ""
+msgstr "# Interner Fehler, undefinierter Modifikator (%c)"
 
-#: mips-dis.c:1209
+#: mips-dis.c:1751
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# Interner Fehler im Disassembler: unerkannter Modifikator (%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Die folgenden MIPS-spezifischen Disassembleroptionen werden zusammen\n"
+"mit dem Schalter »-M« unterstützt (mehrere Optionen sollten durch\n"
+"Kommata getrennt werden):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
 msgstr ""
+"\n"
+"  gpr-names=ABI            Gib GPR-Namen entsprechend des angegebenen ABI aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           disassembliert wird.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Gib FPR-Namen entsprechend des angegebenen ABI aus.\n"
+"                           Standard: numerisch.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Gib CP0-Registernamen entsprechend der angegebenen\n"
+"                           Architektur aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           disassembliert wird.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Gib HWR-Namen entsprechend der angegebenen\n"
+"                           Architektur aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           verarbeitet wird.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Gib GPR- und FPR-Namen entsprechend des\n"
+"                           angegebenen ABI aus.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Gib CP0-Register und HWR-Namen entsprechend der\n"
+"                           angegebenen Architektur aus.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Für die obigen Optionen werden die folgenden Werte für »ABI« unterstützt:\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Für die obigen Optionen werden die folgenden Werte für »ARCH« unterstützt:\n"
+"   "
 
 #: mmix-dis.c:34
 #, c-format
 msgid "Bad case %d (%s) in %s:%d\n"
-msgstr ""
+msgstr "Interner Fehler: case %d (%s) in %s:%d\n"
 
 #: mmix-dis.c:44
 #, c-format
 msgid "Internal: Non-debugged code (test-case missing): %s:%d"
-msgstr ""
+msgstr "Intern: Nicht gedebuggter Code (Testfall fehlt): %s:%d"
 
 #: mmix-dis.c:53
 msgid "(unknown)"
-msgstr ""
+msgstr "(unbekannt)"
 
-#: mmix-dis.c:517
+#: mmix-dis.c:519
 #, c-format
 msgid "*unknown operands type: %d*"
-msgstr ""
+msgstr "Unbekannter Operandentyp: %d*"
 
+#  I and Z are output operands and can`t be immediate
+#  * A is an address and we can`t have the address of
+#  * an immediate either. We don't know how much to increase
+#  * aoffsetp by since whatever generated this is broken
+#  * anyway!
 #. I and Z are output operands and can`t be immediate
 #. * A is an address and we can`t have the address of
 #. * an immediate either. We don't know how much to increase
 #. * aoffsetp by since whatever generated this is broken
 #. * anyway!
 #.
-#: ns32k-dis.c:628
+#: ns32k-dis.c:631
 msgid "$<undefined>"
-msgstr ""
+msgstr "$<undefiniert>"
 
-#: ppc-opc.c:777 ppc-opc.c:810
+#: ppc-opc.c:781 ppc-opc.c:809
 msgid "invalid conditional option"
-msgstr ""
+msgstr "Ungültige bedingte Option"
 
-#: ppc-opc.c:812
+#: ppc-opc.c:811
 msgid "attempt to set y bit when using + or - modifier"
-msgstr ""
+msgstr "Versuch, das y-Bit zusammen mit dem Modifikator »+« oder »-« zu setzen."
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "Offset muss ein Vielfaches von 16 sein"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "Offset muss ein Vielfaches von 2 sein"
 
-#: ppc-opc.c:844 ppc-opc.c:896
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "Offset darf nicht größer als 62 sein"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
 msgid "offset not a multiple of 4"
-msgstr ""
+msgstr "Offset muss ein Vielfaches von 4 sein"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "Offset darf nicht größer als 124 sein"
 
-#: ppc-opc.c:869
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "Offset muss ein Vielfaches von 8 sein"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "Offset darf nicht größer als 248 sein"
+
+#: ppc-opc.c:950
 msgid "offset not between -2048 and 2047"
-msgstr ""
+msgstr "Offset muss im Bereich von -2048 bis 2047 liegen"
 
-#: ppc-opc.c:894
+#: ppc-opc.c:973
 msgid "offset not between -8192 and 8191"
-msgstr ""
+msgstr "Offset muss im Bereich von -8192 bis 8191 liegen"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "Ignoriere ungültige mfcr-Maske."
 
-#: ppc-opc.c:922
+#: ppc-opc.c:1059
 msgid "ignoring least significant bits in branch offset"
-msgstr ""
+msgstr "Ignoriere niedrigste Bits im Verzweigungsoffset"
 
-#: ppc-opc.c:956 ppc-opc.c:993
+#: ppc-opc.c:1090 ppc-opc.c:1125
 msgid "illegal bitmask"
-msgstr ""
+msgstr "Ungültige Bitmaske"
 
-#: ppc-opc.c:1066
+#: ppc-opc.c:1192
 msgid "value out of range"
-msgstr ""
+msgstr "Wert außerhalb des gültigen Bereichs"
 
-#: ppc-opc.c:1142
+#: ppc-opc.c:1262
 msgid "index register in load range"
-msgstr ""
+msgstr "Indexregister im Ladebereich (load range)"
 
-#: ppc-opc.c:1158
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "Die Operanden für das Quell- und Zielregister müssen verschieden sein"
+
+#: ppc-opc.c:1294
 msgid "invalid register operand when updating"
-msgstr ""
+msgstr "Ungültiger Registeroperand beim Aktualisieren"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "Der Zielregisteroperand muss gerade sein"
 
-#. Mark as non-valid instruction
-#: sparc-dis.c:750
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "Der Quellregisteroperand muss gerade sein"
+
+#  Mark as non-valid instruction.
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
 msgid "unknown"
-msgstr ""
+msgstr "unbekannt"
 
-#: sparc-dis.c:825
+#: sparc-dis.c:835
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
-msgstr ""
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:836
+#: sparc-dis.c:846
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
-msgstr ""
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n"
 
-#: sparc-dis.c:885
+#: sparc-dis.c:895
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
-msgstr ""
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\" == \"%s\"\n"
 
-#: v850-dis.c:224
+#: v850-dis.c:221
 #, c-format
 msgid "unknown operand shift: %x\n"
-msgstr ""
+msgstr "Unbekannte Operandenverschiebung: %x\n"
 
-#: v850-dis.c:236
+#: v850-dis.c:233
 #, c-format
 msgid "unknown pop reg: %d\n"
-msgstr ""
+msgstr "Unbekanntes pop-Register: %d\n"
 
+#  The functions used to insert and extract complicated operands.
+#  Note: There is a conspiracy between these functions and
+#  v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#  containing the string 'out of range' will be ignored unless a
+#  specific command line option is given to GAS.
 #. The functions used to insert and extract complicated operands.
 #. Note: There is a conspiracy between these functions and
 #. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
@@ -371,72 +730,84 @@ msgstr ""
 #. specific command line option is given to GAS.
 #: v850-opc.c:68
 msgid "displacement value is not in range and is not aligned"
-msgstr ""
+msgstr "Der Abstandswert ist außerhalb des gültigen Bereichs und nicht ausgerichtet"
 
 #: v850-opc.c:69
 msgid "displacement value is out of range"
-msgstr ""
+msgstr "Der Abstandswert ist außerhalb des fültigen Bereichs."
 
 #: v850-opc.c:70
 msgid "displacement value is not aligned"
-msgstr ""
+msgstr "Der Abstandswert ist nicht ausgerichtet."
 
 #: v850-opc.c:72
 msgid "immediate value is out of range"
-msgstr ""
+msgstr "Direktwert außerhalb des gültigen Bereichs"
 
 #: v850-opc.c:83
 msgid "branch value not in range and to odd offset"
-msgstr ""
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset."
 
 #: v850-opc.c:85 v850-opc.c:117
 msgid "branch value out of range"
-msgstr ""
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs."
 
 #: v850-opc.c:88 v850-opc.c:120
 msgid "branch to odd offset"
-msgstr ""
+msgstr "Verzweigung auf ungeraden Offset"
 
 #: v850-opc.c:115
 msgid "branch value not in range and to an odd offset"
-msgstr ""
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset."
 
 #: v850-opc.c:346
 msgid "invalid register for stack adjustment"
-msgstr ""
+msgstr "Ungültiges Register für Stackanpassung."
 
 #: v850-opc.c:370
 msgid "immediate value not in range and not even"
-msgstr ""
+msgstr "Direktwert außerhalb des gültigen Bereichs und nicht gerade"
 
 #: v850-opc.c:375
 msgid "immediate value must be even"
 msgstr "Der Direktoperand muss gerade sein."
 
-#: xstormy16-asm.c:74
+#: xstormy16-asm.c:76
 msgid "Bad register in preincrement"
-msgstr ""
+msgstr "Ungültiges Register beim Pre-Increment"
 
-#: xstormy16-asm.c:79
+#: xstormy16-asm.c:81
 msgid "Bad register in postincrement"
-msgstr ""
+msgstr "Ungültiges Register beim Post-Increment"
 
-#: xstormy16-asm.c:81
+#: xstormy16-asm.c:83
 msgid "Bad register name"
 msgstr "Falscher Registername."
 
-#: xstormy16-asm.c:85
+#: xstormy16-asm.c:87
 msgid "Label conflicts with register name"
-msgstr ""
+msgstr "Sprungmarke verträgt sich nicht mit dem Registername"
 
-#: xstormy16-asm.c:89
+#: xstormy16-asm.c:91
 msgid "Label conflicts with `Rx'"
-msgstr ""
+msgstr "Sprungmarke verträgt sich nicht mit »Rx«"
 
-#: xstormy16-asm.c:91
+#: xstormy16-asm.c:93
 msgid "Bad immediate expression"
-msgstr ""
+msgstr "Ungültiger Direktausdruck"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Keine Verlagerung für kleine Direktwerte"
 
-#: xstormy16-asm.c:120
+#: xstormy16-asm.c:125
 msgid "Small operand was not an immediate number"
-msgstr ""
+msgstr "Kleiner Operand war keine Direktzahl."
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Operand muss ein Symbol sein"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Syntaxfehler: Kein abschließendes »)«"
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index 15fdff0..9ab8790 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -1,12 +1,14 @@
 # SOME DESCRIPTIVE TITLE.
-# Copyright (C) YEAR Free Software Foundation, Inc.
+# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER
+# This file is distributed under the same license as the PACKAGE package.
 # FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
 #
 #, fuzzy
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2003-07-17 14:54+0100\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2004-03-19 14:59+1030\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -14,11 +16,11 @@ msgstr ""
 "Content-Type: text/plain; charset=CHARSET\n"
 "Content-Transfer-Encoding: 8bit\n"
 
-#: alpha-opc.c:335
+#: alpha-opc.c:330
 msgid "branch operand unaligned"
 msgstr ""
 
-#: alpha-opc.c:358 alpha-opc.c:380
+#: alpha-opc.c:352 alpha-opc.c:373
 msgid "jump hint unaligned"
 msgstr ""
 
@@ -26,21 +28,24 @@ msgstr ""
 msgid "Illegal limm reference in last instruction!\n"
 msgstr ""
 
-#: arm-dis.c:554
+#: arm-dis.c:563
 msgid "<illegal precision>"
 msgstr ""
 
-#: arm-dis.c:1162
+#. XXX - should break 'option' at following delimiter.
+#: arm-dis.c:1199
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
-#: arm-dis.c:1169
+#. XXX - should break 'option' at following delimiter.
+#: arm-dis.c:1207
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:1343
+#: arm-dis.c:1376
+#, c-format
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
@@ -48,10 +53,12 @@ msgid ""
 msgstr ""
 
 #: avr-dis.c:117 avr-dis.c:127
+#, c-format
 msgid "undefined"
 msgstr ""
 
 #: avr-dis.c:179
+#, c-format
 msgid "Internal disassembler error"
 msgstr ""
 
@@ -60,13 +67,13 @@ msgstr ""
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
-#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#: cgen-asm.c:335 fr30-ibld.c:197 frv-ibld.c:197 ip2k-ibld.c:197
+#: iq2000-ibld.c:197 m32r-ibld.c:197 openrisc-ibld.c:197 xstormy16-ibld.c:197
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr ""
 
-#: cgen-asm.c:369
+#: cgen-asm.c:357
 #, c-format
 msgid "operand out of range (%lu not between %lu and %lu)"
 msgstr ""
@@ -87,58 +94,58 @@ msgstr ""
 msgid "Address 0x%x is out of bounds.\n"
 msgstr ""
 
-#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
-#: openrisc-asm.c:244 xstormy16-asm.c:284
+#: fr30-asm.c:323 frv-asm.c:967 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:335
+#: openrisc-asm.c:261 xstormy16-asm.c:284
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr ""
 
-#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
-#: openrisc-asm.c:294 xstormy16-asm.c:334
+#: fr30-asm.c:372 frv-asm.c:1016 ip2k-asm.c:623 iq2000-asm.c:509
+#: m32r-asm.c:384 openrisc-asm.c:310 xstormy16-asm.c:333
 msgid "missing mnemonic in syntax string"
 msgstr ""
 
 #. We couldn't parse it.
-#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
-#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
-#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
-#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
-#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434
-#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470
-#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+#: fr30-asm.c:507 fr30-asm.c:511 fr30-asm.c:598 fr30-asm.c:699 frv-asm.c:1151
+#: frv-asm.c:1155 frv-asm.c:1242 frv-asm.c:1343 ip2k-asm.c:758 ip2k-asm.c:762
+#: ip2k-asm.c:849 ip2k-asm.c:950 iq2000-asm.c:644 iq2000-asm.c:648
+#: iq2000-asm.c:735 iq2000-asm.c:836 m32r-asm.c:519 m32r-asm.c:523
+#: m32r-asm.c:610 m32r-asm.c:711 openrisc-asm.c:445 openrisc-asm.c:449
+#: openrisc-asm.c:536 openrisc-asm.c:637 xstormy16-asm.c:468
+#: xstormy16-asm.c:472 xstormy16-asm.c:559 xstormy16-asm.c:660
 msgid "unrecognized instruction"
 msgstr ""
 
-#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
-#: openrisc-asm.c:477 xstormy16-asm.c:517
+#: fr30-asm.c:554 frv-asm.c:1198 ip2k-asm.c:805 iq2000-asm.c:691
+#: m32r-asm.c:566 openrisc-asm.c:492 xstormy16-asm.c:515
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr ""
 
-#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
-#: openrisc-asm.c:487 xstormy16-asm.c:527
+#: fr30-asm.c:564 frv-asm.c:1208 ip2k-asm.c:815 iq2000-asm.c:701
+#: m32r-asm.c:576 openrisc-asm.c:502 xstormy16-asm.c:525
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr ""
 
-#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
-#: openrisc-asm.c:515 xstormy16-asm.c:555
+#: fr30-asm.c:592 frv-asm.c:1236 ip2k-asm.c:843 iq2000-asm.c:729
+#: m32r-asm.c:604 openrisc-asm.c:530 xstormy16-asm.c:553
 msgid "junk at end of line"
 msgstr ""
 
-#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
-#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662
+#: fr30-asm.c:698 frv-asm.c:1342 ip2k-asm.c:949 iq2000-asm.c:835
+#: m32r-asm.c:710 openrisc-asm.c:636 xstormy16-asm.c:659
 msgid "unrecognized form of instruction"
 msgstr ""
 
-#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
-#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674
+#: fr30-asm.c:710 frv-asm.c:1354 ip2k-asm.c:961 iq2000-asm.c:847
+#: m32r-asm.c:722 openrisc-asm.c:648 xstormy16-asm.c:671
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr ""
 
-#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
-#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677
+#: fr30-asm.c:713 frv-asm.c:1357 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:725 openrisc-asm.c:651 xstormy16-asm.c:674
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr ""
@@ -149,70 +156,70 @@ msgstr ""
 msgid "*unknown*"
 msgstr ""
 
-#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
-#: openrisc-dis.c:138 xstormy16-dis.c:171
+#: fr30-dis.c:319 frv-dis.c:388 ip2k-dis.c:328 iq2000-dis.c:191 m32r-dis.c:262
+#: openrisc-dis.c:137 xstormy16-dis.c:170
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
-#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#: fr30-ibld.c:168 frv-ibld.c:168 ip2k-ibld.c:168 iq2000-ibld.c:168
+#: m32r-ibld.c:168 openrisc-ibld.c:168 xstormy16-ibld.c:168
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr ""
 
-#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
-#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#: fr30-ibld.c:181 frv-ibld.c:181 ip2k-ibld.c:181 iq2000-ibld.c:181
+#: m32r-ibld.c:181 openrisc-ibld.c:181 xstormy16-ibld.c:181
 #, c-format
 msgid "operand out of range (%lu not between 0 and %lu)"
 msgstr ""
 
-#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
-#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#: fr30-ibld.c:732 frv-ibld.c:849 ip2k-ibld.c:609 iq2000-ibld.c:715
+#: m32r-ibld.c:667 openrisc-ibld.c:635 xstormy16-ibld.c:680
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
-#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#: fr30-ibld.c:939 frv-ibld.c:1159 ip2k-ibld.c:686 iq2000-ibld.c:892
+#: m32r-ibld.c:806 openrisc-ibld.c:737 xstormy16-ibld.c:828
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
-#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#: fr30-ibld.c:1088 frv-ibld.c:1431 ip2k-ibld.c:763 iq2000-ibld.c:1026
+#: m32r-ibld.c:922 openrisc-ibld.c:817 xstormy16-ibld.c:941
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
-#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#: fr30-ibld.c:1217 frv-ibld.c:1683 ip2k-ibld.c:820 iq2000-ibld.c:1140
+#: m32r-ibld.c:1018 openrisc-ibld.c:877 xstormy16-ibld.c:1034
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
-#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#: fr30-ibld.c:1351 frv-ibld.c:1944 ip2k-ibld.c:882 iq2000-ibld.c:1263
+#: m32r-ibld.c:1122 openrisc-ibld.c:946 xstormy16-ibld.c:1136
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
-#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#: fr30-ibld.c:1473 frv-ibld.c:2193 ip2k-ibld.c:932 iq2000-ibld.c:1374
+#: m32r-ibld.c:1214 openrisc-ibld.c:1003 xstormy16-ibld.c:1226
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr ""
 
-#: frv-asm.c:365
+#: frv-asm.c:688
 msgid "register number must be even"
 msgstr ""
 
-#: h8300-dis.c:377
+#: h8300-dis.c:358
 #, c-format
 msgid "Hmmmm 0x%x"
 msgstr ""
 
-#: h8300-dis.c:760
+#: h8300-dis.c:741
 #, c-format
 msgid "Don't understand 0x%x \n"
 msgstr ""
@@ -228,7 +235,7 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:1699
+#: i386-dis.c:1712
 msgid "<internal disassembler error>"
 msgstr ""
 
@@ -404,6 +411,7 @@ msgid "21-bit offset out of range"
 msgstr ""
 
 #: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
 msgid "missing `)'"
 msgstr ""
 
@@ -422,12 +430,12 @@ msgstr ""
 msgid "unknown\t0x%04x"
 msgstr ""
 
-#: m68k-dis.c:429
+#: m68k-dis.c:432
 #, c-format
 msgid "<internal error in opcode table: %s %s>\n"
 msgstr ""
 
-#: m68k-dis.c:1007
+#: m68k-dis.c:1025
 #, c-format
 msgid "<function code %d>"
 msgstr ""
@@ -437,47 +445,51 @@ msgstr ""
 msgid "# <dis error: %08x>"
 msgstr ""
 
-#: mips-dis.c:703
+#: mips-dis.c:709
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr ""
 
-#: mips-dis.c:746
+#: mips-dis.c:768
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr ""
 
-#: mips-dis.c:1004
+#: mips-dis.c:1026
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
 msgstr ""
 
-#: mips-dis.c:1755
+#: mips-dis.c:1777
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr ""
 
-#: mips-dis.c:1767
+#: mips-dis.c:1789
+#, c-format
 msgid ""
 "\n"
 "The following MIPS specific disassembler options are supported for use\n"
 "with the -M switch (multiple options should be separated by commas):\n"
 msgstr ""
 
-#: mips-dis.c:1771
+#: mips-dis.c:1793
+#, c-format
 msgid ""
 "\n"
 "  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1775
+#: mips-dis.c:1797
+#, c-format
 msgid ""
 "\n"
 "  fpr-names=ABI            Print FPR names according to specified ABI.\n"
 "                           Default: numeric.\n"
 msgstr ""
 
-#: mips-dis.c:1779
+#: mips-dis.c:1801
+#, c-format
 msgid ""
 "\n"
 "  cp0-names=ARCH           Print CP0 register names according to\n"
@@ -485,7 +497,8 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1784
+#: mips-dis.c:1806
+#, c-format
 msgid ""
 "\n"
 "  hwr-names=ARCH           Print HWR names according to specified \n"
@@ -493,32 +506,37 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1789
+#: mips-dis.c:1811
+#, c-format
 msgid ""
 "\n"
 "  reg-names=ABI            Print GPR and FPR names according to\n"
 "                           specified ABI.\n"
 msgstr ""
 
-#: mips-dis.c:1793
+#: mips-dis.c:1815
+#, c-format
 msgid ""
 "\n"
 "  reg-names=ARCH           Print CP0 register and HWR names according to\n"
 "                           specified architecture.\n"
 msgstr ""
 
-#: mips-dis.c:1797
+#: mips-dis.c:1819
+#, c-format
 msgid ""
 "\n"
 "  For the options above, the following values are supported for \"ABI\":\n"
 "   "
 msgstr ""
 
-#: mips-dis.c:1802 mips-dis.c:1810 mips-dis.c:1812
+#: mips-dis.c:1824 mips-dis.c:1832 mips-dis.c:1834
+#, c-format
 msgid "\n"
 msgstr ""
 
-#: mips-dis.c:1804
+#: mips-dis.c:1826
+#, c-format
 msgid ""
 "\n"
 "  For the options above, The following values are supported for \"ARCH\":\n"
@@ -551,86 +569,87 @@ msgstr ""
 #. * anyway!
 #.
 #: ns32k-dis.c:631
+#, c-format
 msgid "$<undefined>"
 msgstr ""
 
-#: ppc-opc.c:781 ppc-opc.c:809
+#: ppc-opc.c:791 ppc-opc.c:819
 msgid "invalid conditional option"
 msgstr ""
 
-#: ppc-opc.c:811
+#: ppc-opc.c:821
 msgid "attempt to set y bit when using + or - modifier"
 msgstr ""
 
-#: ppc-opc.c:840
+#: ppc-opc.c:849
 msgid "offset not a multiple of 16"
 msgstr ""
 
-#: ppc-opc.c:860
+#: ppc-opc.c:868
 msgid "offset not a multiple of 2"
 msgstr ""
 
-#: ppc-opc.c:862
+#: ppc-opc.c:870
 msgid "offset greater than 62"
 msgstr ""
 
-#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+#: ppc-opc.c:889 ppc-opc.c:934 ppc-opc.c:978
 msgid "offset not a multiple of 4"
 msgstr ""
 
-#: ppc-opc.c:883
+#: ppc-opc.c:891
 msgid "offset greater than 124"
 msgstr ""
 
-#: ppc-opc.c:902
+#: ppc-opc.c:910
 msgid "offset not a multiple of 8"
 msgstr ""
 
-#: ppc-opc.c:904
+#: ppc-opc.c:912
 msgid "offset greater than 248"
 msgstr ""
 
-#: ppc-opc.c:950
+#: ppc-opc.c:955
 msgid "offset not between -2048 and 2047"
 msgstr ""
 
-#: ppc-opc.c:973
+#: ppc-opc.c:976
 msgid "offset not between -8192 and 8191"
 msgstr ""
 
-#: ppc-opc.c:1011
+#: ppc-opc.c:1014
 msgid "ignoring invalid mfcr mask"
 msgstr ""
 
-#: ppc-opc.c:1059
+#: ppc-opc.c:1061
 msgid "ignoring least significant bits in branch offset"
 msgstr ""
 
-#: ppc-opc.c:1090 ppc-opc.c:1125
+#: ppc-opc.c:1091 ppc-opc.c:1126
 msgid "illegal bitmask"
 msgstr ""
 
-#: ppc-opc.c:1192
+#: ppc-opc.c:1191
 msgid "value out of range"
 msgstr ""
 
-#: ppc-opc.c:1262
+#: ppc-opc.c:1259
 msgid "index register in load range"
 msgstr ""
 
-#: ppc-opc.c:1279
+#: ppc-opc.c:1275
 msgid "source and target register operands must be different"
 msgstr ""
 
-#: ppc-opc.c:1294
+#: ppc-opc.c:1290
 msgid "invalid register operand when updating"
 msgstr ""
 
-#: ppc-opc.c:1335
+#: ppc-opc.c:1329
 msgid "target register operand must be even"
 msgstr ""
 
-#: ppc-opc.c:1350
+#: ppc-opc.c:1343
 msgid "source register operand must be even"
 msgstr ""
 
@@ -654,12 +673,12 @@ msgstr ""
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr ""
 
-#: v850-dis.c:221
+#: v850-dis.c:225
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr ""
 
-#: v850-dis.c:233
+#: v850-dis.c:237
 #, c-format
 msgid "unknown pop reg: %d\n"
 msgstr ""
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 76af4e7..4d48b9d 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -1,5 +1,5 @@
 /* ppc-dis.c -- Disassemble PowerPC instructions
-   Copyright 1994, 1995, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -191,9 +191,10 @@ print_insn_powerpc (bfd_vma memaddr,
 	continue;
 
       /* The instruction is valid.  */
-      (*info->fprintf_func) (info->stream, "%s", opcode->name);
       if (opcode->operands[0] != 0)
-	(*info->fprintf_func) (info->stream, "\t");
+	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
+      else
+	(*info->fprintf_func) (info->stream, "%s", opcode->name);
 
       /* Now extract and print the operands.  */
       need_comma = 0;
@@ -235,7 +236,8 @@ print_insn_powerpc (bfd_vma memaddr,
 	    }
 
 	  /* Print the operand as directed by the flags.  */
-	  if ((operand->flags & PPC_OPERAND_GPR) != 0)
+	  if ((operand->flags & PPC_OPERAND_GPR) != 0
+	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 	    (*info->fprintf_func) (info->stream, "r%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 	    (*info->fprintf_func) (info->stream, "f%ld", value);
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 9c65ff3..36fe454 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1,5 +1,5 @@
 /* ppc-opc.c -- PowerPC opcode list
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -362,34 +362,38 @@ const struct powerpc_operand powerpc_operands[] =
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 
-  /* The RA field in the DQ form lq instruction, which has special 
+  /* As above, but 0 in the RA field means zero, not r0.  */
+#define RA0 RA + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RA field in the DQ form lq instruction, which has special
      value restrictions.  */
-#define RAQ RA + 1
-  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+#define RAQ RA0 + 1
+  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */
 #define RAL RAQ + 1
-  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in an lmw instruction, which has special value
      restrictions.  */
 #define RAM RAL + 1
-  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in a D or X form instruction which is an updating
      store or an updating floating point load, which means that the RA
      field may not be zero.  */
 #define RAS RAM + 1
-  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field of the tlbwe instruction, which is optional.  */
-#define RAO RAS + 1
-  { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+#define RAOPT RAS + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
   /* The RB field in an X, XO, M, or MDS form instruction.  */
-#define RB RAO + 1
+#define RB RAOPT + 1
 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 
@@ -407,19 +411,19 @@ const struct powerpc_operand powerpc_operands[] =
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 
-  /* The RS field of the DS form stq instruction, which has special 
+  /* The RS field of the DS form stq instruction, which has special
      value restrictions.  */
 #define RSQ RS + 1
-  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RT field of the DQ form lq instruction, which has special
      value restrictions.  */
 #define RTQ RSQ + 1
-  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RS field of the tlbwe instruction, which is optional.  */
 #define RSO RTQ + 1
-  { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+  { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
   /* The SH field in an X or M form instruction.  */
 #define SH RSO + 1
@@ -1256,7 +1260,7 @@ insert_ram (unsigned long insn,
   return insn | ((value & 0x1f) << 16);
 }
 
-/* The RA field in the DQ form lq instruction, which has special 
+/* The RA field in the DQ form lq instruction, which has special
    value restrictions.  */
 
 static unsigned long
@@ -1326,7 +1330,7 @@ insert_rtq (unsigned long insn,
   return insn | ((value & 0x1f) << 21);
 }
 
-/* The RS field of the DS form stq instruction, which has special 
+/* The RS field of the DS form stq instruction, which has special
    value restrictions.  */
 
 static unsigned long
@@ -1478,11 +1482,11 @@ extract_tbr (unsigned long insn,
 
 /* An Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
-#define CTX_MASK       CTX(0x3f, 0x7)
+#define CTX_MASK CTX(0x3f, 0x7)
 
 /* An User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
-#define UCTX_MASK      UCTX(0x3f, 0x1f)
+#define UCTX_MASK UCTX(0x3f, 0x1f)
 
 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)
@@ -2373,16 +2377,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "li",	     OP(14),	DRA_MASK,	PPCCOM,		{ RT, SI } },
 { "lil",     OP(14),	DRA_MASK,	PWRCOM,		{ RT, SI } },
-{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
-{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
-{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
-{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA } },
+{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
+{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
+{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
+{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
 
 { "lis",     OP(15),	DRA_MASK,	PPCCOM,		{ RT, SISIGNOPT } },
 { "liu",     OP(15),	DRA_MASK,	PWRCOM,		{ RT, SISIGNOPT } },
-{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA,SISIGNOPT } },
-{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA,SISIGNOPT } },
-{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
+{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
+{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
+{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
 
 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDM } },
 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDP } },
@@ -3215,14 +3219,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfcr",    X(31,19),	XRARB_MASK,	NOPOWER4,	{ RT } },
 { "mfcr",    X(31,19),	XFXFXM_MASK,	POWER4,		{ RT, FXM4 } },
 
-{ "lwarx",   X(31,20),	X_MASK,		PPC,		{ RT, RA, RB } },
+{ "lwarx",   X(31,20),	X_MASK,		PPC,		{ RT, RA0, RB } },
 
-{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "icbt",    X(31,22),	X_MASK,		BOOKE,		{ CT, RA, RB } },
 { "icbt",    X(31,262),	XRT_MASK,	PPC403,		{ RA, RB } },
 
-{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lx",      X(31,23),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
 { "slw",     XRC(31,24,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
@@ -3246,7 +3250,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "icbte",   X(31,30),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
 
-{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,	{ OBF, RA, RB } },
 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
@@ -3308,15 +3312,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfmsr",   X(31,83),	XRARB_MASK,	COM,		{ RT } },
 
-{ "ldarx",   X(31,84),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "ldarx",   X(31,84),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "dcbf",    X(31,86),	XRT_MASK,	PPC,		{ RA, RB } },
 
-{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "dcbfe",   X(31,94),	XRT_MASK,	BOOKE64,	{ RA, RB } },
 
-{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "neg",     XO(31,104,0,0), XORB_MASK,	COM,		{ RT, RA } },
 { "neg.",    XO(31,104,0,1), XORB_MASK,	COM,		{ RT, RA } },
@@ -3339,7 +3343,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "not.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RBS } },
 { "nor.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RB } },
 
-{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "lbzuxe",  X(31,127),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
 
@@ -3372,16 +3376,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtmsr",   X(31,146),	XRARB_MASK,	COM,		{ RS } },
 
-{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA, RB } },
+{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA0, RB } },
 
-{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA, RB } },
+{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA0, RB } },
 
-{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA, RB } },
+{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
 { "stx",     X(31,151), X_MASK,		PWRCOM,		{ RS, RA, RB } },
 
-{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA, RB } },
+{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA0, RB } },
 
-{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "slq",     XRC(31,152,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "slq.",    XRC(31,152,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -3399,7 +3403,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
 
 { "stwux",   X(31,183),	X_MASK,		PPCCOM,		{ RS, RAS, RB } },
-{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
 { "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
 { "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
@@ -3426,9 +3430,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32,	{ SR, RS } },
 
-{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA, RB } },
+{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA0, RB } },
 
-{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "sllq",    XRC(31,216,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sllq.",   XRC(31,216,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -3436,7 +3440,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sleq",    XRC(31,217,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sleq.",   XRC(31,217,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "icblc",   X(31,230),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
 
@@ -3512,17 +3516,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbt",    X(31,278),	X_MASK,	PPC,			{ CT, RA, RB } },
 
-{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "eqv",     XRC(31,284,0), X_MASK,	COM,		{ RA, RS, RB } },
 { "eqv.",    XRC(31,284,1), X_MASK,	COM,		{ RA, RS, RB } },
 
 { "dcbte",   X(31,286),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
 
-{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
-{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA, RB } },
+{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA0, RB } },
 
 { "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
 
@@ -3619,9 +3623,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,	{ RT } },
 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, BOOKE,	{ RT } },
 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, BOOKE,	{ RT } },
 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, BOOKE,	{ RT } },
 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, BOOKE,	{ RT } },
 { "mftb",       X(31,371),	   X_MASK,    CLASSIC,	{ RT, TBR } },
 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,	{ RT } },
@@ -3764,14 +3772,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,	{ RT } },
 { "mfspr",      X(31,339),	   X_MASK,    COM,	{ RT, SPR } },
 
-{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "dst",     XDSS(31,342,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 { "dstt",    XDSS(31,342,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 
-{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA0, RB } },
 
-{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "dstst",   XDSS(31,374,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 { "dststt",  XDSS(31,374,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
@@ -3810,7 +3818,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmte",  X(31,402), XRA_MASK,	PPC64,		{ RS, RB } },
 
-{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "lfqx",    X(31,791),	X_MASK,		POWER2,		{ FRT, RA, RB } },
 
@@ -3826,7 +3834,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sradi",   XS(31,413,0), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
 { "sradi.",  XS(31,413,1), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
 
-{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "slbie",   X(31,434),	XRTRA_MASK,	PPC64,		{ RB } },
 
@@ -4094,13 +4102,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "clcs",    X(31,531), XRB_MASK,	M601,		{ RT, RA } },
 
-{ "lswx",    X(31,533),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lswx",    X(31,533),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lsx",     X(31,533),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
-{ "lwbrx",   X(31,534),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lwbrx",   X(31,534),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lbrx",    X(31,534),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
-{ "lfsx",    X(31,535),	X_MASK,		COM,		{ FRT, RA, RB } },
+{ "lfsx",    X(31,535),	X_MASK,		COM,		{ FRT, RA0, RB } },
 
 { "srw",     XRC(31,536,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
 { "sr",      XRC(31,536,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
@@ -4116,11 +4124,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "maskir",  XRC(31,541,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "maskir.", XRC(31,541,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "lwbrxe",  X(31,542),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwbrxe",  X(31,542),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
-{ "lfsxe",   X(31,543),	X_MASK,		BOOKE64,	{ FRT, RA, RB } },
+{ "lfsxe",   X(31,543),	X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
 
 { "bbelr",   X(31,550),	X_MASK,		PPCBRLK,	{ 0 }},
+
 { "tlbsync", X(31,566),	0xffffffff,	PPC,		{ 0 } },
 
 { "lfsux",   X(31,567),	X_MASK,		COM,		{ FRT, RAS, RB } },
@@ -4129,8 +4138,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsr",    X(31,595),	XRB_MASK|(1<<20), COM32,	{ RT, SR } },
 
-{ "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA, NB } },
-{ "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA, NB } },
+{ "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA0, NB } },
+{ "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA0, NB } },
 
 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,		{ 0 } },
 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,	{ 0 } },
@@ -4138,9 +4147,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sync",    X(31,598), XSYNC_MASK,	PPCCOM,		{ LS } },
 { "dcs",     X(31,598), 0xffffffff,	PWRCOM,		{ 0 } },
 
-{ "lfdx",    X(31,599), X_MASK,		COM,		{ FRT, RA, RB } },
+{ "lfdx",    X(31,599), X_MASK,		COM,		{ FRT, RA0, RB } },
 
-{ "lfdxe",   X(31,607), X_MASK,		BOOKE64,	{ FRT, RA, RB } },
+{ "lfdxe",   X(31,607), X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
 
 { "mfsri",   X(31,627), X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
@@ -4152,13 +4161,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsrin",  X(31,659), XRA_MASK,	PPC32,		{ RT, RB } },
 
-{ "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA, RB } },
-{ "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
+{ "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
-{ "stwbrx",  X(31,662), X_MASK,		PPCCOM,		{ RS, RA, RB } },
-{ "stbrx",   X(31,662), X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stwbrx",  X(31,662), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
+{ "stbrx",   X(31,662), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
-{ "stfsx",   X(31,663), X_MASK,		COM,		{ FRS, RA, RB } },
+{ "stfsx",   X(31,663), X_MASK,		COM,		{ FRS, RA0, RB } },
 
 { "srq",     XRC(31,664,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "srq.",    XRC(31,664,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4166,9 +4175,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sre",     XRC(31,665,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sre.",    XRC(31,665,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stwbrxe", X(31,670), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stwbrxe", X(31,670), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
-{ "stfsxe",  X(31,671), X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfsxe",  X(31,671), X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
 
 { "stfsux",  X(31,695),	X_MASK,		COM,		{ FRS, RAS, RB } },
 
@@ -4177,10 +4186,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfsuxe", X(31,703),	X_MASK,		BOOKE64,	{ FRS, RAS, RB } },
 
-{ "stswi",   X(31,725),	X_MASK,		PPCCOM,		{ RS, RA, NB } },
-{ "stsi",    X(31,725),	X_MASK,		PWRCOM,		{ RS, RA, NB } },
+{ "stswi",   X(31,725),	X_MASK,		PPCCOM,		{ RS, RA0, NB } },
+{ "stsi",    X(31,725),	X_MASK,		PWRCOM,		{ RS, RA0, NB } },
 
-{ "stfdx",   X(31,727),	X_MASK,		COM,		{ FRS, RA, RB } },
+{ "stfdx",   X(31,727),	X_MASK,		COM,		{ FRS, RA0, RB } },
 
 { "srlq",    XRC(31,728,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "srlq.",   XRC(31,728,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4188,7 +4197,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sreq",    XRC(31,729,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sreq.",   XRC(31,729,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stfdxe",  X(31,735),	X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfdxe",  X(31,735),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
 
 { "dcba",    X(31,758),	XRT_MASK,	PPC405 | BOOKE,	{ RA, RB } },
 
@@ -4204,7 +4213,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "tlbivax", X(31,786),	XRT_MASK,	BOOKE,		{ RA, RB } },
 { "tlbivaxe",X(31,787),	XRT_MASK,	BOOKE64,	{ RA, RB } },
 
-{ "lhbrx",   X(31,790),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhbrx",   X(31,790),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "sraw",    XRC(31,792,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
 { "sra",     XRC(31,792,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
@@ -4214,10 +4223,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "srad",    XRC(31,794,0), X_MASK,	PPC64,		{ RA, RS, RB } },
 { "srad.",   XRC(31,794,1), X_MASK,	PPC64,		{ RA, RS, RB } },
 
-{ "lhbrxe",  X(31,798),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhbrxe",  X(31,798),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
-{ "ldxe",    X(31,799),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
-{ "lduxe",   X(31,831),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "ldxe",    X(31,799),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
+{ "lduxe",   X(31,831),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "rac",     X(31,818),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
@@ -4243,7 +4252,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
 
-{ "sthbrx",  X(31,918),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "sthbrx",  X(31,918),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "sraq",    XRC(31,920,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sraq.",   XRC(31,920,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4256,9 +4265,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsh.",  XRC(31,922,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
 { "exts.",   XRC(31,922,1), XRB_MASK,	PWRCOM,		{ RA, RS } },
 
-{ "sthbrxe", X(31,926),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "sthbrxe", X(31,926),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
-{ "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,	PPC403,		{ RT, RA } },
@@ -4277,12 +4286,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
-{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAO, SHO } },
+{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAOPT, SHO } },
 { "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },
 
-{ "stfiwx",  X(31,983),	X_MASK,		PPC,		{ FRS, RA, RB } },
+{ "stfiwx",  X(31,983),	X_MASK,		PPC,		{ FRS, RA0, RB } },
 
 { "extsw",   XRC(31,986,0), XRB_MASK,	PPC64 | BOOKE64,{ RA, RS } },
 { "extsw.",  XRC(31,986,1), XRB_MASK,	PPC64,		{ RA, RS } },
@@ -4290,7 +4299,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "icread",  X(31,998),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
 
 { "icbie",   X(31,990),	XRT_MASK,	BOOKE64,	{ RA, RB } },
-{ "stfiwxe", X(31,991),	X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfiwxe", X(31,991),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
 
 { "tlbli",   X(31,1010), XRTRA_MASK,	PPC,		{ RB } },
 
@@ -4312,86 +4321,86 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stvx",    X(31, 231), X_MASK,	PPCVEC,		{ VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,	PPCVEC,		{ VS, RA, RB } },
 
-{ "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA } },
-{ "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
+{ "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
 { "lwzu",    OP(33),	OP_MASK,	PPCCOM,		{ RT, D, RAL } },
-{ "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
-{ "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lbzu",    OP(35),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA } },
-{ "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
+{ "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
 { "stwu",    OP(37),	OP_MASK,	PPCCOM,		{ RS, D, RAS } },
-{ "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
-{ "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA } },
+{ "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA0 } },
 
 { "stbu",    OP(39),	OP_MASK,	COM,		{ RS, D, RAS } },
 
-{ "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lhzu",    OP(41),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lhau",    OP(43),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA } },
+{ "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA0 } },
 
 { "sthu",    OP(45),	OP_MASK,	COM,		{ RS, D, RAS } },
 
 { "lmw",     OP(46),	OP_MASK,	PPCCOM,		{ RT, D, RAM } },
-{ "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
-{ "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA } },
-{ "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
+{ "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
-{ "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA } },
+{ "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA0 } },
 
 { "lfsu",    OP(49),	OP_MASK,	COM,		{ FRT, D, RAS } },
 
-{ "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA } },
+{ "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA0 } },
 
 { "lfdu",    OP(51),	OP_MASK,	COM,		{ FRT, D, RAS } },
 
-{ "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA } },
+{ "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA0 } },
 
 { "stfsu",   OP(53),	OP_MASK,	COM,		{ FRS, D, RAS } },
 
-{ "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA } },
+{ "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA0 } },
 
 { "stfdu",   OP(55),	OP_MASK,	COM,		{ FRS, D, RAS } },
 
 { "lq",      OP(56),	OP_MASK,	POWER4,		{ RTQ, DQ, RAQ } },
 
-{ "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA } },
+{ "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
-{ "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA } },
+{ "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
-{ "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lbzue",   DEO(58,1), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lhze",    DEO(58,2), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lhze",    DEO(58,2), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lhzue",   DEO(58,3), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lhae",    DEO(58,4), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lhae",    DEO(58,4), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lhaue",   DEO(58,5), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lwze",    DEO(58,6), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lwze",    DEO(58,6), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lwzue",   DEO(58,7), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "stbe",    DEO(58,8), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "stbe",    DEO(58,8), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "stbue",   DEO(58,9), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
-{ "sthe",    DEO(58,10), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "sthe",    DEO(58,10), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "sthue",   DEO(58,11), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
-{ "stwe",    DEO(58,14), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "stwe",    DEO(58,14), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "stwue",   DEO(58,15), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
 
-{ "ld",      DSO(58,0),	DS_MASK,	PPC64,		{ RT, DS, RA } },
+{ "ld",      DSO(58,0),	DS_MASK,	PPC64,		{ RT, DS, RA0 } },
 
 { "ldu",     DSO(58,1), DS_MASK,	PPC64,		{ RT, DS, RAL } },
 
-{ "lwa",     DSO(58,2), DS_MASK,	PPC64,		{ RT, DS, RA } },
+{ "lwa",     DSO(58,2), DS_MASK,	PPC64,		{ RT, DS, RA0 } },
 
 { "fdivs",   A(59,18,0), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
 { "fdivs.",  A(59,18,1), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
@@ -4427,24 +4436,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfqu",   OP(61),	OP_MASK,	POWER2,		{ FRS, D, RA } },
 
-{ "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA } },
-{ "ldue",    DEO(62,1), DE_MASK,	BOOKE64,	{ RT, DES, RA } },
-{ "lfse",    DEO(62,4), DE_MASK,	BOOKE64,	{ FRT, DES, RA } },
+{ "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
+{ "ldue",    DEO(62,1), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
+{ "lfse",    DEO(62,4), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
 { "lfsue",   DEO(62,5), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
-{ "lfde",    DEO(62,6), DE_MASK,	BOOKE64,	{ FRT, DES, RA } },
+{ "lfde",    DEO(62,6), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
 { "lfdue",   DEO(62,7), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
-{ "stde",    DEO(62,8), DE_MASK,	BOOKE64,	{ RS, DES, RA } },
+{ "stde",    DEO(62,8), DE_MASK,	BOOKE64,	{ RS, DES, RA0 } },
 { "stdue",   DEO(62,9), DE_MASK,	BOOKE64,	{ RS, DES, RAS } },
-{ "stfse",   DEO(62,12), DE_MASK,	BOOKE64,	{ FRS, DES, RA } },
+{ "stfse",   DEO(62,12), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
 { "stfsue",  DEO(62,13), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
-{ "stfde",   DEO(62,14), DE_MASK,	BOOKE64,	{ FRS, DES, RA } },
+{ "stfde",   DEO(62,14), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
 { "stfdue",  DEO(62,15), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
 
-{ "std",     DSO(62,0),	DS_MASK,	PPC64,		{ RS, DS, RA } },
+{ "std",     DSO(62,0),	DS_MASK,	PPC64,		{ RS, DS, RA0 } },
 
 { "stdu",    DSO(62,1),	DS_MASK,	PPC64,		{ RS, DS, RAS } },
 
-{ "stq",     DSO(62,2),	DS_MASK,	POWER4,		{ RSQ, DS, RA } },
+{ "stq",     DSO(62,2),	DS_MASK,	POWER4,		{ RSQ, DS, RA0 } },
 
 { "fcmpu",   X(63,0),	X_MASK|(3<<21),	COM,		{ BF, FRA, FRB } },
 
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 2512f96..840823e 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble SH instructions.
-   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -433,8 +433,10 @@ print_insn_sh (memaddr, info)
     case bfd_mach_sh3e:
       target_arch = arch_sh3e;
       break;
-    case bfd_mach_sh4:
     case bfd_mach_sh4_nofpu:
+      target_arch = arch_sh4_nofpu;
+      break;
+    case bfd_mach_sh4:
       target_arch = arch_sh4;
       break;
     case bfd_mach_sh4a:
@@ -444,6 +446,9 @@ print_insn_sh (memaddr, info)
     case bfd_mach_sh4al_dsp:
       target_arch = arch_sh4al_dsp;
       break;
+    case bfd_mach_sh4_nommu_nofpu:
+      target_arch = arch_sh4_nommu_nofpu;
+      break;
     case bfd_mach_sh5:
 #ifdef INCLUDE_SHMEDIA
       status = print_insn_sh64 (memaddr, info);
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index 0ef1fab..a1877b3 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -1,5 +1,5 @@
 /* Definitions for SH opcodes.
-   Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003
+   Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -188,12 +188,13 @@ sh_dsp_reg_nums;
 #define arch_sh4al_dsp 0x0400
 #define arch_sh4_nofpu 0x1000
 #define arch_sh4a_nofpu 0x2000
+#define arch_sh4_nommu_nofpu 0x4000  /* no mmu nor fpu */
 
 #define arch_sh1_up  (arch_sh1 | arch_sh2_up)
 #define arch_sh2_up  (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
 #define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
 #define arch_sh3_up  (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
-		      | arch_sh4_nofp_up)
+		      | arch_sh4_nommu_nofpu_up)
 #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
 #define arch_sh4_up  (arch_sh4 | arch_sh4a_up)
 #define arch_sh4a_up (arch_sh4a)
@@ -202,9 +203,14 @@ sh_dsp_reg_nums;
 #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
 #define arch_sh4al_dsp_up (arch_sh4al_dsp)
 
+#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
+
 #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
 #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
 
+#define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
+	| arch_sh4_nofp_up)  /* arch _sh3_up omitting arch_sh4_nommu_nofpu */
+
 typedef struct
 {
   char *name;
@@ -297,6 +303,8 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
 
+/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
+
 /* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
 
 /* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
@@ -309,7 +317,7 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up},
 
-/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
+/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up},
 
@@ -319,6 +327,8 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
 
+/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
+
 /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
 
 /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
@@ -329,7 +339,7 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up},
 
-/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up},
+/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
 
@@ -384,7 +394,7 @@ const sh_opcode_info sh_table[] =
   
 /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
 
-/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
+/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh_any_with_mmu},
 
 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
 
@@ -457,7 +467,7 @@ const sh_opcode_info sh_table[] =
 /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
 
 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
-/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
 /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
@@ -482,11 +492,11 @@ const sh_opcode_info sh_table[] =
 /* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
 
 /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
-/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 
 /* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
@@ -495,7 +505,7 @@ const sh_opcode_info sh_table[] =
 
 /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
 
-/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
 
@@ -567,9 +577,9 @@ const sh_opcode_info sh_table[] =
 
 /* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up},
 
-/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up},
+/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
+/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up},
 
@@ -589,9 +599,9 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
 
-/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up},
+/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
 
-/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up},
+/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up},
 
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index c68df38..6f360c6 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -1,6 +1,6 @@
 /* Print SPARC instructions.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2002, 2003 Free Software Foundation, Inc.
+   2000, 2002, 2003, 2004 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -224,7 +224,7 @@ print_insn_sparc (memaddr, info)
   static int opcodes_initialized = 0;
   /* bfd mach number of last call.  */
   static unsigned long current_mach = 0;
-  bfd_vma (*getword) PARAMS ((const unsigned char *));
+  bfd_vma (*getword) (const void *);
 
   if (!opcodes_initialized
       || info->mach != current_mach)