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| author | Alan Modra <amodra@gmail.com> | 2010-08-06 03:59:49 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2010-08-06 03:59:49 +0000 |
| commit | 6ca4eb778968d5300583213b4ebe153c7eaad6f5 (patch) | |
| tree | 13d6b8b1b0827451b755aba830c1fb8e4d454205 /opcodes | |
| parent | 1e0061d22e6a7cccc3b590c3cac3a8ae00b1437d (diff) | |
| download | gdb-6ca4eb778968d5300583213b4ebe153c7eaad6f5.zip gdb-6ca4eb778968d5300583213b4ebe153c7eaad6f5.tar.gz gdb-6ca4eb778968d5300583213b4ebe153c7eaad6f5.tar.bz2 | |
* disassemble.c: Formatting.
(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 16 |
2 files changed, 14 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 13b5b52..8190fb7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2010-08-06 Alan Modra <amodra@gmail.com> + + * disassemble.c: Formatting. + (disassemble_init_for_target <ARCH_m32c>): Comment on endian. + 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. @@ -16,7 +21,7 @@ (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov r0,r0) and NOP3 (max r0,r0) special cases. * rx-decode.c: Regenerate. - + 2010-07-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Add 0F to VEX opcode enums. diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index b0cb4e3..0fb35ac 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -114,10 +114,8 @@ disassembler (abfd) #endif #ifdef ARCH_arc case bfd_arch_arc: - { - disassemble = arc_get_disassembler (abfd); - break; - } + disassemble = arc_get_disassembler (abfd); + break; #endif #ifdef ARCH_arm case bfd_arch_arm: @@ -317,9 +315,9 @@ disassembler (abfd) #ifdef ARCH_or32 case bfd_arch_or32: if (bfd_big_endian (abfd)) - disassemble = print_insn_big_or32; + disassemble = print_insn_big_or32; else - disassemble = print_insn_little_or32; + disassemble = print_insn_little_or32; break; #endif #ifdef ARCH_pdp11 @@ -361,9 +359,9 @@ disassembler (abfd) #ifdef ARCH_score case bfd_arch_score: if (bfd_big_endian (abfd)) - disassemble = print_insn_big_score; + disassemble = print_insn_big_score; else - disassemble = print_insn_little_score; + disassemble = print_insn_little_score; break; #endif #ifdef ARCH_sh @@ -530,6 +528,8 @@ disassemble_init_for_target (struct disassemble_info * info) #endif #ifdef ARCH_m32c case bfd_arch_m32c: + /* This processor in fact is little endian. The value set here + reflects the way opcodes are written in the cgen description. */ info->endian = BFD_ENDIAN_BIG; if (! info->insn_sets) { |