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| author | Adam Nemet <anemet@caviumnetworks.com> | 2009-02-18 20:51:59 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@caviumnetworks.com> | 2009-02-18 20:51:59 +0000 |
| commit | b1c9882d1b9f182538c9babb35fe11d152708fe0 (patch) | |
| tree | 5c370618947dbb2571b223bb9dca2797f03e65ca /opcodes | |
| parent | 134eb42cf4b2b8363c5e93bac14b4903170880c2 (diff) | |
| download | gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.zip gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.tar.gz gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.tar.bz2 | |
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
dmfc2 and dmtc2 before the architecture-level variants.
gas/testsuite/
* gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2.
* gas/mips/octeon.d: Update.
* gas/mips/octeon-ill.l: Update error message.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 941aff1..db66f45 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-02-18 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific + dmfc2 and dmtc2 before the architecture-level variants. + 2009-02-18 Pierre Muller <muller@ics.u-strasbg.fr> * fr30-opc.c: Regenerate. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 12a8cbe..fdf90ae 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1506,12 +1506,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, -{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, +{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, -{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, |