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authorMichael Eager <eager@eagercon.com>2012-11-29 21:09:01 +0000
committerMichael Eager <eager@eagercon.com>2012-11-29 21:09:01 +0000
commit94dda8b768b96328d755a95ca10c77f3860519b9 (patch)
tree4d5f4b2ac1e3721ecbb540a94d18210899e9189c /opcodes
parent4983028c3a5e15579946e69ab63db20d1dd78a79 (diff)
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opcodes/Changelog:
* microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL * microblaze-dis.c (print_insn_microblaze): Same. gas/Changelog * gas/config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/microblaze-dis.c4
-rw-r--r--opcodes/microblaze-opc.h10
3 files changed, 13 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8a4634d..c367b15 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2012-11-29 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
+ INST_TYPE_R1_R2_SPECIAL
+ * microblaze-dis.c (print_insn_microblaze): Same.
+
2012-11-23 Alan Modra <amodra@gmail.com>
* ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index 7e3a546..bf028c4 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -383,8 +383,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
case INST_TYPE_R1:
print_func (stream, "\t%s", get_field_r1 (inst));
break;
- case INST_TYPE_RD_R1_SPECIAL:
- print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
+ case INST_TYPE_R1_R2_SPECIAL:
+ print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
break;
case INST_TYPE_RD_IMM15:
print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 404985b..e9da12a 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -45,7 +45,7 @@
#define INST_TYPE_R1_RFSL 15
/* New insn type for insn cache. */
-#define INST_TYPE_RD_R1_SPECIAL 16
+#define INST_TYPE_R1_R2_SPECIAL 16
/* New insn type for msrclr, msrset insns. */
#define INST_TYPE_RD_IMM15 17
@@ -171,10 +171,10 @@ struct op_code_struct
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
- {"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
- {"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
- {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
- {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },