Fix failures in the GAS testsuite for the ARC architecture.

gas	* config/tc-arc.c (arc_option): Sets all internal gas options when
	parsing .cpu directive.
	(declare_register_set): Declare all 64 registers.
	(md_section_align): Refactor.
	(md_pcrel_from_section): Remove assert.
	(pseudo_operand_match): Fix pseudo operand match.
	(find_reloc): Use flags filed, extend matching.
	* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
	relocation.

testsuite	* gas/arc/bic.d: Update test.
	* gas/arc/add_s-err.s: New file.
	* gas/arc/cpu-warn1.s: Likewise.
	* gas/arc/pcl-relocs.d: Likewise.
	* gas/arc/pcl-relocs.s: Likewise.
	* gas/arc/pcrel-relocs.d: Likewise.
	* gas/arc/pcrel-relocs.s: Likewise.
	* gas/arc/pic-relocs.d: Likewise.
	* gas/arc/pic-relocs.s: Likewise.
	* gas/arc/plt-relocs.d: Likewise.
	* gas/arc/plt-relocs.s: Likewise.
	* gas/arc/pseudos.d: Likewise.
	* gas/arc/pseudos.s: Likewise.
	* gas/arc/sda-relocs.d: Likewise.
	* gas/arc/sda-relocs.s: Likewise.
	* gas/arc/sda-relocs2.d: Likewise.
	* gas/arc/sda-relocs2.s: Likewise.
	* gas/arc/tls-relocs.d: Likewise.
	* gas/arc/tls-relocs.s: Likewise.

opcode	* arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].

opcodes	* arc-dis.c (special_flag_p): Match full mnemonic.
	* arc-opc.c (print_insn_arc): Check section size to read
	appropriate number of bytes. Fix printing.
	* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
	arguments.

4 files changed, 162 insertions, 106 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7b097f3..7c99b06 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-dis.c (special_flag_p): Match full mnemonic.
+	* arc-opc.c (print_insn_arc): Check section size to read
+	appropriate number of bytes. Fix printing.
+	* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
+	arguments.
+
 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	* arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 6319d8a..b781daf 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -82,15 +82,13 @@ special_flag_p (const char *opname,
 		const char *flgname)
 {
   const struct arc_flag_special *flg_spec;
-  size_t len;
   unsigned i, j, flgidx;
 
   for (i = 0; i < arc_num_flag_special; i++)
     {
       flg_spec = &arc_flag_special_cases[i];
-      len = strlen (flg_spec->name);
 
-      if (strncmp (opname, flg_spec->name, len) != 0)
+      if (strcmp (opname, flg_spec->name))
 	continue;
 
       /* Found potential special case instruction.  */
@@ -127,7 +125,7 @@ print_insn_arc (bfd_vma memaddr,
   int flags;
   bfd_boolean need_comma;
   bfd_boolean open_braket;
-
+  int size;
 
   lowbyte  = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
   highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
@@ -148,8 +146,46 @@ print_insn_arc (bfd_vma memaddr,
       break;
     }
 
+  /* This variable may be set by the instruction decoder.  It suggests
+     the number of bytes objdump should display on a single line.  If
+     the instruction decoder sets this, it should always set it to
+     the same value in order to get reasonable looking output.  */
+
+  info->bytes_per_line  = 8;
+
+  /* In the next lines, we set two info variables control the way
+     objdump displays the raw data.  For example, if bytes_per_line is
+     8 and bytes_per_chunk is 4, the output will look like this:
+     00:   00000000 00000000
+     with the chunks displayed according to "display_endian".  */
+
+  if (info->section
+      && !(info->section->flags & SEC_CODE))
+    {
+      /* This is not a CODE section.  */
+      switch (info->section->size)
+	{
+	case 1:
+	case 2:
+	case 4:
+	  size = info->section->size;
+	  break;
+	default:
+	  size = (info->section->size & 0x01) ? 1 : 4;
+	  break;
+	}
+      info->bytes_per_chunk = 1;
+      info->display_endian = info->endian;
+    }
+  else
+    {
+      size = 2;
+      info->bytes_per_chunk = 2;
+      info->display_endian = info->endian;
+    }
+
   /* Read the insn into a host word.  */
-  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+  status = (*info->read_memory_func) (memaddr, buffer, size, info);
   if (status != 0)
     {
       (*info->memory_error_func) (status, memaddr, info);
@@ -159,20 +195,29 @@ print_insn_arc (bfd_vma memaddr,
   if (info->section
       && !(info->section->flags & SEC_CODE))
     {
-      /* Sort of data section, just print a 32 bit number.  */
-      insnLen = 4;
-      status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
-      if (status != 0)
+      /* Data section.  */
+      unsigned long data;
+
+      data = bfd_get_bits (buffer, size * 8,
+			   info->display_endian == BFD_ENDIAN_BIG);
+      switch (size)
 	{
-	  (*info->memory_error_func) (status, memaddr + 2, info);
-	  return -1;
+	case 1:
+	  (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
+	  break;
+	case 2:
+	  (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
+	  break;
+	case 4:
+	  (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
+	  break;
+	default:
+	  abort ();
 	}
-      insn[0] = ARRANGE_ENDIAN (info, buffer);
-      (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
-      return insnLen;
+      return size;
     }
 
-  if ((((buffer[lowbyte] & 0xf8) > 0x38)
+  if (   (((buffer[lowbyte] & 0xf8) > 0x38)
        && ((buffer[lowbyte] & 0xf8) != 0x48))
       || ((info->mach == bfd_mach_arc_arcv2)
 	  && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly.  */
@@ -196,20 +241,6 @@ print_insn_arc (bfd_vma memaddr,
       insn[0] = ARRANGE_ENDIAN (info, buffer);
     }
 
-  /* This variable may be set by the instruction decoder.  It suggests
-     the number of bytes objdump should display on a single line.  If
-     the instruction decoder sets this, it should always set it to
-     the same value in order to get reasonable looking output.  */
-  info->bytes_per_line  = 8;
-
-  /* The next two variables control the way objdump displays the raw data.
-     For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the
-     output will look like this:
-     00:   00000000 00000000
-     with the chunks displayed according to "display_endian".  */
-  info->bytes_per_chunk = 2;
-  info->display_endian  = info->endian;
-
   /* Set some defaults for the insn info.  */
   info->insn_info_valid    = 1;
   info->branch_delay_insns = 0;
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index db11a1f..fe0c828 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1240,38 +1240,52 @@ const struct arc_flag_special arc_flag_special_cases[] =
 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
 
 /* Relocations.  */
-#undef DEF
-#define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2)	\
-  { #NAME, EXC1, EXC2, RELOC1, RELOC2}
-
 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
 {
-  DEF (sda, "ld", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
-  DEF (sda, "st", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
-  DEF (sda, "ldw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
-  DEF (sda, "ldh", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
-  DEF (sda, "stw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
-  DEF (sda, "sth", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
+  { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+  { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+  { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+  { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+
+  /* Next two entries will cover the undefined behavior ldb/stb with
+     address scaling.  */
+  { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+  { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
+
+  { "sda", "ld", { F_ASFAKE, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+  { "sda", "st", { F_ASFAKE, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+  { "sda", "ldd", { F_ASFAKE, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+  { "sda", "std", { F_ASFAKE, F_NULL },
+    BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
 
   /* Short instructions.  */
-  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD),
-  DEF (sda, 0, F_NULL, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1),
-  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2),
-  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2),
-
-  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME),
-  DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST),
-
-  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25H_PCREL,
-       BFD_RELOC_ARC_S25H_PCREL_PLT),
-  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21H_PCREL,
-       BFD_RELOC_ARC_S21H_PCREL_PLT),
-  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25W_PCREL,
-       BFD_RELOC_ARC_S25W_PCREL_PLT),
-  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21W_PCREL,
-       BFD_RELOC_ARC_S21W_PCREL_PLT),
-
-  DEF (plt, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32),
+  { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
+  { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
+  { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
+  { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
+
+  { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
+  { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+
+  { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
+    BFD_RELOC_ARC_S25H_PCREL_PLT },
+  { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
+    BFD_RELOC_ARC_S21H_PCREL_PLT },
+  { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
+    BFD_RELOC_ARC_S25W_PCREL_PLT },
+  { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
+    BFD_RELOC_ARC_S21W_PCREL_PLT },
+
+  { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
 };
 
 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 78e5b51..1b4715d 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -1871,10 +1871,10 @@
 { "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brk  00100101011011110000000000111111.  */
-{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* brk_s  0111111111111111.  */
-{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100.  */
 { "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
@@ -2272,12 +2272,12 @@
 /* clri c 00100111001011110000CCCCCC111111.  */
 { "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
 
-/* clri 0 00100111001011110000111110111111.  */
-{ "clri", 0x272F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { ZA }, { 0 }},
-
 /* clri u6 00100111011011110000uuuuuu111111.  */
 { "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
 
+/* clri 00100111011011110000uuuuuu111111.  */
+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+
 /* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA.  */
 { "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
 
@@ -6179,7 +6179,7 @@
 { "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* dsync  00100010011011110001RRRRRR111111.  */
-{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
 
 /* ei_s u10 010111uuuuuuuuuu.  */
 { "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }},
@@ -7761,100 +7761,100 @@
 { "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
 
 /* invld042e  00100RRRRR101110RRRRRRRRRRRRRRRR.  */
-{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f0e  00100RRRRR101111RRRRRRRRRR00111R.  */
-{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f12  00100RRRRR101111RRRRRRRRRR01001R.  */
-{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f14  00100RRRRR101111RRRRRRRRRR0101RR.  */
-{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f18  00100RRRRR101111RRRRRRRRRR011RRR.  */
-{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f20  00100RRRRR101111RRRRRRRRRR10RRRR.  */
-{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f30  00100RRRRR101111RRRRRRRRRR110RRR.  */
-{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f38  00100RRRRR101111RRRRRRRRRR1110RR.  */
-{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f3c  00100RRRRR101111RRRRRRRRRR11110R.  */
-{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f3e  00100RRRRR101111RRRRRRRRRR111110.  */
-{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f3f08  00100RRRRR101111R001RRRRRR111111.  */
-{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f3f10  00100RRRRR101111R01RRRRRRR111111.  */
-{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld042f3f20  00100RRRRR101111R1RRRRRRRR111111.  */
-{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld0506  00101RRRRR00011RRRRRRRRRRRRRRRRR.  */
-{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld050a  00101RRRRR00101RRRRRRRRRRRRRRRRR.  */
-{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld050c  00101RRRRR00110RRRRRRRRRRRRRRRRR.  */
-{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld051e  00101RRRRR01111RRRRRRRRRRRRRRRRR.  */
-{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld0520  00101RRRRR100RRRRRRRRRRRRRRRRRRR.  */
-{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld0528  00101RRRRR1010RRRRRRRRRRRRRRRRRR.  */
-{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052c  00101RRRRR10110RRRRRRRRRRRRRRRRR.  */
-{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052e  00101RRRRR101110RRRRRRRRRRRRRRRR.  */
-{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f02  00101RRRRR101111RRRRRRRRRR00001R.  */
-{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f04  00101RRRRR101111RRRRRRRRRR0001RR.  */
-{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f14  00101RRRRR101111RRRRRRRRRR0101RR.  */
-{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f18  00101RRRRR101111RRRRRRRRRR011RRR.  */
-{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f20  00101RRRRR101111RRRRRRRRRR10RRRR.  */
-{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f30  00101RRRRR101111RRRRRRRRRR110RRR.  */
-{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f38  00101RRRRR101111RRRRRRRRRR1110RR.  */
-{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f3c  00101RRRRR101111RRRRRRRRRR11110R.  */
-{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f3e  00101RRRRR101111RRRRRRRRRR111110.  */
-{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld052f3f00  00101RRRRR101111RRRRRRRRRR111111.  */
-{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* invld07  00111RRRRRRRRRRRRRRRRRRRRRRRRRRR.  */
-{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, {  }, { 0 }},
+{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
 /* j c 00100RRR001000000RRRCCCCCCRRRRRR.  */
 { "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
@@ -12790,10 +12790,10 @@
 { "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
 
 /* nop  00100110010010100111000000000000.  */
-{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
 
 /* nop_s  0111100011100000.  */
-{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
 
 /* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001.  */
 { "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
@@ -13768,7 +13768,7 @@
 { "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* rtie  00100100011011110000000000111111.  */
-{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* rtsc b,0 00110bbb01101111RBBB000000011010.  */
 { "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, ZB }, { 0 }},
@@ -13909,13 +13909,13 @@
 { "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011.  */
-{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_DI16 }},
+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011.  */
-{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_DI16 }},
+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
 
 /* scondd<.di> b,limm 00100bbb00101111DBBB111110010011.  */
-{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_DI16 }},
+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
 
 /* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA.  */
 { "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
@@ -14226,6 +14226,9 @@
 /* seti limm 00100110001011110000111110111111.  */
 { "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
 
+/* seti 00100110011011110000uuuuuu111111.  */
+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+
 /* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA.  */
 { "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
 
@@ -15196,19 +15199,19 @@
 { "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
 
 /* swi  00100010011011110000000000111111.  */
-{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* swi_s  0111101011100000.  */
-{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* swi_s u6 01111uuuuuu11111.  */
 { "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
 
 /* sync  00100011011011110000000000111111.  */
-{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, {  }, { 0 }},
+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
 
 /* trap0  00100010011011110000000000111111.  */
-{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, {  }, { 0 }},
+{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }},
 
 /* trap_s u6 01111uuuuuu11110.  */
 { "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
@@ -15277,7 +15280,7 @@
 { "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
 
 /* unimp_s  0111100111100000.  */
-{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, {  }, { 0 }},
+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA.  */
 { "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},