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| author | Thiemo Seufer <ths@networkno.de> | 2006-04-28 13:17:00 +0000 |
|---|---|---|
| committer | Thiemo Seufer <ths@networkno.de> | 2006-04-28 13:17:00 +0000 |
| commit | 59c455b37c55a418e95b0ff4d7c23b1f63c7dae3 (patch) | |
| tree | 4bf08a2393a74ac7d9988be56a8c17b9e5a29fca /opcodes | |
| parent | cc0ca239ed9261e5a45680c89ab3dd5cbd455f90 (diff) | |
| download | gdb-59c455b37c55a418e95b0ff4d7c23b1f63c7dae3.zip gdb-59c455b37c55a418e95b0ff4d7c23b1f63c7dae3.tar.gz gdb-59c455b37c55a418e95b0ff4d7c23b1f63c7dae3.tar.bz2 | |
[ opcodes/ChangeLog ]
2006-04-28 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
Nigel Stevens <nigel@mips.com>
* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
names.
[ gas/testsuite/ChangeLog ]
2006-04-28 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
Nigel Stevens <nigel@mips.com>
* gas/mips/cp0sel-names-mips32r2.d,
gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 21 |
2 files changed, 28 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f9c0619..8352f24 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,11 @@ 2006-04-28 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + Nigel Stevens <nigel@mips.com> + + * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register + names. + +2006-04-28 Thiemo Seufer <ths@mips.com> Nigel Stevens <nigel@mips.com> David Ung <davidu@mips.com> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index e8a083b..0e785cb 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -184,7 +184,28 @@ static const char * const mips_cp0_names_mips3264r2[32] = static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { { 4, 1, "c0_contextconfig" }, + { 0, 1, "c0_mvpcontrol" }, + { 0, 2, "c0_mvpconf0" }, + { 0, 3, "c0_mvpconf1" }, + { 1, 1, "c0_vpecontrol" }, + { 1, 2, "c0_vpeconf0" }, + { 1, 3, "c0_vpeconf1" }, + { 1, 4, "c0_yqmask" }, + { 1, 5, "c0_vpeschedule" }, + { 1, 6, "c0_vpeschefback" }, + { 2, 1, "c0_tcstatus" }, + { 2, 2, "c0_tcbind" }, + { 2, 3, "c0_tcrestart" }, + { 2, 4, "c0_tchalt" }, + { 2, 5, "c0_tccontext" }, + { 2, 6, "c0_tcschedule" }, + { 2, 7, "c0_tcschefback" }, { 5, 1, "c0_pagegrain" }, + { 6, 1, "c0_srsconf0" }, + { 6, 2, "c0_srsconf1" }, + { 6, 3, "c0_srsconf2" }, + { 6, 4, "c0_srsconf3" }, + { 6, 5, "c0_srsconf4" }, { 12, 1, "c0_intctl" }, { 12, 2, "c0_srsctl" }, { 12, 3, "c0_srsmap" }, |