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| author | Jim Wilson <jimw@sifive.com> | 2021-09-08 18:15:39 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2021-09-08 18:23:30 -0700 |
| commit | c7dee84894df6231bb7fce34cf36242c34d7f891 (patch) | |
| tree | a5127cce4214f892f3c152da6c7d53c52ff89b9f /opcodes | |
| parent | d0d2fb0a25517c39ecdec504c7a9a7943247cd86 (diff) | |
| download | gdb-c7dee84894df6231bb7fce34cf36242c34d7f891.zip gdb-c7dee84894df6231bb7fce34cf36242c34d7f891.tar.gz gdb-c7dee84894df6231bb7fce34cf36242c34d7f891.tar.bz2 | |
RISC-V: Pretty print values formed with lui and addiw.
The disassembler has support to pretty print values created by an lui/addi
pair, but there is no support for addiw. There is also no support for
c.addi and c.addiw. This patch extends the pretty printing support to
handle these 3 instructions in addition to addi. Existing testcases serve
as tests for the new feature.
opcodes/
* riscv-dis.c (maybe_print_address): New arg wide. Sign extend when
wide is true.
(print_insn_args): Fix calls to maybe_print_address. Add checks for
c.addi, c.addiw, and addiw, and call maybe_print_address for them.
gas/
* testsuite/gas/riscv/insn.d: Update for disassembler change.
* testsuite/gas/li32.d, testsuite/gas/li64.d: Likwise.
* testsuite/gas/lla64.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 171aea2..57198c7 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -156,7 +156,8 @@ arg_print (struct disassemble_info *info, unsigned long val, } static void -maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) +maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, + int wide) { if (pd->hi_addr[base_reg] != (bfd_vma)-1) { @@ -167,6 +168,10 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) pd->print_addr = pd->gp + offset; else if (base_reg == X_TP || base_reg == 0) pd->print_addr = offset; + + /* Sign-extend a 32-bit value to a 64-bit value. */ + if (wide) + pd->print_addr = (bfd_vma)(int32_t) pd->print_addr; } /* Print insn arguments for 32/64-bit code. */ @@ -211,6 +216,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) break; case 'o': case 'j': + if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); + if (info->mach == bfd_mach_riscv64 + && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l)); break; case 'k': @@ -283,7 +293,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) case 'b': case 's': if ((l & MASK_JALR) == MATCH_JALR) - maybe_print_address (pd, rs1, 0); + maybe_print_address (pd, rs1, 0, 0); print (info->stream, "%s", riscv_gpr_names[rs1]); break; @@ -313,17 +323,20 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) break; case 'o': - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); /* Fall through. */ case 'j': if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) || (l & MASK_JALR) == MATCH_JALR) - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); + if (info->mach == bfd_mach_riscv64 + && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); break; case 'q': - maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); + maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0); print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); break; |