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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-20 15:32:15 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | 5517af829887ba3b19a3f372b6b60e8098bdfa29 (patch) | |
| tree | 920b57119a6b6b1662da63f8916550a5ba35adfe /opcodes | |
| parent | 3521a28f10900ed893f53fcceec2f66c335cb154 (diff) | |
| download | gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.zip gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.tar.gz gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.tar.bz2 | |
aarch64: Apply narrowing of allowed immediate values for SYSP
While CRn and CRm fields in the SYSP instruction are 4-bit wide and
are thus able to accommodate values in the range 0-15, the
specifications for the SYSP instructions limit their ranges to 8-9 for
CRm and 0-7 in the case of CRn.
This led to the need to signal in some way to the operand parser that
a given operand is under special restrictions regarding its use. This
is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the
range of operand values for fields in the instruction tagged with the
flag.
The flag is then used in `parse_operands' when the instruction is
assembled, but needs not be taken into consideration during
disassembly.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 739e78b..3f1b388 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4201,7 +4201,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), - D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), + D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD_NARROW | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), |