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| author | Chris Demetriou <cgd@google.com> | 2002-03-17 02:42:25 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-03-17 02:42:25 +0000 |
| commit | 444269101d8823b47b500af288fd115ca1c074d9 (patch) | |
| tree | 42dd1e6edcf367e6ea0de8853651f99e8070e2a3 /opcodes | |
| parent | ee2d3b3a594f55387e2b4ef27ada09032b8f2d45 (diff) | |
| download | gdb-444269101d8823b47b500af288fd115ca1c074d9.zip gdb-444269101d8823b47b500af288fd115ca1c074d9.tar.gz gdb-444269101d8823b47b500af288fd115ca1c074d9.tar.bz2 | |
2002-03-16 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (M3D): Tweak comment.
(mips_builtin_op): Add comment indicating that opcodes of the
same name must be placed together in the table, and sort
the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt",
"rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 19 |
2 files changed, 19 insertions, 8 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index af5cff2..ac24363 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2002-03-16 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (M3D): Tweak comment. + (mips_builtin_op): Add comment indicating that opcodes of the + same name must be placed together in the table, and sort + the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", + "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. + 2002-03-16 Nick Clifton <nickc@cambridge.redhat.com> * Makefile.am: Tidy up sh64 rules. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index e9d44fc..d3776d6 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -83,7 +83,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define I32 INSN_ISA32 #define I64 INSN_ISA64 -/* MIPS-3D support. */ +/* MIPS64 MIPS-3D ASE support. */ #define M3D INSN_MIPS3D #define P3 INSN_4650 @@ -109,6 +109,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * immediate operands must apear after the same instruction with registers. + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. + Many instructions are short hand for other instructions (i.e., The jal <register> instruction is short for jalr <register>). */ @@ -715,14 +718,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, +{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D }, -{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, @@ -739,14 +742,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, -{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D }, -{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D }, {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, |