[cgen/cpu]

	* cpu/mep-ivc2.cpu (h-ccr-ivc2): Enable for C3 slots, fix
	accumulator names.
	(f-ivc2-ccrn-c3hi): New.
	(f-ivc2-ccrn-c3lo): New.
	(f-ivc2-ccrn-c3): New.
	(ivc2c3ccrn): Use it.

[sid/component/cgen-cpu/mep]

	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-decode.h: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.

8 files changed, 60 insertions, 36 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a3b0f1b..7a48ec9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2009-05-26  DJ Delorie  <dj@redhat.com>
+
+	* mep-asm.c: Regenerate.
+	* mep-desc.c: Regenerate.
+	* mep-desc.h: Regenerate.
+	* mep-dis.c: Regenerate.
+	* mep-ibld.c: Regenerate.
+	* mep-opc.c: Regenerate.
+	* mep-opc.h: Regenerate.
+
 2009-05-26  Nick Clifton  <nickc@redhat.com>
 
 	* po/id.po: Updated Indonesian translation.
diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 1feff81..b0546f4 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -981,7 +981,7 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
       errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6));
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ccrn);
+      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn_c3);
       break;
     case MEP_OPERAND_IVC2CCRN :
       errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn);
diff --git a/opcodes/mep-desc.c b/opcodes/mep-desc.c
index d8a1988..7c8510e 100644
--- a/opcodes/mep-desc.c
+++ b/opcodes/mep-desc.c
@@ -473,22 +473,22 @@ static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
   { "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
   { "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
   { "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc00", 16, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc01", 17, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc02", 18, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc03", 19, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc04", 20, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc05", 21, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc06", 22, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc07", 23, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc10", 24, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc11", 25, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc12", 26, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc13", 27, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc14", 28, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc15", 29, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc16", 30, {0, {{{0, 0}}}}, 0, 0 },
-  { "$acc17", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
@@ -555,7 +555,7 @@ const CGEN_HW_ENTRY mep_cgen_hw_table[] =
   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
   { "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
   { "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
-  { "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
+  { "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
@@ -715,6 +715,8 @@ const CGEN_IFLD mep_cgen_ifld_table[] =
   { MEP_F_IVC2_3U25, "f-ivc2-3u25", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_IMM16P0, "f-ivc2-imm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_SIMM16P0, "f-ivc2-simm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
+  { MEP_F_IVC2_CCRN_C3HI, "f-ivc2-ccrn-c3hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
+  { MEP_F_IVC2_CCRN_C3LO, "f-ivc2-ccrn-c3lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CRN, "f-ivc2-crn", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CRM, "f-ivc2-crm", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CCRN_H1, "f-ivc2-ccrn-h1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
@@ -723,6 +725,7 @@ const CGEN_IFLD mep_cgen_ifld_table[] =
   { MEP_F_IVC2_CMOV1, "f-ivc2-cmov1", 0, 32, 8, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CMOV2, "f-ivc2-cmov2", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CMOV3, "f-ivc2-cmov3", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
+  { MEP_F_IVC2_CCRN_C3, "f-ivc2-ccrn-c3", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CCRN, "f-ivc2-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { MEP_F_IVC2_CRNX, "f-ivc2-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
@@ -747,6 +750,7 @@ const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
 
@@ -833,6 +837,12 @@ const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
     { 0, { (const PTR) 0 } }
 };
+const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
+    { 0, { (const PTR) 0 } }
+};
 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
 {
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
@@ -1347,7 +1357,7 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 /* ivc2c3ccrn: copro control reg CCRn */
   { "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
-    { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } }, 
+    { 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
diff --git a/opcodes/mep-desc.h b/opcodes/mep-desc.h
index 890227c..f402359 100644
--- a/opcodes/mep-desc.h
+++ b/opcodes/mep-desc.h
@@ -168,10 +168,11 @@ typedef enum ifield_type {
  , MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10
  , MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18
  , MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23
- , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CRN
- , MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1, MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO
- , MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2, MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN
- , MEP_F_IVC2_CRNX, MEP_F_MAX
+ , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CCRN_C3HI
+ , MEP_F_IVC2_CCRN_C3LO, MEP_F_IVC2_CRN, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1
+ , MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2
+ , MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN_C3, MEP_F_IVC2_CCRN, MEP_F_IVC2_CRNX
+ , MEP_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) MEP_F_MAX)
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index c1f3be3..79c7aad 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -929,7 +929,7 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
       print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
       break;
     case MEP_OPERAND_IVC2CCRN :
       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c
index bca4005..05767be 100644
--- a/opcodes/mep-ibld.c
+++ b/opcodes/mep-ibld.c
@@ -881,13 +881,13 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC2C3CCRN :
       {
 {
-  FLD (f_ccrn_hi) = ((((unsigned int) (FLD (f_ccrn)) >> (4))) & (3));
-  FLD (f_ccrn_lo) = ((FLD (f_ccrn)) & (15));
+  FLD (f_ivc2_ccrn_c3hi) = ((((unsigned int) (FLD (f_ivc2_ccrn_c3)) >> (4))) & (3));
+  FLD (f_ivc2_ccrn_c3lo) = ((FLD (f_ivc2_ccrn_c3)) & (15));
 }
-        errmsg = insert_normal (cd, fields->f_ccrn_hi, 0, 0, 28, 2, 32, total_length, buffer);
+        errmsg = insert_normal (cd, fields->f_ivc2_ccrn_c3hi, 0, 0, 28, 2, 32, total_length, buffer);
         if (errmsg)
           break;
-        errmsg = insert_normal (cd, fields->f_ccrn_lo, 0, 0, 4, 4, 32, total_length, buffer);
+        errmsg = insert_normal (cd, fields->f_ivc2_ccrn_c3lo, 0, 0, 4, 4, 32, total_length, buffer);
         if (errmsg)
           break;
       }
@@ -1461,11 +1461,11 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
       break;
     case MEP_OPERAND_IVC2C3CCRN :
       {
-        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ccrn_hi);
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_c3hi);
         if (length <= 0) break;
-        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ccrn_lo);
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_c3lo);
         if (length <= 0) break;
-  FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo)));
+  FLD (f_ivc2_ccrn_c3) = ((((FLD (f_ivc2_ccrn_c3hi)) << (4))) | (FLD (f_ivc2_ccrn_c3lo)));
       }
       break;
     case MEP_OPERAND_IVC2CCRN :
@@ -1918,7 +1918,7 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       value = fields->f_ivc2_3u6;
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      value = fields->f_ccrn;
+      value = fields->f_ivc2_ccrn_c3;
       break;
     case MEP_OPERAND_IVC2CCRN :
       value = fields->f_ivc2_ccrn;
@@ -2301,7 +2301,7 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       value = fields->f_ivc2_3u6;
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      value = fields->f_ccrn;
+      value = fields->f_ivc2_ccrn_c3;
       break;
     case MEP_OPERAND_IVC2CCRN :
       value = fields->f_ivc2_ccrn;
@@ -2685,7 +2685,7 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       fields->f_ivc2_3u6 = value;
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      fields->f_ccrn = value;
+      fields->f_ivc2_ccrn_c3 = value;
       break;
     case MEP_OPERAND_IVC2CCRN :
       fields->f_ivc2_ccrn = value;
@@ -3042,7 +3042,7 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
       fields->f_ivc2_3u6 = value;
       break;
     case MEP_OPERAND_IVC2C3CCRN :
-      fields->f_ccrn = value;
+      fields->f_ivc2_ccrn_c3 = value;
       break;
     case MEP_OPERAND_IVC2CCRN :
       fields->f_ivc2_ccrn = value;
diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index 1a8321e..a9b09a5 100644
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -439,7 +439,7 @@ static const CGEN_IFMT ifmt_cmov_crn_rm ATTRIBUTE_UNUSED = {
 };
 
 static const CGEN_IFMT ifmt_cmovc_ccrn_rm ATTRIBUTE_UNUSED = {
-  32, 32, 0xf00ffff3, { { F (F_MAJOR) }, { F (F_CCRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_30) }, { F (F_31) }, { 0 } }
+  32, 32, 0xf00ffff3, { { F (F_MAJOR) }, { F (F_IVC2_CCRN_C3) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_30) }, { F (F_31) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_cmov_crn_rm_p0 ATTRIBUTE_UNUSED = {
diff --git a/opcodes/mep-opc.h b/opcodes/mep-opc.h
index 0704c30..2795519 100644
--- a/opcodes/mep-opc.h
+++ b/opcodes/mep-opc.h
@@ -484,6 +484,8 @@ struct cgen_fields
   long f_ivc2_3u25;
   long f_ivc2_imm16p0;
   long f_ivc2_simm16p0;
+  long f_ivc2_ccrn_c3hi;
+  long f_ivc2_ccrn_c3lo;
   long f_ivc2_crn;
   long f_ivc2_crm;
   long f_ivc2_ccrn_h1;
@@ -492,6 +494,7 @@ struct cgen_fields
   long f_ivc2_cmov1;
   long f_ivc2_cmov2;
   long f_ivc2_cmov3;
+  long f_ivc2_ccrn_c3;
   long f_ivc2_ccrn;
   long f_ivc2_crnx;
 };