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| author | Jan Beulich <jbeulich@suse.com> | 2020-02-13 10:19:28 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-02-13 10:19:28 +0100 |
| commit | 7deea9aad86683a4bcc68d6dd073038039f7a267 (patch) | |
| tree | 5c65487902b62b9a4f48c25f47a30081f7408924 /opcodes | |
| parent | f3b0f7fe42309fa0e00b4d2074b0faefbf2e8ffd (diff) | |
| download | gdb-7deea9aad86683a4bcc68d6dd073038039f7a267.zip gdb-7deea9aad86683a4bcc68d6dd073038039f7a267.tar.gz gdb-7deea9aad86683a4bcc68d6dd073038039f7a267.tar.bz2 | |
x86: fix SSE4a dependencies of ".arch .nosse*"
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should
also disable SSE4a. And as per its name, ".arch .nosse4" should also do
so.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/i386-gen.c | 6 | ||||
| -rw-r--r-- | opcodes/i386-init.h | 12 |
3 files changed, 21 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ad10bf1..6b0c17f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2020-02-13 Jan Beulich <jbeulich@suse.com> + + * i386-gen.c (cpu_flag_init): Move CpuSSE4a from + CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add + CPU_ANY_SSE4_FLAGS entry. + * i386-init.h: Re-generate. + 2020-02-12 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index e1cc493..79f4cc9 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -322,17 +322,19 @@ static initializer cpu_flag_init[] = { "CPU_ANY_MMX_FLAGS", "CPU_3DNOWA_FLAGS" }, { "CPU_ANY_SSE_FLAGS", - "CPU_ANY_SSE2_FLAGS|CpuSSE|CpuSSE4a" }, + "CPU_ANY_SSE2_FLAGS|CpuSSE" }, { "CPU_ANY_SSE2_FLAGS", "CPU_ANY_SSE3_FLAGS|CpuSSE2" }, { "CPU_ANY_SSE3_FLAGS", - "CPU_ANY_SSSE3_FLAGS|CpuSSE3" }, + "CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" }, { "CPU_ANY_SSSE3_FLAGS", "CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" }, { "CPU_ANY_SSE4_1_FLAGS", "CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" }, { "CPU_ANY_SSE4_2_FLAGS", "CpuSSE4_2" }, + { "CPU_ANY_SSE4_FLAGS", + "CPU_ANY_SSE4_1_FLAGS|CpuSSE4a" }, { "CPU_ANY_AVX_FLAGS", "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, { "CPU_ANY_AVX2_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 2c93158..8ecf11719 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -1132,7 +1132,7 @@ #define CPU_ANY_SSE2_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ - 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1140,7 +1140,7 @@ #define CPU_ANY_SSE3_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1170,6 +1170,14 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } +#define CPU_ANY_SSE4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define CPU_ANY_AVX_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |