Add PDP-11 support

10 files changed, 603 insertions, 5 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1dc9b40..3a15815 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+        * Makefile.am: Add PDP-11 target.
+        * configure.in: Likewise.
+        * disassemble.c: Likewise.
+        * pdp11-dis.c: New file.
+        * pdp11-opc.c: New file.
+
 2001-02-14  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-ic.tbl: Update from Intel.  Add setf to fr-writers.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 664644e..42ff0c3 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -97,6 +97,8 @@ CFILES = \
 	m10300-dis.c \
 	m10300-opc.c \
 	ns32k-dis.c \
+	pdp11-dis.c \
+	pdp11-opc.c \
 	pj-dis.c \
 	pj-opc.c \
 	ppc-dis.c \
@@ -170,11 +172,13 @@ ALL_MACHINES = \
 	mips-dis.lo \
 	mips-opc.lo \
 	mips16-opc.lo \
+	ns32k-dis.lo \
+	pdp11-dis.lo \
+	pdp11-opc.lo \
 	pj-dis.lo \
 	pj-opc.lo \
 	ppc-dis.lo \
 	ppc-opc.lo \
-	ns32k-dis.lo \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
@@ -486,6 +490,8 @@ m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
   sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
   opintl.h
+pdp11-dis.lo: pdp11-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/pdp11.h
+pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
 pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
 pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 3d1a759..36c43e4 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -208,6 +208,8 @@ CFILES = \
 	m10300-dis.c \
 	m10300-opc.c \
 	ns32k-dis.c \
+	pdp11-dis.c \
+	pdp11-opc.c \
 	pj-dis.c \
 	pj-opc.c \
 	ppc-dis.c \
@@ -282,11 +284,13 @@ ALL_MACHINES = \
 	mips-dis.lo \
 	mips-opc.lo \
 	mips16-opc.lo \
+	ns32k-dis.lo \
+	pdp11-dis.lo \
+	pdp11-opc.lo \
 	pj-dis.lo \
 	pj-opc.lo \
 	ppc-dis.lo \
 	ppc-opc.lo \
-	ns32k-dis.lo \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
@@ -370,7 +374,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
 
 DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
 
-TAR = tar
+TAR = gtar
 GZIP_ENV = --best
 SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
 OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
@@ -996,6 +1000,8 @@ m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
   sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
   opintl.h
+pdp11-dis.lo: pdp11-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/pdp11.h
+pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
 pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
 pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/configure b/opcodes/configure
index 7d63895..6301ad6 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -4542,6 +4542,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_mn10200_arch)	ta="$ta m10200-dis.lo m10200-opc.lo" ;;
 	bfd_mn10300_arch)	ta="$ta m10300-dis.lo m10300-opc.lo" ;;
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
+	bfd_pdp11_arch)		ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 34b947a..f8030d9 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -196,6 +196,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_mn10200_arch)	ta="$ta m10200-dis.lo m10200-opc.lo" ;;
 	bfd_mn10300_arch)	ta="$ta m10300-dis.lo m10300-opc.lo" ;;
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
+	bfd_pdp11_arch)		ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index ce3b6ad..b5a1fca 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -47,6 +47,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_mn10200
 #define ARCH_mn10300
 #define ARCH_ns32k
+#define ARCH_pdp11
 #define ARCH_pj
 #define ARCH_powerpc
 #define ARCH_rs6000
@@ -225,6 +226,11 @@ disassembler (abfd)
       disassemble = print_insn_mn10300;
       break;
 #endif
+#ifdef ARCH_pdp11
+    case bfd_arch_pdp11:
+      disassemble = print_insn_pdp11;
+      break;
+#endif
 #ifdef ARCH_pj
     case bfd_arch_pj:
       disassemble = print_insn_pj;
diff --git a/opcodes/pdp11-dis.c b/opcodes/pdp11-dis.c
new file mode 100644
index 0000000..e13c7aa
--- /dev/null
+++ b/opcodes/pdp11-dis.c
@@ -0,0 +1,323 @@
+/* Print DEC PDP-11 instructions.
+   Copyright 2001 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "dis-asm.h"
+#include "opcode/pdp11.h"
+
+#define AFTER_INSTRUCTION	"\t"
+#define OPERAND_SEPARATOR	", "
+
+#define JUMP	0x1000	/* flag that this operand is used in a jump */
+
+#define FPRINTF	(*info->fprintf_func)
+#define F	info->stream
+
+/* sign-extend a 16-bit number in an int */
+#define SIGN_BITS	(8 * sizeof (int) - 16)
+#define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS)
+
+static int read_word PARAMS ((bfd_vma memaddr, int *word,
+			      disassemble_info *info));
+static void print_signed_octal PARAMS ((int n, disassemble_info *info));
+static void print_reg PARAMS ((int reg, disassemble_info *info));
+static void print_freg PARAMS ((int freg, disassemble_info *info));
+static int print_operand PARAMS ((bfd_vma *memaddr, int code,
+				  disassemble_info *info));
+int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
+
+static int
+read_word (memaddr, word, info)
+     bfd_vma memaddr;
+     int *word;
+     disassemble_info *info;
+{
+  int status;
+  bfd_byte x[2];
+
+  status = (*info->read_memory_func) (memaddr, x, 2, info);
+  if (status != 0)
+    return -1;
+
+  *word = x[1] << 8 | x[0];
+  return 0;
+}
+
+static void
+print_signed_octal (n, info)
+     int n;
+     disassemble_info *info;
+{
+  if (n < 0)
+    FPRINTF (F, "-%o", -n);
+  else
+    FPRINTF (F, "%o", n);
+}
+
+static void
+print_reg (reg, info)
+     int reg;
+     disassemble_info *info;
+{
+  /* mask off the addressing mode, if any */
+  reg &= 7;
+
+  switch (reg)
+    {
+    case 0: case 1: case 2: case 3: case 4: case 5:
+		FPRINTF (F, "r%d", reg); break;
+    case 6:	FPRINTF (F, "sp"); break;
+    case 7:	FPRINTF (F, "pc"); break;
+    default:	/* error */
+    }
+}
+
+static void
+print_freg (freg, info)
+     int freg;
+     disassemble_info *info;
+{
+  FPRINTF (F, "fr%d", freg);
+}
+
+static int
+print_operand (memaddr, code, info)
+     bfd_vma *memaddr;
+     int code;
+     disassemble_info *info;
+{
+  int mode = (code >> 3) & 7;
+  int reg = code & 7;
+  int disp;
+
+  switch (mode)
+    {
+    case 0:
+      print_reg (reg, info);
+      break;
+    case 1:
+      FPRINTF (F, "(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 2:
+      if (reg == 7)
+	{
+	  int data;
+	  if (read_word (*memaddr, &data, info) < 0)
+	    return -1;
+	  FPRINTF (F, "$");
+	  print_signed_octal (sign_extend (data), info);
+	  *memaddr += 2;
+	}
+      else
+	{
+	  FPRINTF (F, "(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")+");
+	}
+	break;
+    case 3:
+      if (reg == 7)
+	{
+	  int address;
+	  if (read_word (*memaddr, &address, info) < 0)
+	    return -1;
+	  FPRINTF (F, "*$%o", address);
+	  *memaddr += 2;
+	}
+      else
+	{
+	  FPRINTF (F, "*(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")+");
+	}
+	break;
+    case 4:
+      FPRINTF (F, "-(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 5:
+      FPRINTF (F, "*-(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 6:
+    case 7:
+      if (read_word (*memaddr, &disp, info) < 0)
+	return -1;
+      *memaddr += 2;
+      if (reg == 7)
+	{
+	  bfd_vma address = *memaddr + sign_extend (disp);
+	  if (!(code & JUMP))
+	    FPRINTF (F, "*$");
+	  (*info->print_address_func) (address, info);
+	}
+      else
+	{
+	  if (mode == 7)
+	    FPRINTF (F, "*");
+	  print_signed_octal (sign_extend (disp), info);
+	  FPRINTF (F, "(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")");
+	}
+      break;
+    }
+
+  return 0;
+}
+
+/* Print the PDP-11 instruction at address MEMADDR in debugged memory,
+   on INFO->STREAM.  Returns length of the instruction, in bytes.  */
+
+int
+print_insn_pdp11 (memaddr, info)
+     bfd_vma memaddr;
+     disassemble_info *info;
+{
+  bfd_vma start_memaddr = memaddr;
+  int opcode;
+  int src, dst;
+  int i;
+
+  info->bytes_per_line = 6;
+  info->bytes_per_chunk = 2;
+  info->display_endian = BFD_ENDIAN_LITTLE;
+
+  if (read_word (memaddr, &opcode, info) != 0)
+    return -1;
+  memaddr += 2;
+
+  src = (opcode >> 6) & 0x3f;
+  dst = opcode & 0x3f;
+
+  for (i = 0; i < pdp11_num_opcodes; i++)
+    {
+#define OP pdp11_opcodes[i]
+      if ((opcode & OP.mask) == OP.opcode)
+	switch (OP.type)
+	  {
+	  case PDP11_OPCODE_NO_OPS:
+	    FPRINTF (F, OP.name);
+	    break;
+	  case PDP11_OPCODE_REG:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    print_reg (dst, info);
+	    break;
+	  case PDP11_OPCODE_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (strcmp (OP.name, "jmp") == 0)
+	      dst |= JUMP;
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_REG_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    print_reg (src, info);
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    if (strcmp (OP.name, "jsr") == 0)
+	      dst |= JUMP;
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_REG_OP_REV:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    print_reg (src, info);
+	    break;
+	  case PDP11_OPCODE_AC_OP:
+	    {
+	      int ac = (opcode & 0xe0) >> 6;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      print_freg (ac, info);
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      if (print_operand (&memaddr, dst, info) < 0)
+		return -1;
+	      break;
+	    }
+	  case PDP11_OPCODE_OP_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (print_operand (&memaddr, src, info) < 0)
+	      return -1;
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_DISPL:
+	    {
+	      int displ = (opcode & 0xff) << 8;
+	      bfd_vma address = memaddr + (sign_extend (displ) >> 7);
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      (*info->print_address_func) (address, info);
+	      break;
+	    }
+	  case PDP11_OPCODE_REG_DISPL:
+	    {
+	      int displ = (opcode & 0x3f) << 10;
+	      bfd_vma address = memaddr + (sign_extend (displ) >> 9);
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      print_reg (src, info);
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      (*info->print_address_func) (address, info);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM8:
+	    {
+	      int code = opcode & 0xff;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM6:
+	    {
+	      int code = opcode & 0x3f;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM3:
+	    {
+	      int code = opcode & 7;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  default:
+	    /* TODO: is this a proper way of signalling an error? */
+	    FPRINTF (F, "<internal error: unrecognized instruction type>");
+	    return -1;
+	  }
+#undef OP
+    }
+
+  return memaddr - start_memaddr;
+}
diff --git a/opcodes/pdp11-opc.c b/opcodes/pdp11-opc.c
new file mode 100644
index 0000000..3517dee
--- /dev/null
+++ b/opcodes/pdp11-opc.c
@@ -0,0 +1,245 @@
+/* Opcode table for PDP-11.
+   Copyright 2001 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "opcode/pdp11.h"
+
+const struct pdp11_opcode pdp11_opcodes[] =
+{
+  /* name,	pattern, mask,	opcode type,		insn type,    alias */
+  { "halt",	0x0000,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "wait",	0x0001,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "rti",	0x0002,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "bpt",	0x0003,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "iot",	0x0004,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "reset",	0x0005,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "rtt",	0x0006,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_LEIS },
+  { "mfpt",	0x0007,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_MFPT },
+  { "jmp",	0x0040,	0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rts",	0x0080,	0xfff8, PDP11_OPCODE_REG,	PDP11_BASIC },
+  { "",		0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },
+  { "",		0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },
+  { "spl",	0x0098,	0xfff8, PDP11_OPCODE_IMM3,	PDP11_SPL },
+  { "nop",	0x00a0,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clc",	0x00a1,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clv",	0x00a2,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_3",	0x00a3,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clz",	0x00a4,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_5",	0x00a5,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_6",	0x00a6,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_7",	0x00a7,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cln",	0x00a8,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_9",	0x00a9,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_a",	0x00aa,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_b",	0x00ab,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_c",	0x00ac,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_d",	0x00ad,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_e",	0x00ae,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "ccc",	0x00af,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_0",	0x00b0,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sec",	0x00a1,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sev",	0x00b2,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_3",	0x00b3,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sez",	0x00b4,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_5",	0x00b5,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_6",	0x00b6,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_7",	0x00b7,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sen",	0x00b8,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_9",	0x00b9,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_a",	0x00ba,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_b",	0x00bb,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_c",	0x00bc,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_d",	0x00bd,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_e",	0x00be,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "scc",	0x00bf,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "swab",	0x00c0,	0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "br",	0x0100, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bne",	0x0200, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "beq",	0x0300, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bge",	0x0400, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blt",	0x0500, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bgt",	0x0600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "ble",	0x0700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "jsr",	0x0800, 0xfe00, PDP11_OPCODE_REG_OP,	PDP11_BASIC },
+  { "clr",	0x0a00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "com",	0x0a40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "inc",	0x0a80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "dec",	0x0ac0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "neg",	0x0b00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "adc",	0x0b40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sbc",	0x0b80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "tst",	0x0bc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "ror",	0x0c00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rol",	0x0c40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asr",	0x0c80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asl",	0x0cc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mark",	0x0d00, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
+  { "mfpi",	0x0d40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtpi",	0x0d80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sxt",	0x0dc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
+  { "csm",	0x0e00, 0xffc0, PDP11_OPCODE_OP,	PDP11_CSM },
+  { "tstset",	0x0e40, 0xffc0, PDP11_OPCODE_OP,	PDP11_MPROC },
+  { "wrtlck",	0x0e80, 0xffc0, PDP11_OPCODE_OP,	PDP11_MPROC },
+/*{ "",		0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+  { "mov",	0x1000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cmp",	0x2000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bit",	0x3000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bic",	0x4000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bis",	0x5000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "add",	0x6000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "mul",	0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "div",	0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "ash",	0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "ashc",	0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "xor",	0x7800, 0xfe00, PDP11_OPCODE_REG_OP,	PDP11_LEIS },
+  { "fadd",	0x7a00, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fsub",	0x7a08, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fmul",	0x7a10, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fdiv",	0x7a18, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+/*{ "",		0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+  { "l2dr",	0x7c10, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },/*l2d*/
+  { "movc",	0x7c18, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movrc",	0x7c19, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movtc",	0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "locc",	0x7c20, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "skpc",	0x7c21, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "scanc",	0x7c22, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "spanc",	0x7c23, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpc",	0x7c24, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "matc",	0x7c25, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addn",	0x7c28, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subn",	0x7c29, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpn",	0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnl",	0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpn",	0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnp",	0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashn",	0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtln",	0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "l3dr",	0x7c30, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },/*l3d*/
+  { "addp",	0x7c38, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subp",	0x7c39, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpp",	0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpl",	0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "mulp",	0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "divp",	0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashp",	0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlp",	0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movci",	0x7c58, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movrci",	0x7c59, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movtci",	0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "locci",	0x7c60, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "skpci",	0x7c61, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "scanci",	0x7c62, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "spanci",	0x7c63, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpci",	0x7c64, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "matci",	0x7c65, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addni",	0x7c68, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subni",	0x7c69, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpni",	0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnli",	0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpni",	0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnpi",	0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashni",	0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlni",	0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addpi",	0x7c78, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subpi",	0x7c79, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmppi",	0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpli",	0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "mulpi",	0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "divpi",	0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashpi",	0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlpi",	0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "med",	0x7d80, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_UCODE },
+  { "xfc",	0x7dc0, 0xffc0, PDP11_OPCODE_IMM6,	PDP11_UCODE },
+  { "sob",	0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL,	PDP11_LEIS },
+  { "bpl",	0x8000, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bmi",	0x8100, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bhi",	0x8200, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blos",	0x8300, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bvc",	0x8400, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bvs",	0x8500, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bcc",	0x8600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },/*bhis*/
+  { "bcs",	0x8700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },/*blo*/
+  { "emt",	0x8800, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },
+  { "sys",	0x8900, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },/*trap*/
+  { "clrb",	0x8a00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "comb",	0x8a40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "incb",	0x8a80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "decb",	0x8ac0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "negb",	0x8b00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "adcb",	0x8b40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sbcb",	0x8b80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "tstb",	0x8bc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rorb",	0x8c00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rolb",	0x8c40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asrb",	0x8c80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "aslb",	0x8cc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtps",	0x8d00, 0xffc0, PDP11_OPCODE_OP,	PDP11_MXPS },
+  { "mfpd",	0x8d40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtpd",	0x8d80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mfps",	0x8dc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_MXPS },
+  { "movb",	0x9000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cmpb",	0xa000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bitb",	0xb000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bicb",	0xc000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bisb",	0xd000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "sub",	0xe000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cfcc",	0xf000, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "setf",	0xf001, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "seti",	0xf002, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "ldub",	0xf003, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_UCODE },
+  /* fpp trap	0xf004..0xf008 */
+  { "setd",	0xf009, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "setl",	0xf00a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  /* fpp trap	0xf00b..0xf03f */
+  { "ldfps",	0xf040, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "stfps",	0xf080, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "stst",	0xf0c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "clrf",	0xf100, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "tstf",	0xf140, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "absf",	0xf180, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "negf",	0xf1c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "mulf",	0xf200, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "modf",	0xf300, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "addf",	0xf400, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldf",	0xf500, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movif*/
+  { "subf",	0xf600, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "cmpf",	0xf700, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stf",	0xf800, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movfi*/
+  { "divf",	0xf900, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stexp",	0xfa00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcfi",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcff",	0xfc00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
+  { "ldexp",	0xfd00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldcif",	0xfe00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldcff",	0xff00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
+};
+
+const struct pdp11_opcode pdp11_aliases[] =
+{
+  /* name,	pattern, mask,	opcode type,		insn type */
+  { "l2d",	0x7c10, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },
+  { "l3d",	0x7c30, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },
+  { "bhis",	0x8600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blo",	0x8700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "trap",	0x8900, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },
+};
+
+const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0];
+const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0];
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index 2beea2a..766319d 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -69,6 +69,8 @@ mips16-opc.c
 mips-dis.c
 mips-opc.c
 ns32k-dis.c
+pdp11-dis.c
+pdp11-opc.c
 pj-dis.c
 pj-opc.c
 ppc-dis.c
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index 944647a..f7de22b 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-02-09 16:04-0800\n"
+"POT-Creation-Date: 2001-02-18 14:44-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -186,7 +186,7 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:2741
+#: i386-dis.c:2742
 msgid "<internal disassembler error>"
 msgstr ""