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authorJan Beulich <jbeulich@suse.com>2021-03-25 08:19:21 +0100
committerJan Beulich <jbeulich@suse.com>2021-03-25 08:19:21 +0100
commit5364285240737423a4d6368aba803a031d293b95 (patch)
tree93558016404461968935f1d30751cd8e50dbfc01 /opcodes
parentc0e54661f755b1eb1cbf745bc4eb4a068cd5ada2 (diff)
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x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear
This combination makes no sense and is documented to cause #UD.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/i386-dis.c7
2 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bd02d2b..a4c880b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2021-03-25 Jan Beulich <jbeulich@suse.com>
+ * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
+ zeroing-masking without masking.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
* i386-opc.tbl (invlpgb): Fix multi-operand form.
(pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
single-operand forms as deprecated.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9e5c412..00ed251 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9739,6 +9739,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
return end_codep - priv.the_buffer;
}
+ /* If EVEX.z is set, there must be an actual mask register in use. */
+ if (vex.zeroing && vex.mask_register_specifier == 0)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
switch (dp->prefix_requirement)
{
case PREFIX_DATA: