* fr30-asm.c,fr30-desc.h: Rebuild.

	* m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild.  Add m32rx support.
	* m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto.

11 files changed, 1024 insertions, 164 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0ae033..1e2e55c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+1999-10-04  Doug Evans  <devans@casey.cygnus.com>
+
+	* fr30-asm.c,fr30-desc.h: Rebuild.
+	* m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild.  Add m32rx support.
+	* m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto.
+
 1999-09-29  Nick Clifton  <nickc@cygnus.com>
 
 	* sh-opc.h: Fix bit patterns for several load and store
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index b9f8010..6038dbb 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -364,9 +364,14 @@ parse_insn_normal (cd, insn, strp, fields)
   p = CGEN_INSN_MNEMONIC (insn);
   while (*p && tolower (*p) == tolower (*str))
     ++p, ++str;
-  
-  if (* p || (* str && !isspace (* str)))
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && !isspace (* str))
     return _("unrecognized instruction");
+#endif
 
   CGEN_INIT_PARSE (cd);
   cgen_init_parse_operand (cd);
@@ -389,6 +394,10 @@ parse_insn_normal (cd, insn, strp, fields)
       /* Non operand chars must match exactly.  */
       if (CGEN_SYNTAX_CHAR_P (* syn))
 	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
 	  if (*str == CGEN_SYNTAX_CHAR (* syn))
 	    {
 #ifdef CGEN_MNEMONIC_OPERANDS
diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h
index a1ff45e..97e29cd 100644
--- a/opcodes/fr30-desc.h
+++ b/opcodes/fr30-desc.h
@@ -49,6 +49,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
    we can't hash on everything up to the space.  */
 #define CGEN_MNEMONIC_OPERANDS
+
 /* Maximum number of operands any insn or macro-insn has.  */
 #define CGEN_MAX_INSN_OPERANDS 16
 
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 0d67c92..2d3bd96 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -222,6 +222,15 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_acc);
+      break;
+    case M32R_OPERAND_ACCD :
+      errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accd);
+      break;
+    case M32R_OPERAND_ACCS :
+      errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accs);
+      break;
     case M32R_OPERAND_DCR :
       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r1);
       break;
@@ -255,6 +264,9 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
     case M32R_OPERAND_HI16 :
       errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16);
       break;
+    case M32R_OPERAND_IMM1 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_IMM1, &fields->f_imm1);
+      break;
     case M32R_OPERAND_SCR :
       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2);
       break;
@@ -360,9 +372,14 @@ parse_insn_normal (cd, insn, strp, fields)
   p = CGEN_INSN_MNEMONIC (insn);
   while (*p && tolower (*p) == tolower (*str))
     ++p, ++str;
-  
-  if (* p || (* str && !isspace (* str)))
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && !isspace (* str))
     return _("unrecognized instruction");
+#endif
 
   CGEN_INIT_PARSE (cd);
   cgen_init_parse_operand (cd);
@@ -385,6 +402,10 @@ parse_insn_normal (cd, insn, strp, fields)
       /* Non operand chars must match exactly.  */
       if (CGEN_SYNTAX_CHAR_P (* syn))
 	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
 	  if (*str == CGEN_SYNTAX_CHAR (* syn))
 	    {
 #ifdef CGEN_MNEMONIC_OPERANDS
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 9cb5462..ee1cfa9 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -46,6 +46,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
 {
   { "base", MACH_BASE },
   { "m32r", MACH_M32R },
+  { "m32rx", MACH_M32RX },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -57,6 +58,15 @@ static const CGEN_ATTR_ENTRY ISA_attr[] =
   { 0, 0 }
 };
 
+static const CGEN_ATTR_ENTRY PIPE_attr[] =
+{
+  { "NONE", PIPE_NONE },
+  { "O", PIPE_O },
+  { "S", PIPE_S },
+  { "OS", PIPE_OS },
+  { 0, 0 }
+};
+
 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
 {
   { "MACH", & MACH_attr[0] },
@@ -99,6 +109,7 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 {
   { "MACH", & MACH_attr[0] },
+  { "PIPE", & PIPE_attr[0] },
   { "ALIAS", &bool_attr[0], &bool_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
@@ -110,6 +121,7 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
 };
 
@@ -124,6 +136,7 @@ static const CGEN_ISA m32r_cgen_isa_table[] = {
 
 static const CGEN_MACH m32r_cgen_mach_table[] = {
   { "m32r", "m32r", MACH_M32R },
+  { "m32rx", "m32rx", MACH_M32RX },
   { 0 }
 };
 
@@ -189,6 +202,18 @@ CGEN_KEYWORD m32r_cgen_opval_cr_names =
   23
 };
 
+static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
+{
+  { "a0", 0 },
+  { "a1", 1 }
+};
+
+CGEN_KEYWORD m32r_cgen_opval_h_accums =
+{
+  & m32r_cgen_opval_h_accums_entries[0],
+  2
+};
+
 
 
 /* The hardware table.  */
@@ -209,6 +234,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
@@ -242,6 +268,14 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
   { 0 }
 };
 
@@ -290,6 +324,18 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* imm1: 1 bit immediate */
+  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
+    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
+/* accd: accumulator destination register */
+  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
+    { 0, { (1<<MACH_M32RX) } }  },
+/* accs: accumulator source register */
+  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
+    { 0, { (1<<MACH_M32RX) } }  },
+/* acc: accumulator reg (d) */
+  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
+    { 0, { (1<<MACH_M32RX) } }  },
 /* hash: # prefix */
   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
     { 0, { (1<<MACH_BASE) } }  },
@@ -339,497 +385,672 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* add $dr,$sr */
   {
     M32R_INSN_ADD, "add", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* add3 $dr,$sr,$hash$slo16 */
   {
     M32R_INSN_ADD3, "add3", "add3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* and $dr,$sr */
   {
     M32R_INSN_AND, "and", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_AND3, "and3", "and3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* or $dr,$sr */
   {
     M32R_INSN_OR, "or", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* or3 $dr,$sr,$hash$ulo16 */
   {
     M32R_INSN_OR3, "or3", "or3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* xor $dr,$sr */
   {
     M32R_INSN_XOR, "xor", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_XOR3, "xor3", "xor3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* addi $dr,$simm8 */
   {
     M32R_INSN_ADDI, "addi", "addi", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* addv $dr,$sr */
   {
     M32R_INSN_ADDV, "addv", "addv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     M32R_INSN_ADDV3, "addv3", "addv3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* addx $dr,$sr */
   {
     M32R_INSN_ADDX, "addx", "addx", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* bc.s $disp8 */
   {
     M32R_INSN_BC8, "bc8", "bc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bc.l $disp24 */
   {
     M32R_INSN_BC24, "bc24", "bc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     M32R_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* beqz $src2,$disp16 */
   {
     M32R_INSN_BEQZ, "beqz", "beqz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bgez $src2,$disp16 */
   {
     M32R_INSN_BGEZ, "bgez", "bgez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bgtz $src2,$disp16 */
   {
     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* blez $src2,$disp16 */
   {
     M32R_INSN_BLEZ, "blez", "blez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bltz $src2,$disp16 */
   {
     M32R_INSN_BLTZ, "bltz", "bltz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bnez $src2,$disp16 */
   {
     M32R_INSN_BNEZ, "bnez", "bnez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bl.s $disp8 */
   {
     M32R_INSN_BL8, "bl8", "bl.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bl.l $disp24 */
   {
     M32R_INSN_BL24, "bl24", "bl.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bcl.s $disp8 */
+  {
+    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bcl.l $disp24 */
+  {
+    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
+    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* bnc.s $disp8 */
   {
     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bnc.l $disp24 */
   {
     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     M32R_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bra.s $disp8 */
   {
     M32R_INSN_BRA8, "bra8", "bra.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bra.l $disp24 */
   {
     M32R_INSN_BRA24, "bra24", "bra.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bncl.s $disp8 */
+  {
+    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bncl.l $disp24 */
+  {
+    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
+    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* cmp $src1,$src2 */
   {
     M32R_INSN_CMP, "cmp", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* cmpi $src2,$simm16 */
   {
     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* cmpu $src1,$src2 */
   {
     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* cmpui $src2,$simm16 */
   {
     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* cmpeq $src1,$src2 */
+  {
+    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+  },
+/* cmpz $src2 */
+  {
+    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* div $dr,$sr */
   {
     M32R_INSN_DIV, "div", "div", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* divu $dr,$sr */
   {
     M32R_INSN_DIVU, "divu", "divu", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* rem $dr,$sr */
   {
     M32R_INSN_REM, "rem", "rem", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* remu $dr,$sr */
   {
     M32R_INSN_REMU, "remu", "remu", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* divh $dr,$sr */
+  {
+    M32R_INSN_DIVH, "divh", "divh", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* jc $sr */
+  {
+    M32R_INSN_JC, "jc", "jc", 16,
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* jnc $sr */
+  {
+    M32R_INSN_JNC, "jnc", "jnc", 16,
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* jl $sr */
   {
     M32R_INSN_JL, "jl", "jl", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* jmp $sr */
   {
     M32R_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld $dr,@$sr */
   {
     M32R_INSN_LD, "ld", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     M32R_INSN_LD_D, "ld-d", "ld", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldb $dr,@$sr */
   {
     M32R_INSN_LDB, "ldb", "ldb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldh $dr,@$sr */
   {
     M32R_INSN_LDH, "ldh", "ldh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldub $dr,@$sr */
   {
     M32R_INSN_LDUB, "ldub", "ldub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* lduh $dr,@$sr */
   {
     M32R_INSN_LDUH, "lduh", "lduh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ld $dr,@$sr+ */
   {
     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld24 $dr,$uimm24 */
   {
     M32R_INSN_LD24, "ld24", "ld24", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldi8 $dr,$simm8 */
   {
     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* ldi16 $dr,$hash$slo16 */
   {
     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* lock $dr,@$sr */
   {
     M32R_INSN_LOCK, "lock", "lock", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* machi $src1,$src2 */
   {
     M32R_INSN_MACHI, "machi", "machi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* machi $src1,$src2,$acc */
+  {
+    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* maclo $src1,$src2 */
   {
     M32R_INSN_MACLO, "maclo", "maclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* maclo $src1,$src2,$acc */
+  {
+    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* macwhi $src1,$src2 */
   {
     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* macwhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* macwlo $src1,$src2,$acc */
+  {
+    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
     M32R_INSN_MUL, "mul", "mul", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_S } }
   },
 /* mulhi $src1,$src2 */
   {
     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mullo $src1,$src2 */
   {
     M32R_INSN_MULLO, "mullo", "mullo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mullo $src1,$src2,$acc */
+  {
+    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mulwhi $src1,$src2 */
   {
     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulwhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulwlo $src1,$src2,$acc */
+  {
+    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
     M32R_INSN_MV, "mv", "mv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* mvfachi $dr */
   {
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfachi $dr,$accs */
+  {
+    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfaclo $dr */
   {
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfaclo $dr,$accs */
+  {
+    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfacmi $dr */
   {
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfacmi $dr,$accs */
+  {
+    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfc $dr,$scr */
   {
     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* mvtachi $src1 */
   {
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvtachi $src1,$accs */
+  {
+    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvtaclo $src1 */
   {
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvtaclo $src1,$accs */
+  {
+    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvtc $sr,$dcr */
   {
     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* neg $dr,$sr */
   {
     M32R_INSN_NEG, "neg", "neg", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* nop */
   {
     M32R_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* not $dr,$sr */
   {
     M32R_INSN_NOT, "not", "not", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* rac */
   {
     M32R_INSN_RAC, "rac", "rac", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* rac $accd,$accs,$imm1 */
+  {
+    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* rach */
   {
     M32R_INSN_RACH, "rach", "rach", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* rach $accd,$accs,$imm1 */
+  {
+    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* rte */
   {
     M32R_INSN_RTE, "rte", "rte", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* seth $dr,$hash$hi16 */
   {
     M32R_INSN_SETH, "seth", "seth", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* sll $dr,$sr */
   {
     M32R_INSN_SLL, "sll", "sll", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SLL3, "sll3", "sll3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* slli $dr,$uimm5 */
   {
     M32R_INSN_SLLI, "slli", "slli", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sra $dr,$sr */
   {
     M32R_INSN_SRA, "sra", "sra", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRA3, "sra3", "sra3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* srai $dr,$uimm5 */
   {
     M32R_INSN_SRAI, "srai", "srai", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* srl $dr,$sr */
   {
     M32R_INSN_SRL, "srl", "srl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRL3, "srl3", "srl3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* srli $dr,$uimm5 */
   {
     M32R_INSN_SRLI, "srli", "srli", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@$src2 */
   {
     M32R_INSN_ST, "st", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     M32R_INSN_ST_D, "st-d", "st", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* stb $src1,@$src2 */
   {
     M32R_INSN_STB, "stb", "stb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     M32R_INSN_STB_D, "stb-d", "stb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* sth $src1,@$src2 */
   {
     M32R_INSN_STH, "sth", "sth", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     M32R_INSN_STH_D, "sth-d", "sth", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* st $src1,@+$src2 */
   {
     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@-$src2 */
   {
     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sub $dr,$sr */
   {
     M32R_INSN_SUB, "sub", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* subv $dr,$sr */
   {
     M32R_INSN_SUBV, "subv", "subv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* subx $dr,$sr */
   {
     M32R_INSN_SUBX, "subx", "subx", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* trap $uimm4 */
   {
     M32R_INSN_TRAP, "trap", "trap", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* unlock $src1,@$src2 */
   {
     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
+  },
+/* satb $dr,$sr */
+  {
+    M32R_INSN_SATB, "satb", "satb", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* sath $dr,$sr */
+  {
+    M32R_INSN_SATH, "sath", "sath", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* sat $dr,$sr */
+  {
+    M32R_INSN_SAT, "sat", "sat", 32,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* pcmpbz $src2 */
+  {
+    M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+  },
+/* sadd */
+  {
+    M32R_INSN_SADD, "sadd", "sadd", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* macwu1 $src1,$src2 */
+  {
+    M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* msblo $src1,$src2 */
+  {
+    M32R_INSN_MSBLO, "msblo", "msblo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* mulwu1 $src1,$src2 */
+  {
+    M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* maclh1 $src1,$src2 */
+  {
+    M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* sc */
+  {
+    M32R_INSN_SC, "sc", "sc", 16,
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* snc */
+  {
+    M32R_INSN_SNC, "snc", "snc", 16,
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 };
 
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index f83dab5..6a0fac6 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* Selected cpu families.  */
 #define HAVE_CPU_M32RBF
+#define HAVE_CPU_M32RXF
 
 #define CGEN_INSN_LSB0_P 0
 
@@ -49,6 +50,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
    we can't hash on everything up to the space.  */
 #define CGEN_MNEMONIC_OPERANDS
+
 /* Maximum number of operands any insn or macro-insn has.  */
 #define CGEN_MAX_INSN_OPERANDS 16
 
@@ -96,8 +98,7 @@ typedef enum cr_names {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_M32R
- , MACH_MAX
+  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -105,6 +106,11 @@ typedef enum isa_attr {
   ISA_M32R, ISA_MAX
 } ISA_ATTR;
 
+/* Enum declaration for parallel execution pipeline selection.  */
+typedef enum pipe_attr {
+  PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+} PIPE_ATTR;
+
 /* Number of architecture variants.  */
 #define MAX_ISAS  1
 #define MAX_MACHS ((int) MACH_MAX)
@@ -131,8 +137,9 @@ typedef enum ifield_type {
  , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16
  , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16
  , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16
- , M32R_F_DISP24
- , M32R_F_MAX
+ , M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3, M32R_F_ACC
+ , M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT14
+ , M32R_F_IMM1, M32R_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) M32R_F_MAX)
@@ -153,8 +160,8 @@ typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
  , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
- , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW
- , HW_H_LOCK, HW_MAX
+ , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW
+ , HW_H_BBPSW, HW_H_LOCK, HW_MAX
 } CGEN_HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
@@ -177,6 +184,7 @@ typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
+ , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
  , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
  , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
  , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
@@ -215,6 +223,7 @@ extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 
 extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
+extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 
 
 
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index f4fd199..f880784 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -164,6 +164,15 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
+      break;
+    case M32R_OPERAND_ACCD :
+      print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
+      break;
+    case M32R_OPERAND_ACCS :
+      print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
+      break;
     case M32R_OPERAND_DCR :
       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
       break;
@@ -185,6 +194,9 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case M32R_OPERAND_HI16 :
       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
       break;
+    case M32R_OPERAND_IMM1 :
+      print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
     case M32R_OPERAND_SCR :
       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
       break;
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 5b78547..48dc73f 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -584,6 +584,15 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
+      break;
+    case M32R_OPERAND_ACCD :
+      errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
+      break;
+    case M32R_OPERAND_ACCS :
+      errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_DCR :
       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
       break;
@@ -616,6 +625,13 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case M32R_OPERAND_HI16 :
       errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_IMM1 :
+      {
+        long value = fields->f_imm1;
+        value = ((value) - (1));
+        errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
+      }
+      break;
     case M32R_OPERAND_SCR :
       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
       break;
@@ -694,6 +710,15 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
+      break;
+    case M32R_OPERAND_ACCD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
+      break;
+    case M32R_OPERAND_ACCS :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
+      break;
     case M32R_OPERAND_DCR :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
       break;
@@ -729,6 +754,14 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case M32R_OPERAND_HI16 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
       break;
+    case M32R_OPERAND_IMM1 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
+        value = ((value) + (1));
+        fields->f_imm1 = value;
+      }
+      break;
     case M32R_OPERAND_SCR :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
       break;
@@ -801,6 +834,15 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      value = fields->f_acc;
+      break;
+    case M32R_OPERAND_ACCD :
+      value = fields->f_accd;
+      break;
+    case M32R_OPERAND_ACCS :
+      value = fields->f_accs;
+      break;
     case M32R_OPERAND_DCR :
       value = fields->f_r1;
       break;
@@ -822,6 +864,9 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
     case M32R_OPERAND_HI16 :
       value = fields->f_hi16;
       break;
+    case M32R_OPERAND_IMM1 :
+      value = fields->f_imm1;
+      break;
     case M32R_OPERAND_SCR :
       value = fields->f_r2;
       break;
@@ -879,6 +924,15 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      value = fields->f_acc;
+      break;
+    case M32R_OPERAND_ACCD :
+      value = fields->f_accd;
+      break;
+    case M32R_OPERAND_ACCS :
+      value = fields->f_accs;
+      break;
     case M32R_OPERAND_DCR :
       value = fields->f_r1;
       break;
@@ -900,6 +954,9 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
     case M32R_OPERAND_HI16 :
       value = fields->f_hi16;
       break;
+    case M32R_OPERAND_IMM1 :
+      value = fields->f_imm1;
+      break;
     case M32R_OPERAND_SCR :
       value = fields->f_r2;
       break;
@@ -961,6 +1018,15 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      fields->f_acc = value;
+      break;
+    case M32R_OPERAND_ACCD :
+      fields->f_accd = value;
+      break;
+    case M32R_OPERAND_ACCS :
+      fields->f_accs = value;
+      break;
     case M32R_OPERAND_DCR :
       fields->f_r1 = value;
       break;
@@ -981,6 +1047,9 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
     case M32R_OPERAND_HI16 :
       fields->f_hi16 = value;
       break;
+    case M32R_OPERAND_IMM1 :
+      fields->f_imm1 = value;
+      break;
     case M32R_OPERAND_SCR :
       fields->f_r2 = value;
       break;
@@ -1035,6 +1104,15 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      fields->f_acc = value;
+      break;
+    case M32R_OPERAND_ACCD :
+      fields->f_accd = value;
+      break;
+    case M32R_OPERAND_ACCS :
+      fields->f_accs = value;
+      break;
     case M32R_OPERAND_DCR :
       fields->f_r1 = value;
       break;
@@ -1055,6 +1133,9 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
     case M32R_OPERAND_HI16 :
       fields->f_hi16 = value;
       break;
+    case M32R_OPERAND_IMM1 :
+      fields->f_imm1 = value;
+      break;
     case M32R_OPERAND_SCR :
       fields->f_r2 = value;
       break;
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index d4504fe..a1efecc 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -93,11 +93,15 @@ static const CGEN_IFMT ifmt_cmpi = {
   32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
+static const CGEN_IFMT ifmt_cmpz = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
 static const CGEN_IFMT ifmt_div = {
   32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
-static const CGEN_IFMT ifmt_jl = {
+static const CGEN_IFMT ifmt_jc = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
@@ -109,10 +113,18 @@ static const CGEN_IFMT ifmt_ldi16 = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
 };
 
+static const CGEN_IFMT ifmt_machi_a = {
+  16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
+};
+
 static const CGEN_IFMT ifmt_mvfachi = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
+static const CGEN_IFMT ifmt_mvfachi_a = {
+  16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
+};
+
 static const CGEN_IFMT ifmt_mvfc = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
@@ -121,6 +133,10 @@ static const CGEN_IFMT ifmt_mvtachi = {
   16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
+static const CGEN_IFMT ifmt_mvtachi_a = {
+  16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
+};
+
 static const CGEN_IFMT ifmt_mvtc = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
@@ -129,6 +145,10 @@ static const CGEN_IFMT ifmt_nop = {
   16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
 };
 
+static const CGEN_IFMT ifmt_rac_dsi = {
+  16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
 static const CGEN_IFMT ifmt_seth = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
 };
@@ -145,6 +165,10 @@ static const CGEN_IFMT ifmt_trap = {
   16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
 };
 
+static const CGEN_IFMT ifmt_satb = {
+  32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
+};
+
 #undef F
 
 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
@@ -298,6 +322,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DISP24), 0 } },
     & ifmt_bc24, { 0xfe000000 }
   },
+/* bcl.s $disp8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
+    & ifmt_bc8, { 0x7800 }
+  },
+/* bcl.l $disp24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
+    & ifmt_bc24, { 0xf8000000 }
+  },
 /* bnc.s $disp8 */
   {
     { 0, 0, 0, 0 },
@@ -328,6 +364,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DISP24), 0 } },
     & ifmt_bc24, { 0xff000000 }
   },
+/* bncl.s $disp8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
+    & ifmt_bc8, { 0x7900 }
+  },
+/* bncl.l $disp24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
+    & ifmt_bc24, { 0xf9000000 }
+  },
 /* cmp $src1,$src2 */
   {
     { 0, 0, 0, 0 },
@@ -352,6 +400,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
     & ifmt_cmpi, { 0x80500000 }
   },
+/* cmpeq $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_cmp, { 0x60 }
+  },
+/* cmpz $src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC2), 0 } },
+    & ifmt_cmpz, { 0x70 }
+  },
 /* div $dr,$sr */
   {
     { 0, 0, 0, 0 },
@@ -376,17 +436,35 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     & ifmt_div, { 0x90300000 }
   },
+/* divh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90000010 }
+  },
+/* jc $sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
+    & ifmt_jc, { 0x1cc0 }
+  },
+/* jnc $sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
+    & ifmt_jc, { 0x1dc0 }
+  },
 /* jl $sr */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SR), 0 } },
-    & ifmt_jl, { 0x1ec0 }
+    & ifmt_jc, { 0x1ec0 }
   },
 /* jmp $sr */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SR), 0 } },
-    & ifmt_jl, { 0x1fc0 }
+    & ifmt_jc, { 0x1fc0 }
   },
 /* ld $dr,@$sr */
   {
@@ -484,24 +562,48 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3040 }
   },
+/* machi $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3040 }
+  },
 /* maclo $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3050 }
   },
+/* maclo $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3050 }
+  },
 /* macwhi $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3060 }
   },
+/* macwhi $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3060 }
+  },
 /* macwlo $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3070 }
   },
+/* macwlo $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3070 }
+  },
 /* mul $dr,$sr */
   {
     { 0, 0, 0, 0 },
@@ -514,24 +616,48 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3000 }
   },
+/* mulhi $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3000 }
+  },
 /* mullo $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3010 }
   },
+/* mullo $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3010 }
+  },
 /* mulwhi $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3020 }
   },
+/* mulwhi $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3020 }
+  },
 /* mulwlo $src1,$src2 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x3030 }
   },
+/* mulwlo $src1,$src2,$acc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+    & ifmt_machi_a, { 0x3030 }
+  },
 /* mv $dr,$sr */
   {
     { 0, 0, 0, 0 },
@@ -544,18 +670,36 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DR), 0 } },
     & ifmt_mvfachi, { 0x50f0 }
   },
+/* mvfachi $dr,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+    & ifmt_mvfachi_a, { 0x50f0 }
+  },
 /* mvfaclo $dr */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DR), 0 } },
     & ifmt_mvfachi, { 0x50f1 }
   },
+/* mvfaclo $dr,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+    & ifmt_mvfachi_a, { 0x50f1 }
+  },
 /* mvfacmi $dr */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DR), 0 } },
     & ifmt_mvfachi, { 0x50f2 }
   },
+/* mvfacmi $dr,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+    & ifmt_mvfachi_a, { 0x50f2 }
+  },
 /* mvfc $dr,$scr */
   {
     { 0, 0, 0, 0 },
@@ -568,12 +712,24 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), 0 } },
     & ifmt_mvtachi, { 0x5070 }
   },
+/* mvtachi $src1,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+    & ifmt_mvtachi_a, { 0x5070 }
+  },
 /* mvtaclo $src1 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRC1), 0 } },
     & ifmt_mvtachi, { 0x5071 }
   },
+/* mvtaclo $src1,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+    & ifmt_mvtachi_a, { 0x5071 }
+  },
 /* mvtc $sr,$dcr */
   {
     { 0, 0, 0, 0 },
@@ -604,12 +760,24 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, 0 } },
     & ifmt_nop, { 0x5090 }
   },
+/* rac $accd,$accs,$imm1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+    & ifmt_rac_dsi, { 0x5090 }
+  },
 /* rach */
   {
     { 0, 0, 0, 0 },
     { { MNEM, 0 } },
     & ifmt_nop, { 0x5080 }
   },
+/* rach $accd,$accs,$imm1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+    & ifmt_rac_dsi, { 0x5080 }
+  },
 /* rte */
   {
     { 0, 0, 0, 0 },
@@ -754,6 +922,72 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x2050 }
   },
+/* satb $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_satb, { 0x80600300 }
+  },
+/* sath $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_satb, { 0x80600200 }
+  },
+/* sat $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_satb, { 0x80600000 }
+  },
+/* pcmpbz $src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC2), 0 } },
+    & ifmt_cmpz, { 0x370 }
+  },
+/* sadd */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x50e4 }
+  },
+/* macwu1 $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_cmp, { 0x50b0 }
+  },
+/* msblo $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_cmp, { 0x50d0 }
+  },
+/* mulwu1 $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_cmp, { 0x50a0 }
+  },
+/* maclh1 $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_cmp, { 0x50c0 }
+  },
+/* sc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x7401 }
+  },
+/* snc */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_nop, { 0x7501 }
+  },
 };
 
 #undef A
@@ -781,6 +1015,14 @@ static const CGEN_IFMT ifmt_bl24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
+static const CGEN_IFMT ifmt_bcl8r = {
+  16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT ifmt_bcl24r = {
+  32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
 static const CGEN_IFMT ifmt_bnc8r = {
   16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
 };
@@ -797,6 +1039,14 @@ static const CGEN_IFMT ifmt_bra24r = {
   32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
 };
 
+static const CGEN_IFMT ifmt_bncl8r = {
+  16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT ifmt_bncl24r = {
+  32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
 static const CGEN_IFMT ifmt_ld_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
 };
@@ -849,6 +1099,22 @@ static const CGEN_IFMT ifmt_ldi16a = {
   32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 }
 };
 
+static const CGEN_IFMT ifmt_rac_d = {
+  16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+static const CGEN_IFMT ifmt_rac_ds = {
+  16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+static const CGEN_IFMT ifmt_rach_d = {
+  16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+static const CGEN_IFMT ifmt_rach_ds = {
+  16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
 static const CGEN_IFMT ifmt_st_2 = {
   16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
 };
@@ -893,142 +1159,182 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bc $disp8 */
   {
     -1, "bc8r", "bc", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bc $disp24 */
   {
     -1, "bc24r", "bc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bl $disp8 */
   {
     -1, "bl8r", "bl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bl $disp24 */
   {
     -1, "bl24r", "bl", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bcl $disp8 */
+  {
+    -1, "bcl8r", "bcl", 16,
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bcl $disp24 */
+  {
+    -1, "bcl24r", "bcl", 32,
+    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* bnc $disp8 */
   {
     -1, "bnc8r", "bnc", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bnc $disp24 */
   {
     -1, "bnc24r", "bnc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bra $disp8 */
   {
     -1, "bra8r", "bra", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bra $disp24 */
   {
     -1, "bra24r", "bra", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bncl $disp8 */
+  {
+    -1, "bncl8r", "bncl", 16,
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bncl $disp24 */
+  {
+    -1, "bncl24r", "bncl", 32,
+    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* ld $dr,@($sr) */
   {
     -1, "ld-2", "ld", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld $dr,@($sr,$slo16) */
   {
     -1, "ld-d2", "ld", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldb $dr,@($sr) */
   {
     -1, "ldb-2", "ldb", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldb $dr,@($sr,$slo16) */
   {
     -1, "ldb-d2", "ldb", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldh $dr,@($sr) */
   {
     -1, "ldh-2", "ldh", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldh $dr,@($sr,$slo16) */
   {
     -1, "ldh-d2", "ldh", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldub $dr,@($sr) */
   {
     -1, "ldub-2", "ldub", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldub $dr,@($sr,$slo16) */
   {
     -1, "ldub-d2", "ldub", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* lduh $dr,@($sr) */
   {
     -1, "lduh-2", "lduh", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* lduh $dr,@($sr,$slo16) */
   {
     -1, "lduh-d2", "lduh", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* pop $dr */
   {
     -1, "pop", "pop", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldi $dr,$simm8 */
   {
     -1, "ldi8a", "ldi", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
   },
 /* ldi $dr,$hash$slo16 */
   {
     -1, "ldi16a", "ldi", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* rac $accd */
+  {
+    -1, "rac-d", "rac", 16,
+    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* rac $accd,$accs */
+  {
+    -1, "rac-ds", "rac", 16,
+    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* rach $accd */
+  {
+    -1, "rach-d", "rach", 16,
+    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* rach $accd,$accs */
+  {
+    -1, "rach-ds", "rach", 16,
+    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* st $src1,@($src2) */
   {
     -1, "st-2", "st", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@($src2,$slo16) */
   {
     -1, "st-d2", "st", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* stb $src1,@($src2) */
   {
     -1, "stb-2", "stb", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* stb $src1,@($src2,$slo16) */
   {
     -1, "stb-d2", "stb", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* sth $src1,@($src2) */
   {
     -1, "sth-2", "sth", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* sth $src1,@($src2,$slo16) */
   {
     -1, "sth-d2", "sth", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* push $src1 */
   {
     -1, "push", "push", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 };
 
@@ -1060,6 +1366,18 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
     { { MNEM, ' ', OP (DISP24), 0 } },
     & ifmt_bl24r, { 0xfe000000 }
   },
+/* bcl $disp8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
+    & ifmt_bcl8r, { 0x7800 }
+  },
+/* bcl $disp24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
+    & ifmt_bcl24r, { 0xf8000000 }
+  },
 /* bnc $disp8 */
   {
     { 0, 0, 0, 0 },
@@ -1084,6 +1402,18 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
     { { MNEM, ' ', OP (DISP24), 0 } },
     & ifmt_bra24r, { 0xff000000 }
   },
+/* bncl $disp8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
+    & ifmt_bncl8r, { 0x7900 }
+  },
+/* bncl $disp24 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
+    & ifmt_bncl24r, { 0xf9000000 }
+  },
 /* ld $dr,@($sr) */
   {
     { 0, 0, 0, 0 },
@@ -1162,6 +1492,30 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
     & ifmt_ldi16a, { 0x90f00000 }
   },
+/* rac $accd */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), 0 } },
+    & ifmt_rac_d, { 0x5090 }
+  },
+/* rac $accd,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+    & ifmt_rac_ds, { 0x5090 }
+  },
+/* rach $accd */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), 0 } },
+    & ifmt_rach_d, { 0x5080 }
+  },
+/* rach $accd,$accs */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+    & ifmt_rach_ds, { 0x5080 }
+  },
 /* st $src1,@($src2) */
   {
     { 0, 0, 0, 0 },
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 6c57daa..f92a332 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -47,37 +47,34 @@ typedef enum cgen_insn_type {
  , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
- , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
- , M32R_INSN_BRA24
- , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
- , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
- , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
- , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
- , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
- , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
- , M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACLO
- , M32R_INSN_MACWHI
- , M32R_INSN_MACWLO
- , M32R_INSN_MUL, M32R_INSN_MULHI
- , M32R_INSN_MULLO
- , M32R_INSN_MULWHI
- , M32R_INSN_MULWLO
- , M32R_INSN_MV, M32R_INSN_MVFACHI
- , M32R_INSN_MVFACLO
- , M32R_INSN_MVFACMI
- , M32R_INSN_MVFC, M32R_INSN_MVTACHI
- , M32R_INSN_MVTACLO
+ , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24
+ , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
+ , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
+ , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
+ , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
+ , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
+ , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
+ , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
+ , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
+ , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
+ , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
+ , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
+ , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
+ , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
+ , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
+ , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
  , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC
- , M32R_INSN_RACH
+ , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
  , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
  , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
  , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
  , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
  , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
  , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_MAX
+ , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
+ , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
+ , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
@@ -107,6 +104,14 @@ struct cgen_fields
   long f_disp8;
   long f_disp16;
   long f_disp24;
+  long f_op23;
+  long f_op3;
+  long f_acc;
+  long f_accs;
+  long f_accd;
+  long f_bits67;
+  long f_bit14;
+  long f_imm1;
 };
 
 #define CGEN_INIT_PARSE(od) \
diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c
index f9d1e31..269651f 100644
--- a/opcodes/m32r-opinst.c
+++ b/opcodes/m32r-opinst.c
@@ -146,6 +146,24 @@ static const CGEN_OPINST sfmt_bl24_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_bcl8_ops[] = {
+  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_bcl24_ops[] = {
+  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_bra8_ops[] = {
   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
@@ -172,6 +190,12 @@ static const CGEN_OPINST sfmt_cmpi_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_cmpz_ops[] = {
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_div_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
@@ -179,6 +203,13 @@ static const CGEN_OPINST sfmt_div_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_jc_ops[] = {
+  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_jl_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
@@ -250,6 +281,14 @@ static const CGEN_OPINST sfmt_machi_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_machi_a_ops[] = {
+  { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_mulhi_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
@@ -257,6 +296,13 @@ static const CGEN_OPINST sfmt_mulhi_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_mv_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
@@ -269,6 +315,12 @@ static const CGEN_OPINST sfmt_mvfachi_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
+  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
+  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_mvfc_ops[] = {
   { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
@@ -282,6 +334,13 @@ static const CGEN_OPINST sfmt_mvtachi_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
+  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_mvtc_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
@@ -298,6 +357,13 @@ static const CGEN_OPINST sfmt_rac_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
+  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
+  { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
+  { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
+  { END }
+};
+
 static const CGEN_OPINST sfmt_rte_ops[] = {
   { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
   { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
@@ -407,6 +473,46 @@ static const CGEN_OPINST sfmt_unlock_ops[] = {
   { END }
 };
 
+static const CGEN_OPINST sfmt_satb_ops[] = {
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
+  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_sat_ops[] = {
+  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
+  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_sadd_ops[] = {
+  { INPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
+  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
+  { OUTPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_macwu1_ops[] = {
+  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_mulwu1_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
+  { END }
+};
+
+static const CGEN_OPINST sfmt_sc_ops[] = {
+  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { END }
+};
+
 #undef INPUT
 #undef OUTPUT
 #undef END
@@ -440,19 +546,28 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_beqz_ops[0],
   & sfmt_bl8_ops[0],
   & sfmt_bl24_ops[0],
+  & sfmt_bcl8_ops[0],
+  & sfmt_bcl24_ops[0],
   & sfmt_bc8_ops[0],
   & sfmt_bc24_ops[0],
   & sfmt_beq_ops[0],
   & sfmt_bra8_ops[0],
   & sfmt_bra24_ops[0],
+  & sfmt_bcl8_ops[0],
+  & sfmt_bcl24_ops[0],
   & sfmt_cmp_ops[0],
   & sfmt_cmpi_ops[0],
   & sfmt_cmp_ops[0],
   & sfmt_cmpi_ops[0],
+  & sfmt_cmp_ops[0],
+  & sfmt_cmpz_ops[0],
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_jc_ops[0],
+  & sfmt_jc_ops[0],
   & sfmt_jl_ops[0],
   & sfmt_jmp_ops[0],
   & sfmt_ld_ops[0],
@@ -471,27 +586,42 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_ldi16_ops[0],
   & sfmt_lock_ops[0],
   & sfmt_machi_ops[0],
+  & sfmt_machi_a_ops[0],
   & sfmt_machi_ops[0],
+  & sfmt_machi_a_ops[0],
   & sfmt_machi_ops[0],
+  & sfmt_machi_a_ops[0],
   & sfmt_machi_ops[0],
+  & sfmt_machi_a_ops[0],
   & sfmt_add_ops[0],
   & sfmt_mulhi_ops[0],
+  & sfmt_mulhi_a_ops[0],
   & sfmt_mulhi_ops[0],
+  & sfmt_mulhi_a_ops[0],
   & sfmt_mulhi_ops[0],
+  & sfmt_mulhi_a_ops[0],
   & sfmt_mulhi_ops[0],
+  & sfmt_mulhi_a_ops[0],
   & sfmt_mv_ops[0],
   & sfmt_mvfachi_ops[0],
+  & sfmt_mvfachi_a_ops[0],
   & sfmt_mvfachi_ops[0],
+  & sfmt_mvfachi_a_ops[0],
   & sfmt_mvfachi_ops[0],
+  & sfmt_mvfachi_a_ops[0],
   & sfmt_mvfc_ops[0],
   & sfmt_mvtachi_ops[0],
+  & sfmt_mvtachi_a_ops[0],
   & sfmt_mvtachi_ops[0],
+  & sfmt_mvtachi_a_ops[0],
   & sfmt_mvtc_ops[0],
   & sfmt_mv_ops[0],
   & sfmt_nop_ops[0],
   & sfmt_mv_ops[0],
   & sfmt_rac_ops[0],
+  & sfmt_rac_dsi_ops[0],
   & sfmt_rac_ops[0],
+  & sfmt_rac_dsi_ops[0],
   & sfmt_rte_ops[0],
   & sfmt_seth_ops[0],
   & sfmt_add_ops[0],
@@ -516,6 +646,17 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_addx_ops[0],
   & sfmt_trap_ops[0],
   & sfmt_unlock_ops[0],
+  & sfmt_satb_ops[0],
+  & sfmt_satb_ops[0],
+  & sfmt_sat_ops[0],
+  & sfmt_cmpz_ops[0],
+  & sfmt_sadd_ops[0],
+  & sfmt_macwu1_ops[0],
+  & sfmt_machi_ops[0],
+  & sfmt_mulwu1_ops[0],
+  & sfmt_macwu1_ops[0],
+  & sfmt_sc_ops[0],
+  & sfmt_sc_ops[0],
 };
 
 /* Function to call before using the operand instance table.  */