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| author | David S. Miller <davem@redhat.com> | 2012-04-27 18:04:00 +0000 |
|---|---|---|
| committer | David S. Miller <davem@redhat.com> | 2012-04-27 18:04:00 +0000 |
| commit | 58004e23c9b5405fa07f4fbf63cc88d5ad710f66 (patch) | |
| tree | d140d475f9cb121c231a4ad6cb01d6916d5a7b1b /opcodes | |
| parent | fa66ec5377f31b68ca9554d47166632c6d6d8e37 (diff) | |
| download | gdb-58004e23c9b5405fa07f4fbf63cc88d5ad710f66.zip gdb-58004e23c9b5405fa07f4fbf63cc88d5ad710f66.tar.gz gdb-58004e23c9b5405fa07f4fbf63cc88d5ad710f66.tar.bz2 | |
Add support for sparc pause instruction.
opcodes/
* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
gas/
* config/tc-sparc.c (sparc_arch_table): Add HWCAP_PAUSE to sparc4,
v8pluse, v8plusv, v9e, and v9v.
(v9a_asr_table): Add 'pause'.
gas/testsuite/
* gas/sparc/sparc.exp: Run pause test.
* gas/sparc/pause.s: New testcase.
* gas/sparc/pause.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 3 | ||||
| -rw-r--r-- | opcodes/sparc-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/sparc-opc.c | 4 |
3 files changed, 8 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c20461b..43f4a9d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,8 @@ 2012-04-27 David S. Miller <davem@davemloft.net> + * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. + * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. + * sparc-opc.c (CBCOND): New define. (CBCOND_XCC): Likewise. (cbcond): New helper macro. diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c index bda1b0d..7599f89 100644 --- a/opcodes/sparc-dis.c +++ b/opcodes/sparc-dis.c @@ -109,7 +109,7 @@ static char *v9a_asr_reg_names[] = { "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26", - "resv27", "cps" + "pause", "cps" }; /* Macros used to extract instruction fields. Not all fields have diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index d83b49d..1f9ee49 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -876,9 +876,13 @@ const struct sparc_opcode sparc_opcodes[] = { { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */ { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */ { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */ +{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */ +{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */ { "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */ { "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */ +{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, v9b }, /* wr %g0,i,%pause */ + { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, v8 }, /* rd %asrX,r */ { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, v6 }, /* rd %y,r */ { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, v6notv9 }, /* rd %psr,r */ |