Merge drow-cplus-merge-20040208 to drow-cplus-branch.

9 files changed, 56 insertions, 23 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index df95ada..c8a2ded 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,36 @@
+2004-01-27  Michael Snyder  <msnyder@redhat.com>
+
+	* sh-opc.h (sh_table): "fsrra", not "fssra".
+
+2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
+
+	* sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
+	contraints.
+
+2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
+
+	* sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
+
+2004-01-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (OP_E): Print scale factor on intel mode sib when not
+	1.  Don't print scale factor on AT&T mode when index missing.
+
+2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
+
+	* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
+	when loaded into XR registers.
+
+2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frv-desc.h: Regenerate.
+	* frv-desc.c: Regenerate.
+	* frv-opc.c: Regenerate.
+
+2004-01-13  Michael Snyder  <msnyder@redhat.com>
+
+	* sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
+
 2004-01-09  Paul Brook  <paul@codesourcery.com>
 
 	* arm-opc.h (arm_opcodes): Move generic mcrr after known
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index 9cc85fe..35659c7 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -84,6 +84,7 @@ static const CGEN_ATTR_ENTRY UNIT_attr[] =
   { "B01", UNIT_B01 },
   { "C", UNIT_C },
   { "MULT_DIV", UNIT_MULT_DIV },
+  { "IACC", UNIT_IACC },
   { "LOAD", UNIT_LOAD },
   { "STORE", UNIT_STORE },
   { "SCAN", UNIT_SCAN },
@@ -2397,17 +2398,17 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* smu$pack $GRi,$GRj */
   {
     FRV_INSN_SMU, "smu", "smu", 32,
-    { 0, { (1<<MACH_FR400), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* smass$pack $GRi,$GRj */
   {
     FRV_INSN_SMASS, "smass", "smass", 32,
-    { 0, { (1<<MACH_FR400), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* smsss$pack $GRi,$GRj */
   {
     FRV_INSN_SMSSS, "smsss", "smsss", 32,
-    { 0, { (1<<MACH_FR400), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* sll$pack $GRi,$GRj,$GRk */
   {
diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h
index 5f72800..f46c3f9 100644
--- a/opcodes/frv-desc.h
+++ b/opcodes/frv-desc.h
@@ -549,9 +549,9 @@ typedef enum unit_attr {
  , UNIT_I2, UNIT_I3, UNIT_IALL, UNIT_FM0
  , UNIT_FM1, UNIT_FM01, UNIT_FM2, UNIT_FM3
  , UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
- , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_LOAD
- , UNIT_STORE, UNIT_SCAN, UNIT_DCPL, UNIT_MDUALACC
- , UNIT_MCLRACC_1, UNIT_NUM_UNITS
+ , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC
+ , UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL
+ , UNIT_MDUALACC, UNIT_MCLRACC_1, UNIT_NUM_UNITS
 } UNIT_ATTR;
 
 /* Enum declaration for fr400 major insn categories.  */
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index 61bdb45..1560d20 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -239,6 +239,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
 /* B01      */     UNIT_B0,
 /* C        */     UNIT_C,
 /* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0  unit.  */
+/* IACC     */     UNIT_I01, /* iacc multiply       in I0 or I1 unit.  */
 /* LOAD     */     UNIT_I0,  /* load                only in I0  unit.  */
 /* STORE    */     UNIT_I0,  /* store               only in I0  unit.  */
 /* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
@@ -269,6 +270,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
 /* B01      */     UNIT_B01,
 /* C        */     UNIT_C,
 /* MULT-DIV */     UNIT_I01, /* multiply and divide in I0 or I1 unit.  */
+/* IACC     */     UNIT_NIL, /* iacc multiply       not implemented */
 /* LOAD     */     UNIT_I01, /* load                in I0 or I1 unit.  */
 /* STORE    */     UNIT_I0,  /* store               only in I0 unit.  */
 /* SCAN     */     UNIT_I01, /* scan                in I0 or I1 unit.  */
@@ -299,6 +301,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
 /* B01      */     UNIT_B01,
 /* C        */     UNIT_C,
 /* MULT-DIV */     UNIT_I01,  /* multiply and divide in I0 or I1 unit.    */
+/* IACC     */     UNIT_NIL,  /* iacc multiply       not implemented.     */
 /* LOAD     */     UNIT_I01,  /* load                in I0 or I1 unit.    */
 /* STORE    */     UNIT_I01,  /* store               in I0 or I1 unit.    */
 /* SCAN     */     UNIT_IALL, /* scan                in any integer unit. */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 0ef57ef..f9a0a9b 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3173,11 +3173,7 @@ OP_E (int bytemode, int sizeflag)
 			     ? names64[index] : names32[index]);
 		  oappend (scratchbuf);
 		}
-	      if (!intel_syntax
-		  || (intel_syntax
-		      && bytemode != b_mode
-		      && bytemode != w_mode
-		      && bytemode != v_mode))
+	      if (scale != 0 || (!intel_syntax && index != 4))
 		{
 		  *obufp++ = scale_char;
 		  *obufp = '\0';
diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index d1a2ea2..4082b29 100644
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -1,5 +1,5 @@
 /* Assemble Matsushita MN10300 instructions.
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2004 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -561,8 +561,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0xfb080000,  0xffff0000,  0,    FMT_D7, AM33,	{SIMM8, RN02}},
 { "mov",	0xfd080000,  0xffff0000,  0,    FMT_D8, AM33,	{SIMM24, RN02}},
 { "mov",	0xfe080000,  0xffff0000,  0,    FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
-{ "mov",	0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,	{SIMM8, XRN02}},
-{ "mov",	0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,	{SIMM24, XRN02}},
+{ "mov",	0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,	{IMM8, XRN02}},
+{ "mov",	0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,	{IMM24, XRN02}},
 { "mov",	0xfef80000,  0xffff0000,  0,    FMT_D9, AM33,	{IMM32_HIGH8, XRN02}},
 { "mov",	0xfe0e0000,  0xffff0f00,  0,    FMT_D9, AM33,	{MEM(IMM32_HIGH8_MEM), RN2}},
 { "mov",	0xfe1e0000,  0xffff0f00,  0,    FMT_D9, AM33,	{RM2, MEM(IMM32_HIGH8_MEM)}},
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index c0e1a2e..70fdffb 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -397,7 +397,7 @@ print_insn_sh (memaddr, info)
 {
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
-  unsigned char insn[2];
+  unsigned char insn[4];
   unsigned char nibs[4];
   int status;
   bfd_vma relmask = ~(bfd_vma) 0;
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index b9e103c..4b0b0a8 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -935,7 +935,7 @@ const sh_opcode_info sh_table[] =
 /* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
 /* 1111nnnn01101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
 
-/* 1111nnnn01111101 fssra <F_REG_N>    */{"fssra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4a_up},
+/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4a_up},
 
 /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
 
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 0010232..22f18fa 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1,6 +1,6 @@
 /* Table of opcodes for the sparc.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000
+   2000, 2002, 2004
    Free Software Foundation, Inc.
 
 This file is part of the BFD library.
@@ -1525,17 +1525,17 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 { "fstoi",	F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
 { "fqtoi",	F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
 
-{ "fdtox",	F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },
-{ "fstox",	F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },
-{ "fqtox",	F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 },
+{ "fdtox",	F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
+{ "fstox",	F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
+{ "fqtox",	F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
 
 { "fitod",	F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
 { "fitos",	F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
 { "fitoq",	F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
 
-{ "fxtod",	F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },
-{ "fxtos",	F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },
-{ "fxtoq",	F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 },
+{ "fxtod",	F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
+{ "fxtos",	F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
+{ "fxtoq",	F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
 
 { "fdtoq",	F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
 { "fdtos",	F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },