diff options
| author | Jeff Law <law@redhat.com> | 1996-12-10 20:34:14 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-12-10 20:34:14 +0000 |
| commit | 7bfc95d9175e2d3cdf44a013492ae54af4318063 (patch) | |
| tree | faca20685294568c279fed5dd57a4560ea217ae5 /opcodes | |
| parent | 3b159258ad6555fec451a7277aa580656717bf2e (diff) | |
| download | gdb-7bfc95d9175e2d3cdf44a013492ae54af4318063.zip gdb-7bfc95d9175e2d3cdf44a013492ae54af4318063.tar.gz gdb-7bfc95d9175e2d3cdf44a013492ae54af4318063.tar.bz2 | |
* mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
instruction. Fix opcode field for "movb (imm24),dn".
Stuff found by the testsuite.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 3 | ||||
| -rw-r--r-- | opcodes/mn10200-opc.c | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f46d3da..5db149a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,8 @@ Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) + * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 + instruction. Fix opcode field for "movb (imm24),dn". + * mn10200-opc.c (mn10200_operands): Fix insertion position for DI operand. diff --git a/opcodes/mn10200-opc.c b/opcodes/mn10200-opc.c index e52c869..ba4da2a 100644 --- a/opcodes/mn10200-opc.c +++ b/opcodes/mn10200-opc.c @@ -155,7 +155,7 @@ const struct mn10200_operand mn10200_operands[] = { sorted by major opcode. */ const struct mn10200_opcode mn10200_opcodes[] = { -{ "mov", 0x8000, 0xfc00, FMT_5, {SIMM8, DN01}}, +{ "mov", 0x8000, 0xfc00, FMT_2, {SIMM8, DN01}}, { "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, { "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, @@ -206,7 +206,7 @@ const struct mn10200_opcode mn10200_opcodes[] = { { "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, { "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, { "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, -{ "movb", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, +{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, { "movb", 0x10, 0xf0, FMT_1, {DM1, MEM(AN0)}}, { "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, { "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, |