diff options
| author | David Carlton <carlton@bactrian.org> | 2003-06-27 21:50:37 +0000 |
|---|---|---|
| committer | David Carlton <carlton@bactrian.org> | 2003-06-27 21:50:37 +0000 |
| commit | 3abe3bc90be798445086f45d9c3723165cc6c893 (patch) | |
| tree | 20de3690d32dbb68a1e4266dfd13575be97ea40e /opcodes | |
| parent | c8a2fad7b41a8264964233608ae10c35918243fb (diff) | |
| download | gdb-3abe3bc90be798445086f45d9c3723165cc6c893.zip gdb-3abe3bc90be798445086f45d9c3723165cc6c893.tar.gz gdb-3abe3bc90be798445086f45d9c3723165cc6c893.tar.bz2 | |
2003-06-27 David Carlton <carlton@kealia.com>
* Merge with mainline; tag is carlton_dictionary-20030627-merge.
Diffstat (limited to 'opcodes')
47 files changed, 3198 insertions, 1846 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index de8f363..d0806c4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,121 @@ +2003-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in + Intel Precott New Instructions. + (PREGRP27): New. Added for "addsubpd" and "addsubps". + (PREGRP28): New. Added for "haddpd" and "haddps". + (PREGRP29): New. Added for "hsubpd" and "hsubps". + (PREGRP30): New. Added for "movsldup" and "movddup". + (PREGRP31): New. Added for "movshdup" and "movhpd". + (PREGRP32): New. Added for "lddqu". + (dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry. + Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for + entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for + entry 0xd0. Use PREGRP32 for entry 0xf0. + (twobyte_has_modrm): Updated. + (twobyte_uses_SSE_prefix): Likewise. + (grps): Use PNI_Fixup in the "sidtQ" entry. + (prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30, + PREGRP31 and PREGRP32. + (float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb. + Use "fisttpll" in entry 1 in opcode 0xdd. + Use "fisttp" in entry 1 in opcode 0xdf. + +2003-06-19 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (instr_data_s): Change tabl_index from long to int. + (print_insn_z8k): Correctly check return value from + z8k_lookup_instr call. + (unparse_instr): Handle CLASS_IRO case. + * z8kgen.c: Fix function definitions. Fix formatting. + (opt): Add brk opcode alias for non-simulator breakpoint. Add + missing and fix existing in/out and sin/sout opcode definitions. + (args): "@ri", "@ro" - add CLASS_IRO register usage for in/out + opcodes. + (internal): Check p->flags for non-zero before dereferencing it. + (gas): Add CLASS_IRO line. Insert new OPC_xxx lines for the added + opcodes and renumber the remaining lines repectively. + (main): Remove "-d" command line switch. + * z8k-opc.h: Regenerate with new z8kgen.c. + +2003-06-11 H.J. Lu <hongjiu.lu@intel.com> + + * po/Make-in (DESTDIR): New. + (install-data-yes): Support $(DESTDIR). + (uninstall): Likewise. + +2003-06-11 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2003-06-10 Doug Evans <dje@sebabeach.org> + + * cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to + CGEN_INSN_RELAXED. + * fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate. + * frv-asm.c,frv-desc.c,frv-desc.h: Regenerate. + * ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate. + * iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate. + * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate. + * openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate. + * xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate. + +2003-06-10 Gary Hade <garyhade@us.ibm.com> + Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define. + (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New. + (powerpc_opcodes): Add "attn", "lq" and "stq". + +2003-06-10 Richard Sandiford <rsandifo@redhat.com> + + * h8300-dis.c (bfd_h8_disassemble): Don't print brackets round + rts/l and rte/l register lists. + +2003-06-03 Nick Clifton <nickc@redhat.com> + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-asm.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.h: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-06-03 Michael Snyder <msnyder@redhat.com> + and Bernd Schmidt <bernds@redhat.com> + and Alexandre Oliva <aoliva@redhat.com> + + * disassemble.c (disassembler): Add support for h8300sx. + * h8300-dis.c: Ditto. + +2003-06-03 Nick Clifton <nickc@redhat.com> + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-desc.c: Regenerate. + * iq2000-desc.h: Regenerate. + * iq2000-dis.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * iq2000-opc.c: Regenerate. + * iq2000-opc.h: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-05-23 Jason Eckhardt <jle@rice.edu> + + * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3. + (print_insn_i860): Grab 4 bits of the control register field + instead of 3. + 2003-05-18 Jason Eckhardt <jle@rice.edu> * i860-dis.c (print_insn_i860): Instruction shrd has a dual bit, @@ -5,9 +123,9 @@ 2003-05-17 Andreas Jaeger <aj@suse.de> - * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. - (libopcodes_la_DEPENDENCIES): Add libbfd.la. - * Makefile.in: Regenerated. + * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. + (libopcodes_la_DEPENDENCIES): Add libbfd.la. + * Makefile.in: Regenerated. 2003-05-16 Nick Clifton <nickc@redhat.com> @@ -71,7 +189,7 @@ 2003-03-25 Stan Cox <scox@redhat.com> Nick Clifton <nickc@redhat.com> - + Contribute support for Intel's iWMMXt chip - an ARM variant: * arm-dis.c (regnames): Add iWMMXt register names. @@ -179,24 +297,24 @@ 2002-01-02 Ben Elliston <bje@redhat.com> Jeff Johnston <jjohnstn@redhat.com> - * iq2000-asm.c: New file. - * iq2000-desc.c: Likewise. - * iq2000-desc.h: Likewise. - * iq2000-dis.c: Likewise. - * iq2000-ibld.c: Likewise. - * iq2000-opc.c: Likewise. - * iq2000-opc.h: Likewise. - * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. - (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, - iq2000-ibld.c, iq2000-opc.c. - (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, - iq2000-ibld.lo, iq2000-opc.lo. - (CLEANFILES): Add stamp-iq2000. - (IQ2000_DEPS): New macro. - (stamp-iq2000): New target. - * Makefile.in: Regenerate. - * configure.in: Handle bfd_iq2000_arch. - * configure: Regenerate. + * iq2000-asm.c: New file. + * iq2000-desc.c: Likewise. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * iq2000-opc.c: Likewise. + * iq2000-opc.h: Likewise. + * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. + (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c. + (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, + iq2000-ibld.lo, iq2000-opc.lo. + (CLEANFILES): Add stamp-iq2000. + (IQ2000_DEPS): New macro. + (stamp-iq2000): New target. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_iq2000_arch. + * configure: Regenerate. 2003-01-02 Chris Demetriou <cgd@broadcom.com> @@ -392,7 +510,7 @@ (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate. - + 2002-11-25 Aldy Hernandez <aldyh@redhat.com> * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa, @@ -470,7 +588,7 @@ * xstormy16-desc.c: Regenerate. * xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate. - + 2002-11-18 Klee Dienes <kdienes@apple.com> * avr-dis.c: Include libiberty.h (for xmalloc). @@ -552,18 +670,18 @@ 2002-11-07 Klee Dienes <kdienes@apple.com> - * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' - argument to ia64-gen. + * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' + argument to ia64-gen. Regenerate dependencies for ia64-len.lo. * Makefile.in: Regenerate. - * ia64-gen.c: Convert to use getopt(). Add the standard GNU - options, as well as '--srcdir', which controls the directory in - which ia64-gen looks for the sources it uses to generate the - output table. Add a 'const' to the declaration of the final - output table. Call xmalloc_set_program_name to set the program - name. + * ia64-gen.c: Convert to use getopt(). Add the standard GNU + options, as well as '--srcdir', which controls the directory in + which ia64-gen looks for the sources it uses to generate the + output table. Add a 'const' to the declaration of the final + output table. Call xmalloc_set_program_name to set the program + name. * ia64-asmtab.c: Regenerate. - + 2002-11-07 Nick Clifton <nickc@redhat.com> * ia64-gen.c: Fix comment formatting and compile time warnings. @@ -577,7 +695,7 @@ 2002-11-06 Aldy Hernandez <aldyh@redhat.com> - * opcodes/ppc-opc.c: Change RD to RS for evmerge*. + * opcodes/ppc-opc.c: Change RD to RS for evmerge*. 2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu> @@ -592,10 +710,10 @@ at the end. 2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 6ec05e4..7097be0 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -649,10 +649,12 @@ iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ - iq2000-opc.h opintl.h $(INCDIR)/libiberty.h + iq2000-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ - $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \ + opintl.h iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 8c03c17..2823902 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -1,4 +1,4 @@ -# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am +# Makefile.in generated automatically by automake 1.4-p6 from Makefile.am # Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation @@ -467,7 +467,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = gtar +TAR = tar GZIP_ENV = --best SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS) @@ -1145,10 +1145,12 @@ iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ - iq2000-opc.h opintl.h $(INCDIR)/libiberty.h + iq2000-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ - $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \ + opintl.h iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4 index 184bf36..92732d3 100644 --- a/opcodes/aclocal.m4 +++ b/opcodes/aclocal.m4 @@ -35,6 +35,24 @@ AC_SUBST(bfdlibdir) AC_SUBST(bfdincludedir) ]) +#serial 1 +# This test replaces the one in autoconf. +# Currently this macro should have the same name as the autoconf macro +# because gettext's gettext.m4 (distributed in the automake package) +# still uses it. Otherwise, the use in gettext.m4 makes autoheader +# give these diagnostics: +# configure.in:556: AC_TRY_COMPILE was called before AC_ISC_POSIX +# configure.in:556: AC_TRY_RUN was called before AC_ISC_POSIX + +undefine([AC_ISC_POSIX]) + +AC_DEFUN([AC_ISC_POSIX], + [ + dnl This test replaces the obsolescent AC_ISC_POSIX kludge. + AC_CHECK_LIB(cposix, strerror, [LIBS="$LIBS -lcposix"]) + ] +) + # Do all the work for Automake. This macro actually does too much -- # some checks are only needed if your package does certain things. # But this isn't really a big deal. diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in index 525177c..1ea0768 100644 --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -361,10 +361,10 @@ const CGEN_INSN * if (! @arch@_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/config.in b/opcodes/config.in index 6355be0..5caef55 100644 --- a/opcodes/config.in +++ b/opcodes/config.in @@ -25,9 +25,6 @@ /* Define to `long' if <sys/types.h> doesn't define. */ #undef off_t -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - /* Define to `unsigned' if <sys/types.h> doesn't define. */ #undef size_t @@ -109,12 +106,6 @@ /* Define if you have the <sys/param.h> header file. */ #undef HAVE_SYS_PARAM_H -/* Define if you have the <sys/stat.h> header file. */ -#undef HAVE_SYS_STAT_H - -/* Define if you have the <sys/types.h> header file. */ -#undef HAVE_SYS_TYPES_H - /* Define if you have the <unistd.h> header file. */ #undef HAVE_UNISTD_H diff --git a/opcodes/configure b/opcodes/configure index bb07938..ae248d0 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -732,249 +732,49 @@ test "$host_alias" != "$target_alias" && NONENONEs,x,x, && program_prefix=${target_alias}- -# Extract the first word of "gcc", so it can be a program name with args. -set dummy gcc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:739: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="gcc" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - -if test -z "$CC"; then - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:769: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_prog_rejected=no - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue - fi - ac_cv_prog_CC="cc" - break - fi - done - IFS="$ac_save_ifs" -if test $ac_prog_rejected = yes; then - # We found a bogon in the path, so make sure we never use it. - set dummy $ac_cv_prog_CC - shift - if test $# -gt 0; then - # We chose a different compiler from the bogus one. - # However, it has the same basename, so the bogon will be chosen - # first if we set CC to just the basename; use the full file name. - shift - set dummy "$ac_dir/$ac_word" "$@" - shift - ac_cv_prog_CC="$@" - fi -fi -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - if test -z "$CC"; then - case "`uname -s`" in - *win32* | *WIN32*) - # Extract the first word of "cl", so it can be a program name with args. -set dummy cl; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:820: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "checking for strerror in -lcposix""... $ac_c" 1>&6 +echo "configure:738: checking for strerror in -lcposix" >&5 +ac_lib_var=`echo cposix'_'strerror | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="cl" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - ;; - esac - fi - test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } -fi - -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:852: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 - -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -cat > conftest.$ac_ext << EOF - -#line 863 "configure" + ac_save_LIBS="$LIBS" +LIBS="-lcposix $LIBS" +cat > conftest.$ac_ext <<EOF +#line 746 "configure" #include "confdefs.h" +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char strerror(); -main(){return(0);} +int main() { +strerror() +; return 0; } EOF -if { (eval echo configure:868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then - ac_cv_prog_cc_works=yes - # If we can't run a trivial program, we are probably using a cross compiler. - if (./conftest; exit) 2>/dev/null; then - ac_cv_prog_cc_cross=no - else - ac_cv_prog_cc_cross=yes - fi +if { (eval echo configure:757: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" else echo "configure: failed program was:" >&5 cat conftest.$ac_ext >&5 - ac_cv_prog_cc_works=no -fi -rm -fr conftest* -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 -if test $ac_cv_prog_cc_works = no; then - { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } -fi -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:894: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 -echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 -cross_compiling=$ac_cv_prog_cc_cross - -echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:899: checking whether we are using GNU C" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - cat > conftest.c <<EOF -#ifdef __GNUC__ - yes; -#endif -EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:908: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then - ac_cv_prog_gcc=yes -else - ac_cv_prog_gcc=no -fi -fi - -echo "$ac_t""$ac_cv_prog_gcc" 1>&6 - -if test $ac_cv_prog_gcc = yes; then - GCC=yes -else - GCC= -fi - -ac_test_CFLAGS="${CFLAGS+set}" -ac_save_CFLAGS="$CFLAGS" -CFLAGS= -echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:927: checking whether ${CC-cc} accepts -g" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - echo 'void f(){}' > conftest.c -if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then - ac_cv_prog_cc_g=yes -else - ac_cv_prog_cc_g=no + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" fi rm -f conftest* +LIBS="$ac_save_LIBS" fi - -echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 -if test "$ac_test_CFLAGS" = set; then - CFLAGS="$ac_save_CFLAGS" -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi - -echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 -echo "configure:959: checking for POSIXized ISC" >&5 -if test -d /etc/conf/kconfig.d && - grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 -then +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 - ISC=yes # If later tests want to check for ISC. - cat >> confdefs.h <<\EOF -#define _POSIX_SOURCE 1 -EOF - - if test "$GCC" = yes; then - CC="$CC -posix" - else - CC="$CC -Xp" - fi + LIBS="$LIBS -lcposix" else echo "$ac_t""no" 1>&6 - ISC= fi + + # We currently only use the version number for the name of any shared # library. For user convenience, we always use the same version @@ -993,7 +793,7 @@ BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${ # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:997: checking for a BSD compatible install" >&5 +echo "configure:797: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1046,7 +846,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6 -echo "configure:1050: checking whether build environment is sane" >&5 +echo "configure:850: checking whether build environment is sane" >&5 # Just in case sleep 1 echo timestamp > conftestfile @@ -1103,7 +903,7 @@ test "$program_suffix" != NONE && test "$program_transform_name" = "" && program_transform_name="s,x,x," echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 -echo "configure:1107: checking whether ${MAKE-make} sets \${MAKE}" >&5 +echo "configure:907: checking whether ${MAKE-make} sets \${MAKE}" >&5 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1149,7 +949,7 @@ EOF missing_dir=`cd $ac_aux_dir && pwd` echo $ac_n "checking for working aclocal""... $ac_c" 1>&6 -echo "configure:1153: checking for working aclocal" >&5 +echo "configure:953: checking for working aclocal" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1162,7 +962,7 @@ else fi echo $ac_n "checking for working autoconf""... $ac_c" 1>&6 -echo "configure:1166: checking for working autoconf" >&5 +echo "configure:966: checking for working autoconf" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1175,7 +975,7 @@ else fi echo $ac_n "checking for working automake""... $ac_c" 1>&6 -echo "configure:1179: checking for working automake" >&5 +echo "configure:979: checking for working automake" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1188,7 +988,7 @@ else fi echo $ac_n "checking for working autoheader""... $ac_c" 1>&6 -echo "configure:1192: checking for working autoheader" >&5 +echo "configure:992: checking for working autoheader" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1201,7 +1001,7 @@ else fi echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6 -echo "configure:1205: checking for working makeinfo" >&5 +echo "configure:1005: checking for working makeinfo" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1224,7 +1024,7 @@ fi # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1228: checking for $ac_word" >&5 +echo "configure:1028: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1256,7 +1056,7 @@ fi # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1260: checking for $ac_word" >&5 +echo "configure:1060: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1288,7 +1088,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1292: checking for $ac_word" >&5 +echo "configure:1092: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1391,6 +1191,228 @@ else enable_fast_install=yes fi +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1198: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1228: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1279: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1311: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 1322 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:1327: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1353: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1358: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <<EOF +#ifdef __GNUC__ + yes; +#endif +EOF +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1367: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1386: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + # Check whether --with-gnu-ld or --without-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then withval="$with_gnu_ld" @@ -1403,7 +1425,7 @@ ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6 -echo "configure:1407: checking for ld used by GCC" >&5 +echo "configure:1429: checking for ld used by GCC" >&5 case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw @@ -1433,10 +1455,10 @@ echo "configure:1407: checking for ld used by GCC" >&5 esac elif test "$with_gnu_ld" = yes; then echo $ac_n "checking for GNU ld""... $ac_c" 1>&6 -echo "configure:1437: checking for GNU ld" >&5 +echo "configure:1459: checking for GNU ld" >&5 else echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6 -echo "configure:1440: checking for non-GNU ld" >&5 +echo "configure:1462: checking for non-GNU ld" >&5 fi if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1471,7 +1493,7 @@ else fi test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; } echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6 -echo "configure:1475: checking if the linker ($LD) is GNU ld" >&5 +echo "configure:1497: checking if the linker ($LD) is GNU ld" >&5 if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1488,7 +1510,7 @@ with_gnu_ld=$lt_cv_prog_gnu_ld echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6 -echo "configure:1492: checking for $LD option to reload object files" >&5 +echo "configure:1514: checking for $LD option to reload object files" >&5 if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1500,7 +1522,7 @@ reload_flag=$lt_cv_ld_reload_flag test -n "$reload_flag" && reload_flag=" $reload_flag" echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6 -echo "configure:1504: checking for BSD-compatible nm" >&5 +echo "configure:1526: checking for BSD-compatible nm" >&5 if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1538,7 +1560,7 @@ NM="$lt_cv_path_NM" echo "$ac_t""$NM" 1>&6 echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6 -echo "configure:1542: checking whether ln -s works" >&5 +echo "configure:1564: checking whether ln -s works" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1559,7 +1581,7 @@ else fi echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6 -echo "configure:1563: checking how to recognise dependant libraries" >&5 +echo "configure:1585: checking how to recognise dependant libraries" >&5 if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1732,13 +1754,13 @@ file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method echo $ac_n "checking for object suffix""... $ac_c" 1>&6 -echo "configure:1736: checking for object suffix" >&5 +echo "configure:1758: checking for object suffix" >&5 if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else rm -f conftest* echo 'int i = 1;' > conftest.$ac_ext -if { (eval echo configure:1742: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1764: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then for ac_file in conftest.*; do case $ac_file in *.c) ;; @@ -1758,7 +1780,7 @@ ac_objext=$ac_cv_objext echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:1762: checking for executable suffix" >&5 +echo "configure:1784: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1768,7 +1790,7 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:1772: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:1794: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in *.c | *.o | *.obj | *.ilk | *.pdb) ;; @@ -1795,7 +1817,7 @@ case $deplibs_check_method in file_magic*) if test "$file_magic_cmd" = '$MAGIC_CMD'; then echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6 -echo "configure:1799: checking for ${ac_tool_prefix}file" >&5 +echo "configure:1821: checking for ${ac_tool_prefix}file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1857,7 +1879,7 @@ fi if test -z "$lt_cv_path_MAGIC_CMD"; then if test -n "$ac_tool_prefix"; then echo $ac_n "checking for file""... $ac_c" 1>&6 -echo "configure:1861: checking for file" >&5 +echo "configure:1883: checking for file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1928,7 +1950,7 @@ esac # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1932: checking for $ac_word" >&5 +echo "configure:1954: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1960,7 +1982,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1964: checking for $ac_word" >&5 +echo "configure:1986: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1995,7 +2017,7 @@ fi # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1999: checking for $ac_word" >&5 +echo "configure:2021: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2027,7 +2049,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2031: checking for $ac_word" >&5 +echo "configure:2053: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2094,8 +2116,8 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic" case $host in *-*-irix6*) # Find out which ABI we are using. - echo '#line 2098 "configure"' > conftest.$ac_ext - if { (eval echo configure:2099: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + echo '#line 2120 "configure"' > conftest.$ac_ext + if { (eval echo configure:2121: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then if test "$lt_cv_prog_gnu_ld" = yes; then case `/usr/bin/file conftest.$ac_objext` in *32-bit*) @@ -2128,7 +2150,7 @@ case $host in ia64-*-hpux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext - if { (eval echo configure:2132: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + if { (eval echo configure:2154: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then case "`/usr/bin/file conftest.o`" in *ELF-32*) HPUX_IA64_MODE="32" @@ -2146,7 +2168,7 @@ ia64-*-hpux*) SAVE_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -belf" echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6 -echo "configure:2150: checking whether the C compiler needs -belf" >&5 +echo "configure:2172: checking whether the C compiler needs -belf" >&5 if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2159,14 +2181,14 @@ ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$a cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext <<EOF -#line 2163 "configure" +#line 2185 "configure" #include "confdefs.h" int main() { ; return 0; } EOF -if { (eval echo configure:2170: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2192: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* lt_cv_cc_needs_belf=yes else @@ -2334,7 +2356,7 @@ if test -z "$target" ; then fi echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:2338: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:2360: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" @@ -2357,7 +2379,7 @@ fi echo $ac_n "checking whether to install libbfd""... $ac_c" 1>&6 -echo "configure:2361: checking whether to install libbfd" >&5 +echo "configure:2383: checking whether to install libbfd" >&5 # Check whether --enable-install-libbfd or --disable-install-libbfd was given. if test "${enable_install_libbfd+set}" = set; then enableval="$enable_install_libbfd" @@ -2394,7 +2416,7 @@ fi echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:2398: checking for executable suffix" >&5 +echo "configure:2420: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2404,7 +2426,7 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:2408: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:2430: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in *.c | *.o | *.obj | *.ilk | *.pdb) ;; @@ -2430,7 +2452,7 @@ ac_exeext=$EXEEXT # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2434: checking for $ac_word" >&5 +echo "configure:2456: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2460,7 +2482,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2464: checking for $ac_word" >&5 +echo "configure:2486: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2511,7 +2533,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2515: checking for $ac_word" >&5 +echo "configure:2537: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2543,7 +2565,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:2547: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:2569: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -2554,12 +2576,12 @@ cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext << EOF -#line 2558 "configure" +#line 2580 "configure" #include "confdefs.h" main(){return(0);} EOF -if { (eval echo configure:2563: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -2585,12 +2607,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:2589: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:2611: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:2594: checking whether we are using GNU C" >&5 +echo "configure:2616: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2599,7 +2621,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2603: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2625: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -2618,7 +2640,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:2622: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:2644: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2652,7 +2674,7 @@ fi ALL_LINGUAS="fr sv tr es da de id pt_BR ro" echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:2656: checking how to run the C preprocessor" >&5 +echo "configure:2678: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -2667,13 +2689,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 2671 "configure" +#line 2693 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2677: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2699: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2684,13 +2706,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 2688 "configure" +#line 2710 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2694: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2701,13 +2723,13 @@ else rm -rf conftest* CPP="${CC-cc} -nologo -E" cat > conftest.$ac_ext <<EOF -#line 2705 "configure" +#line 2727 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2711: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2734,7 +2756,7 @@ echo "$ac_t""$CPP" 1>&6 # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2738: checking for $ac_word" >&5 +echo "configure:2760: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2762,12 +2784,12 @@ else fi echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 -echo "configure:2766: checking for ANSI C header files" >&5 +echo "configure:2788: checking for ANSI C header files" >&5 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2771 "configure" +#line 2793 "configure" #include "confdefs.h" #include <stdlib.h> #include <stdarg.h> @@ -2775,7 +2797,7 @@ else #include <float.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2779: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2801: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2792,7 +2814,7 @@ rm -f conftest* if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2796 "configure" +#line 2818 "configure" #include "confdefs.h" #include <string.h> EOF @@ -2810,7 +2832,7 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2814 "configure" +#line 2836 "configure" #include "confdefs.h" #include <stdlib.h> EOF @@ -2831,7 +2853,7 @@ if test "$cross_compiling" = yes; then : else cat > conftest.$ac_ext <<EOF -#line 2835 "configure" +#line 2857 "configure" #include "confdefs.h" #include <ctype.h> #define ISLOWER(c) ('a' <= (c) && (c) <= 'z') @@ -2842,7 +2864,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); exit (0); } EOF -if { (eval echo configure:2846: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:2868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then : else @@ -2866,12 +2888,12 @@ EOF fi echo $ac_n "checking for working const""... $ac_c" 1>&6 -echo "configure:2870: checking for working const" >&5 +echo "configure:2892: checking for working const" >&5 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2875 "configure" +#line 2897 "configure" #include "confdefs.h" int main() { @@ -2920,7 +2942,7 @@ ccp = (char const *const *) p; ; return 0; } EOF -if { (eval echo configure:2924: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2946: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_const=yes else @@ -2941,21 +2963,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:2945: checking for inline" >&5 +echo "configure:2967: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <<EOF -#line 2952 "configure" +#line 2974 "configure" #include "confdefs.h" int main() { } $ac_kw foo() { ; return 0; } EOF -if { (eval echo configure:2959: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -2981,12 +3003,12 @@ EOF esac echo $ac_n "checking for off_t""... $ac_c" 1>&6 -echo "configure:2985: checking for off_t" >&5 +echo "configure:3007: checking for off_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2990 "configure" +#line 3012 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -3014,12 +3036,12 @@ EOF fi echo $ac_n "checking for size_t""... $ac_c" 1>&6 -echo "configure:3018: checking for size_t" >&5 +echo "configure:3040: checking for size_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3023 "configure" +#line 3045 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -3049,19 +3071,19 @@ fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:3053: checking for working alloca.h" >&5 +echo "configure:3075: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3058 "configure" +#line 3080 "configure" #include "confdefs.h" #include <alloca.h> int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:3065: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3087: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -3082,12 +3104,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:3086: checking for alloca" >&5 +echo "configure:3108: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3091 "configure" +#line 3113 "configure" #include "confdefs.h" #ifdef __GNUC__ @@ -3115,7 +3137,7 @@ int main() { char *p = (char *) alloca(1); ; return 0; } EOF -if { (eval echo configure:3119: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3141: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -3147,12 +3169,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:3151: checking whether alloca needs Cray hooks" >&5 +echo "configure:3173: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3156 "configure" +#line 3178 "configure" #include "confdefs.h" #if defined(CRAY) && ! defined(CRAY2) webecray @@ -3177,12 +3199,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3181: checking for $ac_func" >&5 +echo "configure:3203: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3186 "configure" +#line 3208 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3205,7 +3227,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3209: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3231: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3232,7 +3254,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:3236: checking stack direction for C alloca" >&5 +echo "configure:3258: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3240,7 +3262,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <<EOF -#line 3244 "configure" +#line 3266 "configure" #include "confdefs.h" find_stack_direction () { @@ -3259,7 +3281,7 @@ main () exit (find_stack_direction() < 0); } EOF -if { (eval echo configure:3263: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3285: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -3284,17 +3306,17 @@ for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3288: checking for $ac_hdr" >&5 +echo "configure:3310: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3293 "configure" +#line 3315 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3298: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3320: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3323,12 +3345,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3327: checking for $ac_func" >&5 +echo "configure:3349: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3332 "configure" +#line 3354 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3351,7 +3373,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3355: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3377: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3376,7 +3398,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:3380: checking for working mmap" >&5 +echo "configure:3402: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3384,7 +3406,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 3388 "configure" +#line 3410 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -3524,7 +3546,7 @@ main() } EOF -if { (eval echo configure:3528: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3550: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -3552,17 +3574,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3556: checking for $ac_hdr" >&5 +echo "configure:3578: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3561 "configure" +#line 3583 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3566: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3588: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3592,12 +3614,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3596: checking for $ac_func" >&5 +echo "configure:3618: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3601 "configure" +#line 3623 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3620,7 +3642,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3624: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3646: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3649,12 +3671,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3653: checking for $ac_func" >&5 +echo "configure:3675: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3658 "configure" +#line 3680 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3677,7 +3699,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3681: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3703: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3711,19 +3733,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:3715: checking for LC_MESSAGES" >&5 +echo "configure:3737: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3720 "configure" +#line 3742 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:3727: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -3744,7 +3766,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:3748: checking whether NLS is requested" >&5 +echo "configure:3770: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -3764,7 +3786,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:3768: checking whether included gettext is requested" >&5 +echo "configure:3790: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -3783,17 +3805,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:3787: checking for libintl.h" >&5 +echo "configure:3809: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3792 "configure" +#line 3814 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3797: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3819: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3810,19 +3832,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:3814: checking for gettext in libc" >&5 +echo "configure:3836: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3819 "configure" +#line 3841 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3826: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3848: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -3838,7 +3860,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:3842: checking for bindtextdomain in -lintl" >&5 +echo "configure:3864: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3846,7 +3868,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3850 "configure" +#line 3872 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3857,7 +3879,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:3861: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3883: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3873,19 +3895,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:3877: checking for gettext in libintl" >&5 +echo "configure:3899: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3882 "configure" +#line 3904 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3889: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3911: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -3913,7 +3935,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3917: checking for $ac_word" >&5 +echo "configure:3939: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3947,12 +3969,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3951: checking for $ac_func" >&5 +echo "configure:3973: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3956 "configure" +#line 3978 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3975,7 +3997,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3979: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4001: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4002,7 +4024,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4006: checking for $ac_word" >&5 +echo "configure:4028: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4038,7 +4060,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4042: checking for $ac_word" >&5 +echo "configure:4064: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4070,7 +4092,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 4074 "configure" +#line 4096 "configure" #include "confdefs.h" int main() { @@ -4078,7 +4100,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:4082: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4104: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -4110,7 +4132,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4114: checking for $ac_word" >&5 +echo "configure:4136: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4144,7 +4166,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4148: checking for $ac_word" >&5 +echo "configure:4170: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4180,7 +4202,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4184: checking for $ac_word" >&5 +echo "configure:4206: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4270,7 +4292,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:4274: checking for catalogs to be installed" >&5 +echo "configure:4296: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -4298,17 +4320,17 @@ echo "configure:4274: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:4302: checking for linux/version.h" >&5 +echo "configure:4324: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4307 "configure" +#line 4329 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4312: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4334: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4386,7 +4408,7 @@ if test "x$cross_compiling" = "xno"; then EXEEXT_FOR_BUILD='$(EXEEXT)' else echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 -echo "configure:4390: checking for build system executable suffix" >&5 +echo "configure:4412: checking for build system executable suffix" >&5 if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4423,7 +4445,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:4427: checking for a BSD compatible install" >&5 +echo "configure:4449: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4480,17 +4502,17 @@ for ac_hdr in string.h strings.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4484: checking for $ac_hdr" >&5 +echo "configure:4506: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4489 "configure" +#line 4511 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4494: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4516: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4869,7 +4891,6 @@ s%@build_alias@%$build_alias%g s%@build_cpu@%$build_cpu%g s%@build_vendor@%$build_vendor%g s%@build_os@%$build_os%g -s%@CC@%$CC%g s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g s%@INSTALL_DATA@%$INSTALL_DATA%g @@ -4883,6 +4904,7 @@ s%@MAKEINFO@%$MAKEINFO%g s%@SET_MAKE@%$SET_MAKE%g s%@AR@%$AR%g s%@RANLIB@%$RANLIB%g +s%@CC@%$CC%g s%@LN_S@%$LN_S%g s%@OBJEXT@%$OBJEXT%g s%@EXEEXT@%$EXEEXT%g diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c index be9c36c..8e7c7b8 100644 --- a/opcodes/fr30-asm.c +++ b/opcodes/fr30-asm.c @@ -657,10 +657,10 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! fr30_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 01d896f..3309d54 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h index 6be96d9..35d0de7 100644 --- a/opcodes/fr30-desc.h +++ b/opcodes/fr30-desc.h @@ -240,7 +240,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c index 538ed2d..0e3d8dd 100644 --- a/opcodes/frv-asm.c +++ b/opcodes/frv-asm.c @@ -64,6 +64,8 @@ static const char * parse_s12 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); static const char * parse_u12 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_even_register + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); static const char * parse_ulo16 (cd, strp, opindex, valuep) @@ -346,6 +348,26 @@ parse_u12 (cd, strp, opindex, valuep) } } +static const char * +parse_even_register (cd, strP, tableP, valueP) + CGEN_CPU_DESC cd; + const char ** strP; + CGEN_KEYWORD * tableP; + long * valueP; +{ + const char * errmsg; + const char * saved_star_strP = * strP; + + errmsg = cgen_parse_keyword (cd, strP, tableP, valueP); + + if (errmsg == NULL && ((* valueP) & 1)) + { + errmsg = _("register number must be even"); + * strP = saved_star_strP; + } + + return errmsg; +} /* -- */ const char * frv_cgen_parse_operand @@ -455,12 +477,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields) case FRV_OPERAND_FRINTI : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; case FRV_OPERAND_FRINTJ : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; case FRV_OPERAND_FRINTK : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; case FRV_OPERAND_FRJ : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); break; @@ -929,10 +960,10 @@ frv_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! frv_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 5fac77a..97d49b3 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -188,7 +188,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "PRIVILEGED", &bool_attr[0], &bool_attr[0] }, @@ -2173,6 +2173,18 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* FRintieven: (even) source register 1 */ + { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintjeven: (even) source register 2 */ + { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintkeven: (even) target register */ + { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, + { 0, { (1<<MACH_BASE) } } }, /* d12: 12 bit signed immediate */ { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, @@ -5472,7 +5484,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ +/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5497,7 +5509,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MSRAHI, "msrahi", "msrahi", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdrotli$pack $FRinti,$u6,$FRintk */ +/* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5517,7 +5529,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MSATHS, "msaths", "msaths", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, -/* mqsaths$pack $FRinti,$FRintj,$FRintk */ +/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } @@ -5582,42 +5594,42 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, -/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } @@ -5682,32 +5694,32 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } @@ -5742,37 +5754,37 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ +/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ +/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, -/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, -/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5817,22 +5829,22 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } @@ -5847,12 +5859,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mexpdhd$pack $FRinti,$u6,$FRintk */ +/* mexpdhd$pack $FRinti,$u6,$FRintkeven */ { FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ +/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } @@ -5862,37 +5874,37 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MPACKH, "mpackh", "mpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdpackh$pack $FRinti,$FRintj,$FRintk */ +/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } } }, -/* munpackh$pack $FRinti,$FRintk */ +/* munpackh$pack $FRinti,$FRintkeven */ { FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* mdunpackh$pack $FRinti,$FRintk */ +/* mdunpackh$pack $FRintieven,$FRintk */ { FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32, { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } }, -/* mbtoh$pack $FRintj,$FRintk */ +/* mbtoh$pack $FRintj,$FRintkeven */ { FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* mhtob$pack $FRintj,$FRintk */ +/* mhtob$pack $FRintjeven,$FRintk */ { FRV_INSN_MHTOB, "mhtob", "mhtob", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ { FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index 53cad79..a169e7a 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -677,15 +677,16 @@ typedef enum cgen_operand_type { , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE - , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12 - , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 - , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS - , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA - , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX + , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN + , FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12 + , FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16 + , FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET + , FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT + , FRV_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 77 +#define MAX_OPERANDS 80 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 @@ -695,7 +696,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index f71e1c5..dfe053d 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -230,12 +230,21 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) case FRV_OPERAND_FRINTI : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); break; + case FRV_OPERAND_FRINTIEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; case FRV_OPERAND_FRINTJ : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); break; + case FRV_OPERAND_FRINTJEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; case FRV_OPERAND_FRINTK : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); break; + case FRV_OPERAND_FRINTKEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; case FRV_OPERAND_FRJ : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); break; diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index 316b2cc..bac1837 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -651,12 +651,21 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) case FRV_OPERAND_FRINTI : errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRINTJ : errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRINTK : errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRJ : errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); break; @@ -942,12 +951,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case FRV_OPERAND_FRINTI : length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); break; + case FRV_OPERAND_FRINTIEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; case FRV_OPERAND_FRINTJ : length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); break; + case FRV_OPERAND_FRINTJEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; case FRV_OPERAND_FRINTK : length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); break; + case FRV_OPERAND_FRINTKEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; case FRV_OPERAND_FRJ : length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); break; @@ -1216,12 +1234,21 @@ frv_cgen_get_int_operand (cd, opindex, fields) case FRV_OPERAND_FRINTI : value = fields->f_FRi; break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; case FRV_OPERAND_FRINTJ : value = fields->f_FRj; break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; case FRV_OPERAND_FRINTK : value = fields->f_FRk; break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; case FRV_OPERAND_FRJ : value = fields->f_FRj; break; @@ -1441,12 +1468,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields) case FRV_OPERAND_FRINTI : value = fields->f_FRi; break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; case FRV_OPERAND_FRINTJ : value = fields->f_FRj; break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; case FRV_OPERAND_FRINTK : value = fields->f_FRk; break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; case FRV_OPERAND_FRJ : value = fields->f_FRj; break; @@ -1675,12 +1711,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value) case FRV_OPERAND_FRINTI : fields->f_FRi = value; break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; case FRV_OPERAND_FRINTJ : fields->f_FRj = value; break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; case FRV_OPERAND_FRINTK : fields->f_FRk = value; break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; case FRV_OPERAND_FRJ : fields->f_FRj = value; break; @@ -1897,12 +1942,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value) case FRV_OPERAND_FRINTI : fields->f_FRi = value; break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; case FRV_OPERAND_FRINTJ : fields->f_FRj = value; break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; case FRV_OPERAND_FRINTK : fields->f_FRk = value; break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; case FRV_OPERAND_FRJ : fields->f_FRj = value; break; diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 5e56e35..de27a43 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -1033,6 +1033,18 @@ static const CGEN_IFMT ifmt_mcuti = { 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } }; +static const CGEN_IFMT ifmt_mdcutssi = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mdrotli = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mqsaths = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mcmpsh = { 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; @@ -1041,6 +1053,10 @@ static const CGEN_IFMT ifmt_mabshs = { 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_cmqaddhss = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_maddaccs = { 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } }; @@ -1053,6 +1069,14 @@ static const CGEN_IFMT ifmt_cmmulhs = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqmulhs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmulhs = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mmachu = { 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; @@ -1061,18 +1085,54 @@ static const CGEN_IFMT ifmt_cmmachu = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqmachu = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmachu = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cmexpdhw = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } }; +static const CGEN_IFMT ifmt_mexpdhd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhd = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + static const CGEN_IFMT ifmt_munpackh = { 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } }; +static const CGEN_IFMT ifmt_mdunpackh = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mbtoh = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cmbtoh = { 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mhtob = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmhtob = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtohe = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mclracc = { 32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } }; @@ -4978,11 +5038,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, & ifmt_mcuti, { 0x1ec0bc0 } }, -/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ +/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, - & ifmt_mcuti, { 0x1e00380 } + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mdcutssi, { 0x1e00380 } }, /* maveh$pack $FRinti,$FRintj,$FRintk */ { @@ -5008,11 +5068,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, & ifmt_mrotli, { 0x1ec02c0 } }, -/* mdrotli$pack $FRinti,$u6,$FRintk */ +/* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, - & ifmt_mrotli, { 0x1e002c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mdrotli, { 0x1e002c0 } }, /* mcplhi$pack $FRinti,$u6,$FRintk */ { @@ -5032,11 +5092,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, & ifmt_mand, { 0x1ec0300 } }, -/* mqsaths$pack $FRinti,$FRintj,$FRintk */ +/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1e003c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e003c0 } }, /* msathu$pack $FRinti,$FRintj,$FRintk */ { @@ -5110,53 +5170,53 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmand, { 0x1c400c0 } }, -/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0600 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0600 } }, -/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0640 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0640 } }, -/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0680 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0680 } }, -/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec06c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec06c0 } }, -/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0000 } }, -/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0040 } }, -/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0080 } }, -/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc00c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc00c0 } }, /* maddaccs$pack $ACC40Si,$ACC40Sk */ { @@ -5230,41 +5290,41 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmulhs, { 0x1c80040 } }, -/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0700 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0700 } }, -/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0740 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0740 } }, -/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0a80 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0a80 } }, -/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0ac0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0ac0 } }, -/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00000 } }, -/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00040 } }, /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ { @@ -5302,47 +5362,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmachu, { 0x1c800c0 } }, -/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0780 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0780 } }, -/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ +/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, - & ifmt_mmachu, { 0x1ec07c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), 0 } }, + & ifmt_mqmachu, { 0x1ec07c0 } }, -/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00080 } }, -/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ +/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmachu, { 0x1d000c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmachu, { 0x1d000c0 } }, -/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00000 } }, -/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00040 } }, -/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00080 } }, /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ { @@ -5392,29 +5452,29 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmulhs, { 0x1d400c0 } }, -/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0900 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0900 } }, -/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0940 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0940 } }, -/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0980 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0980 } }, -/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec09c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec09c0 } }, /* mexpdhw$pack $FRinti,$u6,$FRintk */ { @@ -5428,17 +5488,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmexpdhw, { 0x1d80080 } }, -/* mexpdhd$pack $FRinti,$u6,$FRintk */ +/* mexpdhd$pack $FRinti,$u6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, - & ifmt_mrotli, { 0x1ec0cc0 } + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mexpdhd, { 0x1ec0cc0 } }, -/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ +/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmexpdhw, { 0x1d800c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhd, { 0x1d800c0 } }, /* mpackh$pack $FRinti,$FRintj,$FRintk */ { @@ -5446,47 +5506,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, & ifmt_mand, { 0x1ec0d00 } }, -/* mdpackh$pack $FRinti,$FRintj,$FRintk */ +/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0d80 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0d80 } }, -/* munpackh$pack $FRinti,$FRintk */ +/* munpackh$pack $FRinti,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTKEVEN), 0 } }, & ifmt_munpackh, { 0x1ec0d40 } }, -/* mdunpackh$pack $FRinti,$FRintk */ +/* mdunpackh$pack $FRintieven,$FRintk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, - & ifmt_munpackh, { 0x1ec0dc0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mdunpackh, { 0x1ec0dc0 } }, -/* mbtoh$pack $FRintj,$FRintk */ +/* mbtoh$pack $FRintj,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mabshs, { 0x1ec0e00 } + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mbtoh, { 0x1ec0e00 } }, -/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmbtoh, { 0x1dc0000 } }, -/* mhtob$pack $FRintj,$FRintk */ +/* mhtob$pack $FRintjeven,$FRintk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mabshs, { 0x1ec0e40 } + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mhtob, { 0x1ec0e40 } }, -/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmbtoh, { 0x1dc0040 } + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmhtob, { 0x1dc0040 } }, /* mbtohe$pack $FRintj,$FRintk */ { @@ -5498,7 +5558,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmbtoh, { 0x1dc0080 } + & ifmt_cmbtohe, { 0x1dc0080 } }, /* mclracc$pack $ACC40Sk,$A */ { diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 018a643..5d23cf9 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -27,11 +27,14 @@ with this program; if not, write to the Free Software Foundation, Inc., /* -- opc.h */ -#undef CGEN_DIS_HASH_SIZE +#undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 128 -#undef CGEN_DIS_HASH +#undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + /* Vliw support. */ #define FRV_VLIW_SIZE 4 /* fr500 has largest vliw size of 4. */ typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c index 2a3cd21..ea8d30b 100644 --- a/opcodes/h8300-dis.c +++ b/opcodes/h8300-dis.c @@ -1,5 +1,5 @@ /* Disassemble h8300 instructions. - Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002 + Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -34,11 +34,39 @@ struct h8_instruction struct h8_instruction *h8_instructions; static void bfd_h8_disassemble_init PARAMS ((void)); -static unsigned int bfd_h8_disassemble - PARAMS ((bfd_vma, disassemble_info *, int)); +static void print_one_arg PARAMS ((disassemble_info *, bfd_vma, op_type, + int, int, int, int, const char **, int)); +static unsigned int bfd_h8_disassemble PARAMS ((bfd_vma, + disassemble_info *, + int)); +static void extract_immediate PARAMS ((FILE *, + op_type, int, + unsigned char *, + int *, int *, + const struct h8_opcode *)); + +static void print_colon_thingie PARAMS ((op_type *)); + +static void +print_colon_thingie (op_type *nib) +{ + switch (*nib & SIZE) { + case L_2: fprintf (stdout, "2"); break; + case L_3: + case L_3NZ: fprintf (stdout, "3"); break; + case L_4: fprintf (stdout, "4"); break; + case L_5: fprintf (stdout, "5"); break; + case L_8: fprintf (stdout, "8"); break; + case L_16: + case L_16U: fprintf (stdout, "16"); break; + case L_24: fprintf (stdout, "24"); break; + case L_32: fprintf (stdout, "32"); break; + } +} /* Run through the opcodes and sort them into order to make them easy to disassemble. */ + static void bfd_h8_disassemble_init () { @@ -69,11 +97,14 @@ bfd_h8_disassemble_init () /* Just make sure there are an even number of nibbles in it, and that the count is the same as the length. */ - for (i = 0; p->data.nib[i] != E; i++) + for (i = 0; p->data.nib[i] != (op_type) E; i++) ; if (i & 1) - abort (); + { + fprintf (stderr, "Internal error, h8_disassemble_init.\n"); + abort (); + } pi->length = i / 2; pi->opcode = p; @@ -84,42 +115,287 @@ bfd_h8_disassemble_init () pi->opcode = p; } -static unsigned int -bfd_h8_disassemble (addr, info, mode) - bfd_vma addr; +static void +extract_immediate (stream, looking_for, thisnib, data, cst, len, q) + FILE *stream; + op_type looking_for; + int thisnib; + unsigned char *data; + int *cst, *len; + const struct h8_opcode *q; +{ + switch (looking_for & SIZE) + { + case L_2: + *len = 2; + *cst = thisnib & 3; + + /* DISP2 special treatment. */ + if ((looking_for & MODE) == DISP) + { + if (OP_KIND (q->how) == O_MOVAB || + OP_KIND (q->how) == O_MOVAW || + OP_KIND (q->how) == O_MOVAL) + { + /* Handling for mova insn. */ + switch (q->args.nib[0] & MODE) { + case INDEXB: + default: + break; + case INDEXW: + *cst *= 2; + break; + case INDEXL: + *cst *= 4; + break; + } + } + else + { + /* Handling for non-mova insn. */ + switch (OP_SIZE (q->how)) { + default: break; + case SW: + *cst *= 2; + break; + case SL: + *cst *= 4; + break; + } + } + } + break; + case L_8: + *len = 8; + *cst = data[0]; + break; + case L_16: + case L_16U: + *len = 16; + *cst = (data[0] << 8) + data [1]; +#if 0 + if ((looking_for & SIZE) == L_16) + *cst = (short) *cst; /* sign extend */ +#endif + break; + case L_32: + *len = 32; + *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3]; + break; + default: + *len = 0; + *cst = 0; + fprintf (stream, "DISP bad size\n"); + break; + } +} + +static const char *regnames[] = +{ + "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", + "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l" +}; +static const char *wregnames[] = +{ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" +}; +static const char *lregnames[] = +{ + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" +}; +static const char *cregnames[] = +{ + "ccr", "exr", "mach", "macl", "", "", "vbr", "sbr" +}; + +static void +print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len) disassemble_info *info; - int mode; + bfd_vma addr; + op_type x; + int cst, cstlen, rdisp_n, rn; + const char **pregnames; + int len; { - /* Find the first entry in the table for this opcode. */ - static const char *regnames[] = + void *stream = info->stream; + fprintf_ftype outfn = info->fprintf_func; + + if ((x & SIZE) == L_3 || + (x & SIZE) == L_3NZ) + { + outfn (stream, "#0x%x", (unsigned) cst); + } + else if ((x & MODE) == IMM) + { + outfn (stream, "#0x%x", (unsigned) cst); + } + else if ((x & MODE) == DBIT || + (x & MODE) == KBIT) + { + outfn (stream, "#%d", (unsigned) cst); + } + else if ((x & MODE) == CONST_2) + outfn (stream, "#2"); + else if ((x & MODE) == CONST_4) + outfn (stream, "#4"); + else if ((x & MODE) == CONST_8) + outfn (stream, "#8"); + else if ((x & MODE) == CONST_16) + outfn (stream, "#16"); + else if ((x & MODE) == REG) + { + switch (x & SIZE) + { + case L_8: + outfn (stream, "%s", regnames[rn]); + break; + case L_16: + case L_16U: + outfn (stream, "%s", wregnames[rn]); + break; + case L_P: + case L_32: + outfn (stream, "%s", lregnames[rn]); + break; + } + } + else if ((x & MODE) == LOWREG) + { + switch (x & SIZE) + { + case L_8: + /* Always take low half of reg. */ + outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]); + break; + case L_16: + case L_16U: + /* Always take low half of reg. */ + outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn - 8]); + break; + case L_P: + case L_32: + outfn (stream, "%s.l", lregnames[rn]); + break; + } + } + else if ((x & MODE) == POSTINC) + { + outfn (stream, "@%s+", pregnames[rn]); + } + else if ((x & MODE) == POSTDEC) + { + outfn (stream, "@%s-", pregnames[rn]); + } + else if ((x & MODE) == PREINC) + { + outfn (stream, "@+%s", pregnames[rn]); + } + else if ((x & MODE) == PREDEC) + { + outfn (stream, "@-%s", pregnames[rn]); + } + else if ((x & MODE) == IND) + { + outfn (stream, "@%s", pregnames[rn]); + } + else if ((x & MODE) == ABS || (x & ABSJMP)) + { + outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen); + } + else if ((x & MODE) == MEMIND) + { + outfn (stream, "@@%d (0x%x)", cst, cst); + } + else if ((x & MODE) == VECIND) + { + /* FIXME Multiplier should be 2 or 4, depending on processor mode, + by which is meant "normal" vs. "middle", "advanced", "maximum". */ + + int offset = (cst + 0x80) * 4; + outfn (stream, "@@%d (0x%x)", offset, offset); + } + else if ((x & MODE) == PCREL) + { + if ((x & SIZE) == L_16 || + (x & SIZE) == L_16U) + { + outfn (stream, ".%s%d (0x%x)", + (short) cst > 0 ? "+" : "", + (short) cst, + addr + (short) cst + len); + } + else + { + outfn (stream, ".%s%d (0x%x)", + (char) cst > 0 ? "+" : "", + (char) cst, + addr + (char) cst + len); + } + } + else if ((x & MODE) == DISP) + { + outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, + pregnames[rdisp_n]); + } + else if ((x & MODE) == INDEXB) + { + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, + regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]); + } + else if ((x & MODE) == INDEXW) { - "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", - "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l" - }; - static const char *wregnames[] = + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, + wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]); + } + else if ((x & MODE) == INDEXL) { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" - }; - static const char *lregnames[] = + outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, + lregnames[rdisp_n]); + } + else if (x & CTRL) { - "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", - "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" - }; - int rs = 0; - int rd = 0; - int rdisp = 0; - int abs = 0; - int bit = 0; - int plen = 0; + outfn (stream, cregnames[rn]); + } + else if ((x & MODE) == CCR) + { + outfn (stream, "ccr"); + } + else if ((x & MODE) == EXR) + { + outfn (stream, "exr"); + } + else if ((x & MODE) == MACREG) + { + outfn (stream, "mac%c", cst ? 'l' : 'h'); + } + else + /* xgettext:c-format */ + outfn (stream, _("Hmmmm 0x%x"), x); +} + +static unsigned int +bfd_h8_disassemble (addr, info, mach) + bfd_vma addr; + disassemble_info *info; + int mach; +{ + /* Find the first entry in the table for this opcode. */ + int regno[3] = { 0, 0, 0 }; + int dispregno[3] = { 0, 0, 0 }; + int cst[3] = { 0, 0, 0 }; + int cstlen[3] = { 0, 0, 0 }; static bfd_boolean init = 0; const struct h8_instruction *qi; - char const **pregnames = mode != 0 ? lregnames : wregnames; + char const **pregnames = mach != 0 ? lregnames : wregnames; int status; - int l; - unsigned char data[20]; + unsigned int l; + unsigned char data[MAX_CODE_NIBBLES]; void *stream = info->stream; - fprintf_ftype fprintf = info->fprintf_func; + fprintf_ftype outfn = info->fprintf_func; if (!init) { @@ -134,7 +410,7 @@ bfd_h8_disassemble (addr, info, mode) return -1; } - for (l = 2; status == 0 && l < 10; l += 2) + for (l = 2; status == 0 && l < sizeof (data) / 2; l += 2) status = info->read_memory_func (addr + l, data + l, 2, info); /* Find the exact opcode/arg combo. */ @@ -147,9 +423,12 @@ bfd_h8_disassemble (addr, info, mode) while (1) { op_type looking_for = *nib; - int thisnib = data[len >> 1]; + int thisnib = data[len / 2]; + int opnr; - thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); + thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib / 16) & 0xf); + opnr = ((looking_for & OP3) == OP3 ? 2 + : (looking_for & DST) == DST ? 1 : 0); if (looking_for < 16 && looking_for >= 0) { @@ -160,21 +439,78 @@ bfd_h8_disassemble (addr, info, mode) { if ((int) looking_for & (int) B31) { - if (!(((int) thisnib & 0x8) != 0)) + if (!((thisnib & 0x8) != 0)) goto fail; looking_for = (op_type) ((int) looking_for & ~(int) B31); + thisnib &= 0x7; } - - if ((int) looking_for & (int) B30) + else if ((int) looking_for & (int) B30) { - if (!(((int) thisnib & 0x8) == 0)) + if (!((thisnib & 0x8) == 0)) goto fail; looking_for = (op_type) ((int) looking_for & ~(int) B30); } - if (looking_for & DBIT) + if ((int) looking_for & (int) B21) + { + if (!((thisnib & 0x4) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B21); + thisnib &= 0xb; + } + else if ((int) looking_for & (int) B20) + { + if (!((thisnib & 0x4) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B20); + } + if ((int) looking_for & (int) B11) + { + if (!((thisnib & 0x2) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B11); + thisnib &= 0xd; + } + else if ((int) looking_for & (int) B10) + { + if (!((thisnib & 0x2) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B10); + } + + if ((int) looking_for & (int) B01) + { + if (!((thisnib & 0x1) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B01); + thisnib &= 0xe; + } + else if ((int) looking_for & (int) B00) + { + if (!((thisnib & 0x1) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B00); + } + + if (looking_for & IGNORE) + { + /* Hitachi has declared that IGNORE must be zero. */ + if (thisnib != 0) + goto fail; + } + else if ((looking_for & MODE) == DATA) + { + ; /* Skip embedded data. */ + } + else if ((looking_for & MODE) == DBIT) { /* Exclude adds/subs by looking at bit 0 and 2, and make sure the operand size, either w or l, @@ -182,45 +518,98 @@ bfd_h8_disassemble (addr, info, mode) if ((looking_for & 7) != (thisnib & 7)) goto fail; - abs = (thisnib & 0x8) ? 2 : 1; + cst[opnr] = (thisnib & 0x8) ? 2 : 1; } - else if (looking_for & (REG | IND | INC | DEC)) + else if ((looking_for & MODE) == DISP || + (looking_for & MODE) == ABS || + (looking_for & MODE) == PCREL || + (looking_for & MODE) == INDEXB || + (looking_for & MODE) == INDEXW || + (looking_for & MODE) == INDEXL) { - if (looking_for & SRC) - rs = thisnib; - else - rd = thisnib; + extract_immediate (stream, looking_for, thisnib, + data + len / 2, cst + opnr, + cstlen + opnr, q); + /* Even address == bra, odd == bra/s. */ + if (q->how == O (O_BRAS, SB)) + cst[opnr] -= 1; } - else if (looking_for & L_16) + else if ((looking_for & MODE) == REG || + (looking_for & MODE) == LOWREG || + (looking_for & MODE) == IND || + (looking_for & MODE) == PREINC || + (looking_for & MODE) == POSTINC || + (looking_for & MODE) == PREDEC || + (looking_for & MODE) == POSTDEC) { - abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; - plen = 16; + regno[opnr] = thisnib; } - else if (looking_for & ABSJMP) + else if (looking_for & CTRL) /* Control Register */ { - abs = (data[1] << 16) | (data[2] << 8) | (data[3]); + thisnib &= 7; + if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) || + ((looking_for & MODE) == EXR && (thisnib != C_EXR)) || + ((looking_for & MODE) == MACH && (thisnib != C_MACH)) || + ((looking_for & MODE) == MACL && (thisnib != C_MACL)) || + ((looking_for & MODE) == VBR && (thisnib != C_VBR)) || + ((looking_for & MODE) == SBR && (thisnib != C_SBR))) + goto fail; + if (((looking_for & MODE) == CCR_EXR && + (thisnib != C_CCR && thisnib != C_EXR)) || + ((looking_for & MODE) == VBR_SBR && + (thisnib != C_VBR && thisnib != C_SBR)) || + ((looking_for & MODE) == MACREG && + (thisnib != C_MACH && thisnib != C_MACL))) + goto fail; + if (((looking_for & MODE) == CC_EX_VB_SB && + (thisnib != C_CCR && thisnib != C_EXR && + thisnib != C_VBR && thisnib != C_SBR))) + goto fail; + + regno[opnr] = thisnib; + } + else if ((looking_for & SIZE) == L_5) + { + cst[opnr] = data[len / 2] & 31; + cstlen[opnr] = 5; + } + else if ((looking_for & SIZE) == L_4) + { + cst[opnr] = thisnib; + cstlen[opnr] = 4; + } + else if ((looking_for & SIZE) == L_16 || + (looking_for & SIZE) == L_16U) + { + cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2]; + cstlen[opnr] = 16; + } + else if ((looking_for & MODE) == MEMIND) + { + cst[opnr] = data[1]; } - else if (looking_for & MEMIND) + else if ((looking_for & MODE) == VECIND) { - abs = data[1]; + cst[opnr] = data[1] & 0x7f; } - else if (looking_for & L_32) + else if ((looking_for & SIZE) == L_32) { - int i = len >> 1; + int i = len / 2; - abs = (data[i] << 24) - | (data[i + 1] << 16) - | (data[i + 2] << 8) - | (data[i + 3]); + cst[opnr] = ((data[i] << 24) + | (data[i + 1] << 16) + | (data[i + 2] << 8) + | (data[i + 3])); - plen = 32; + cstlen[opnr] = 32; } - else if (looking_for & L_24) + else if ((looking_for & SIZE) == L_24) { - int i = len >> 1; + int i = len / 2; - abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); - plen = 24; + cst[opnr] = + (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); + cstlen[opnr] = 24; } else if (looking_for & IGNORE) { @@ -228,64 +617,67 @@ bfd_h8_disassemble (addr, info, mode) } else if (looking_for & DISPREG) { - rdisp = thisnib; + dispregno[opnr] = thisnib & 7; } - else if (looking_for & KBIT) + else if ((looking_for & MODE) == KBIT) { switch (thisnib) { case 9: - abs = 4; + cst[opnr] = 4; break; case 8: - abs = 2; + cst[opnr] = 2; break; case 0: - abs = 1; + cst[opnr] = 1; break; default: goto fail; } } - else if (looking_for & L_8) + else if ((looking_for & SIZE) == L_8) { - plen = 8; - abs = data[len >> 1]; + cstlen[opnr] = 8; + cst[opnr] = data[len / 2]; } - else if (looking_for & L_3) + else if ((looking_for & SIZE) == L_3 || + (looking_for & SIZE) == L_3NZ) { - bit = thisnib & 0x7; + cst[opnr] = thisnib & 0x7; + if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ) + goto fail; } - else if (looking_for & L_2) + else if ((looking_for & SIZE) == L_2) { - plen = 2; - abs = thisnib & 0x3; + cstlen[opnr] = 2; + cst[opnr] = thisnib & 0x3; } - else if (looking_for & MACREG) + else if ((looking_for & MODE) == MACREG) { - abs = (thisnib == 3); + cst[opnr] = (thisnib == 3); } - else if (looking_for == E) + else if (looking_for == (op_type) E) { int i; for (i = 0; i < qi->length; i++) - fprintf (stream, "%02x ", data[i]); + outfn (stream, "%02x ", data[i]); for (; i < 6; i++) - fprintf (stream, " "); + outfn (stream, " "); - fprintf (stream, "%s\t", q->name); + outfn (stream, "%s\t", q->name); /* Gross. Disgusting. */ if (strcmp (q->name, "ldm.l") == 0) { int count, high; - count = (data[1] >> 4) & 0x3; - high = data[3] & 0x7; + count = (data[1] / 16) & 0x3; + high = regno[1]; - fprintf (stream, "@sp+,er%d-er%d", high - count, high); + outfn (stream, "@sp+,er%d-er%d", high - count, high); return qi->length; } @@ -293,121 +685,71 @@ bfd_h8_disassemble (addr, info, mode) { int count, low; - count = (data[1] >> 4) & 0x3; - low = data[3] & 0x7; + count = (data[1] / 16) & 0x3; + low = regno[0]; - fprintf (stream, "er%d-er%d,@-sp", low, low + count); + outfn (stream, "er%d-er%d,@-sp", low, low + count); + return qi->length; + } + if (strcmp (q->name, "rte/l") == 0 + || strcmp (q->name, "rts/l") == 0) + { + if (regno[0] == 0) + outfn (stream, "er%d", regno[1]); + else + { + outfn (stream, "er%d-er%d", regno[1] - regno[0], + regno[1]); + } + return qi->length; + } + if (strncmp (q->name, "mova", 4) == 0) + { + op_type *args = q->args.nib; + + if (args[1] == (op_type) E) + { + /* Short form. */ + print_one_arg (info, addr, args[0], cst[0], + cstlen[0], dispregno[0], regno[0], + pregnames, qi->length); + outfn (stream, ",er%d", dispregno[0]); + } + else + { + outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]); + print_one_arg (info, addr, args[1], cst[1], + cstlen[1], dispregno[1], regno[1], + pregnames, qi->length); + outfn (stream, ".%c),", + (args[0] & MODE) == INDEXB ? 'b' : 'w'); + print_one_arg (info, addr, args[2], cst[2], + cstlen[2], dispregno[2], regno[2], + pregnames, qi->length); + } return qi->length; } - /* Fill in the args. */ { op_type *args = q->args.nib; int hadone = 0; + int nargs; - while (*args != E) + for (nargs = 0; + nargs < 3 && args[nargs] != (op_type) E; + nargs++) { - int x = *args; + int x = args[nargs]; if (hadone) - fprintf (stream, ","); - - if (x & L_3) - { - fprintf (stream, "#0x%x", (unsigned) bit); - } - else if (x & (IMM | KBIT | DBIT)) - { - /* Bletch. For shal #2,er0 and friends. */ - if (*(args + 1) & SRC_IN_DST) - abs = 2; - - fprintf (stream, "#0x%x", (unsigned) abs); - } - else if (x & REG) - { - int rn = (x & DST) ? rd : rs; - - switch (x & SIZE) - { - case L_8: - fprintf (stream, "%s", regnames[rn]); - break; - case L_16: - fprintf (stream, "%s", wregnames[rn]); - break; - case L_P: - case L_32: - fprintf (stream, "%s", lregnames[rn]); - break; - } - } - else if (x & MACREG) - { - fprintf (stream, "mac%c", abs ? 'l' : 'h'); - } - else if (x & INC) - { - fprintf (stream, "@%s+", pregnames[rs]); - } - else if (x & DEC) - { - fprintf (stream, "@-%s", pregnames[rd]); - } - else if (x & IND) - { - int rn = (x & DST) ? rd : rs; - fprintf (stream, "@%s", pregnames[rn]); - } - else if (x & ABS8MEM) - { - fprintf (stream, "@0x%x:8", (unsigned) abs); - } - else if (x & (ABS | ABSJMP)) - { - fprintf (stream, "@0x%x:%d", (unsigned) abs, plen); - } - else if (x & MEMIND) - { - fprintf (stream, "@@%d (%x)", abs, abs); - } - else if (x & PCREL) - { - if (x & L_16) - { - abs += 2; - fprintf (stream, - ".%s%d (%x)", - (short) abs > 0 ? "+" : "", - (short) abs, addr + (short) abs + 2); - } - else - { - fprintf (stream, - ".%s%d (%x)", - (char) abs > 0 ? "+" : "", - (char) abs, addr + (char) abs + 2); - } - } - else if (x & DISP) - { - fprintf (stream, "@(0x%x:%d,%s)", - abs, plen, pregnames[rdisp]); - } - else if (x & CCR) - { - fprintf (stream, "ccr"); - } - else if (x & EXR) - { - fprintf (stream, "exr"); - } - else - /* xgettext:c-format */ - fprintf (stream, _("Hmmmm %x"), x); + outfn (stream, ","); + + print_one_arg (info, addr, x, + cst[nargs], cstlen[nargs], + dispregno[nargs], regno[nargs], + pregnames, qi->length); hadone = 1; - args++; } } @@ -415,7 +757,7 @@ bfd_h8_disassemble (addr, info, mode) } else /* xgettext:c-format */ - fprintf (stream, _("Don't understand %x \n"), looking_for); + outfn (stream, _("Don't understand 0x%x \n"), looking_for); } len++; @@ -427,7 +769,7 @@ bfd_h8_disassemble (addr, info, mode) } /* Fell off the end. */ - fprintf (stream, "%02x %02x .word\tH'%x,H'%x", + outfn (stream, "%02x %02x .word\tH'%x,H'%x", data[0], data[1], data[0], data[1]); return 2; diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index be78e83..7c03205 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -93,6 +93,7 @@ static void OP_XS PARAMS ((int, int)); static void OP_3DNowSuffix PARAMS ((int, int)); static void OP_SIMD_Suffix PARAMS ((int, int)); static void SIMD_Fixup PARAMS ((int, int)); +static void PNI_Fixup PARAMS ((int, int)); static void BadOp PARAMS ((void)); struct dis_private { @@ -417,6 +418,12 @@ fetch_data (info, addr) #define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 #define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 #define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 +#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0 +#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0 +#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0 +#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0 +#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0 +#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0 #define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 @@ -776,11 +783,11 @@ static const struct dis386 dis386_twobyte[] = { /* 10 */ { PREGRP8 }, { PREGRP9 }, - { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ + { PREGRP30 }, { "movlpX", EX, XM, SIMD_Fixup, 'h' }, { "unpcklpX", XM, EX, XX }, { "unpckhpX", XM, EX, XX }, - { "movhpX", XM, EX, SIMD_Fixup, 'l' }, + { PREGRP31 }, { "movhpX", EX, XM, SIMD_Fixup, 'l' }, /* 18 */ { GRP14 }, @@ -895,8 +902,8 @@ static const struct dis386 dis386_twobyte[] = { { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { PREGRP28 }, + { PREGRP29 }, { PREGRP23 }, { PREGRP20 }, /* 80 */ @@ -990,7 +997,7 @@ static const struct dis386 dis386_twobyte[] = { { "bswap", RMeSI, XX, XX }, { "bswap", RMeDI, XX, XX }, /* d0 */ - { "(bad)", XX, XX, XX }, + { PREGRP27 }, { "psrlw", MX, EM, XX }, { "psrld", MX, EM, XX }, { "psrlq", MX, EM, XX }, @@ -1026,7 +1033,7 @@ static const struct dis386 dis386_twobyte[] = { { "pmaxsw", MX, EM, XX }, { "pxor", MX, EM, XX }, /* f0 */ - { "(bad)", XX, XX, XX }, + { PREGRP32 }, { "psllw", MX, EM, XX }, { "pslld", MX, EM, XX }, { "psllq", MX, EM, XX }, @@ -1078,15 +1085,15 @@ static const unsigned char twobyte_has_modrm[256] = { /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */ /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ + /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1095,21 +1102,21 @@ static const unsigned char twobyte_uses_SSE_prefix[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ - /* 10 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */ /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */ - /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ + /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ + /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1349,7 +1356,7 @@ static const struct dis386 grps[][8] = { /* GRP7 */ { { "sgdtQ", M, XX, XX }, - { "sidtQ", M, XX, XX }, + { "sidtQ", PNI_Fixup, 0, XX, XX }, { "lgdtQ", M, XX, XX }, { "lidtQ", M, XX, XX }, { "smswQ", Ev, XX, XX }, @@ -1638,6 +1645,48 @@ static const struct dis386 prefix_user_table[][4] = { { "punpcklqdq", XM, EX, XX }, { "(bad)", XM, EX, XX }, }, + /* PREGRP27 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "addsubpd", XM, EX, XX }, + { "addsubps", XM, EX, XX }, + }, + /* PREGRP28 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "haddpd", XM, EX, XX }, + { "haddps", XM, EX, XX }, + }, + /* PREGRP29 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "hsubpd", XM, EX, XX }, + { "hsubps", XM, EX, XX }, + }, + /* PREGRP30 */ + { + { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ + { "movsldup", XM, EX, XX }, + { "movlpd", XM, EX, XX }, + { "movddup", XM, EX, XX }, + }, + /* PREGRP31 */ + { + { "movhpX", XM, EX, SIMD_Fixup, 'l' }, + { "movshdup", XM, EX, XX }, + { "movhpd", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP32 */ + { + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "lddqu", XM, M, XX }, + }, }; static const struct dis386 x86_64_table[][2] = { @@ -2294,7 +2343,7 @@ static const char *float_mem[] = { "fidivr{l||l|}", /* db */ "fild{l||l|}", - "(bad)", + "fisttp{l||l|}", "fist{l||l|}", "fistp{l||l|}", "(bad)", @@ -2312,7 +2361,7 @@ static const char *float_mem[] = { "fdivr{l||l|}", /* dd */ "fld{l||l|}", - "(bad)", + "fisttpll", "fst{l||l|}", "fstp{l||l|}", "frstor", @@ -2330,7 +2379,7 @@ static const char *float_mem[] = { "fidivr", /* df */ "fild", - "(bad)", + "fisttp", "fist", "fistp", "fbld", @@ -4138,6 +4187,33 @@ SIMD_Fixup (extrachar, sizeflag) } static void +PNI_Fixup (extrachar, sizeflag) + int extrachar ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + if (mod == 3 && reg == 1) + { + char *p = obuf + strlen (obuf); + + /* Override "sidt". */ + if (rm) + { + /* mwait %eax,%ecx */ + strcpy (p - 4, "mwait %eax,%ecx"); + } + else + { + /* monitor %eax,%ecx,%edx" */ + strcpy (p - 4, "monitor %eax,%ecx,%edx"); + } + + codep++; + } + else + OP_E (0, sizeflag); +} + +static void BadOp (void) { /* Throw away prefixes and 1st. opcode byte. */ diff --git a/opcodes/i860-dis.c b/opcodes/i860-dis.c index 69a106d..a3e87b0 100644 --- a/opcodes/i860-dis.c +++ b/opcodes/i860-dis.c @@ -1,5 +1,5 @@ /* Disassembler for the i860. - Copyright 2000 Free Software Foundation, Inc. + Copyright 2000, 2003 Free Software Foundation, Inc. Contributed by Jason Eckhardt <jle@cygnus.com>. @@ -37,9 +37,11 @@ static const char *const frnames[] = "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; -/* Control/status register names (encoded as 0..5 in the instruction). */ +/* Control/status register names (encoded as 0..11 in the instruction). + Registers bear, ccr, p0, p1, p2 and p3 are XP only. */ static const char *const crnames[] = - {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""}; + {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr", + "p0", "p1", "p2", "p3", "--", "--", "--", "--" }; /* Prototypes. */ @@ -190,7 +192,7 @@ print_insn_i860 (memaddr, info) /* Control register. */ case 'c': (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, - crnames[(insn >> 21) & 0x7]); + crnames[(insn >> 21) & 0xf]); break; /* 16-bit immediate (sign extend, except for bitwise ops). */ diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c index 6a1653b..524f256 100644 --- a/opcodes/ip2k-asm.c +++ b/opcodes/ip2k-asm.c @@ -908,10 +908,10 @@ ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! ip2k_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c index f8e4932..0ab2cc5 100644 --- a/opcodes/ip2k-desc.c +++ b/opcodes/ip2k-desc.c @@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] }, diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h index 84db7fb..1122026 100644 --- a/opcodes/ip2k-desc.h +++ b/opcodes/ip2k-desc.h @@ -225,7 +225,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c index 17b93eb..7fb795e 100644 --- a/opcodes/iq2000-asm.c +++ b/opcodes/iq2000-asm.c @@ -385,15 +385,15 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields) case IQ2000_OPERAND_EXECODE : errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode); break; + case IQ2000_OPERAND_F_INDEX : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_F_INDEX, &fields->f_index); + break; case IQ2000_OPERAND_HI16 : errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm); break; case IQ2000_OPERAND_IMM : errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, &fields->f_imm); break; - case IQ2000_OPERAND_INDEX : - errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_INDEX, &fields->f_index); - break; case IQ2000_OPERAND_JMPTARG : { bfd_vma value; @@ -477,9 +477,6 @@ iq2000_cgen_init_asm (cd) iq2000_cgen_init_ibld_table (cd); cd->parse_handlers = & iq2000_cgen_parse_handlers[0]; cd->parse_operand = iq2000_cgen_parse_operand; -#ifdef CGEN_ASM_INIT_HOOK -CGEN_ASM_INIT_HOOK -#endif } @@ -797,10 +794,10 @@ iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! iq2000_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c index a30bf56..6c7f3b0 100644 --- a/opcodes/iq2000-desc.c +++ b/opcodes/iq2000-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -23,7 +23,6 @@ with this program; if not, write to the Free Software Foundation, Inc., */ #include "sysdep.h" -#include <ctype.h> #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" @@ -33,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "iq2000-opc.h" #include "opintl.h" #include "libiberty.h" +#include "xregex.h" /* Attributes. */ @@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, @@ -122,7 +122,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = /* Instruction set variants. */ static const CGEN_ISA iq2000_cgen_isa_table[] = { - { "iq2000", 32, 32, 32, 32 }, + { "iq2000", 32, 32, 23, 32 }, { 0, 0, 0, 0, 0 } }; @@ -255,6 +255,9 @@ const CGEN_IFLD iq2000_cgen_ifld_table[] = { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } }, { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, + { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, @@ -295,21 +298,21 @@ const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] = { - { 0, { (void *) &(iq2000_cgen_ifld_table[5])} }, - { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, - {0,{0}} + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, + { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] = { - { 0, { (void *) &(iq2000_cgen_ifld_table[5])} }, - { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, - {0,{0}} + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, + { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] = { - { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, - { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, - {0,{0}} + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, + { 0, { (const PTR) 0 } } }; /* The operand table. */ @@ -329,133 +332,136 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] = { /* pc: program counter */ { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (void *) &(iq2000_cgen_ifld_table[0])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* rs: register Rs */ { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, { 0, { (1<<MACH_BASE) } } }, /* rt: register Rt */ { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, { 0, { (1<<MACH_BASE) } } }, /* rd: register Rd */ { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[5])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, { 0, { (1<<MACH_BASE) } } }, /* rd-rs: register Rd from Rs */ { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10, - { 2, { (void *) &(IQ2000_F_RD_RS_MULTI_IFIELD[0])} }, + { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* rd-rt: register Rd from Rt */ { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10, - { 2, { (void *) &(IQ2000_F_RD_RT_MULTI_IFIELD[0])} }, + { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* rt-rs: register Rt from Rs */ { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10, - { 2, { (void *) &(IQ2000_F_RT_RS_MULTI_IFIELD[0])} }, + { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* shamt: shift amount */ { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[6])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } }, { 0, { (1<<MACH_BASE) } } }, /* imm: immediate */ { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, { 0, { (1<<MACH_BASE) } } }, /* offset: pc-relative offset */ { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[14])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* baseoff: base register offset */ { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, { 0, { (1<<MACH_BASE) } } }, /* jmptarg: jump target */ { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[12])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* mask: mask */ { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4, - { 0, { (void *) &(iq2000_cgen_ifld_table[18])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } }, { 0, { (1<<MACH_BASE) } } }, /* maskq10: iq10 mask */ { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[19])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } }, { 0, { (1<<MACH_BASE) } } }, /* maskl: mask left */ { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[20])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } }, { 0, { (1<<MACH_BASE) } } }, /* count: count */ { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7, - { 0, { (void *) &(iq2000_cgen_ifld_table[15])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } }, { 0, { (1<<MACH_BASE) } } }, -/* index: index */ - { "index", IQ2000_OPERAND_INDEX, HW_H_UINT, 8, 9, - { 0, { (void *) &(iq2000_cgen_ifld_table[17])} }, +/* f-index: index */ + { "f-index", IQ2000_OPERAND_F_INDEX, HW_H_UINT, 8, 9, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } }, { 0, { (1<<MACH_BASE) } } }, /* execode: execcode */ { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20, - { 0, { (void *) &(iq2000_cgen_ifld_table[21])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } }, { 0, { (1<<MACH_BASE) } } }, /* bytecount: byte count */ { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8, - { 0, { (void *) &(iq2000_cgen_ifld_table[16])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } }, { 0, { (1<<MACH_BASE) } } }, /* cam-y: cam global opn y */ { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3, - { 0, { (void *) &(iq2000_cgen_ifld_table[29])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } }, { 0, { (1<<MACH_BASE) } } }, /* cam-z: cam global mask z */ { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3, - { 0, { (void *) &(iq2000_cgen_ifld_table[28])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } }, { 0, { (1<<MACH_BASE) } } }, /* cm-3func: CM 3 bit fn field */ { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3, - { 0, { (void *) &(iq2000_cgen_ifld_table[30])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } }, { 0, { (1<<MACH_BASE) } } }, /* cm-4func: CM 4 bit fn field */ { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4, - { 0, { (void *) &(iq2000_cgen_ifld_table[31])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } }, { 0, { (1<<MACH_BASE) } } }, /* cm-3z: CM 3 bit Z field */ { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2, - { 0, { (void *) &(iq2000_cgen_ifld_table[32])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } }, { 0, { (1<<MACH_BASE) } } }, /* cm-4z: CM 4 bit Z field */ { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3, - { 0, { (void *) &(iq2000_cgen_ifld_table[33])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } }, { 0, { (1<<MACH_BASE) } } }, /* base: base register */ { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, { 0, { (1<<MACH_BASE) } } }, /* maskr: mask right */ { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, { 0, { (1<<MACH_BASE) } } }, /* bitnum: bit number */ { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5, - { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, { 0, { (1<<MACH_BASE) } } }, /* hi16: high 16 bit immediate */ { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, { 0, { (1<<MACH_BASE) } } }, /* lo16: 16 bit signed immediate, for low */ { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, { 0, { (1<<MACH_BASE) } } }, /* mlo16: negated 16 bit signed immediate */ { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16, - { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, { 0, { (1<<MACH_BASE) } } }, /* jmptargq10: iq10 21-bit jump offset */ { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21, - { 0, { (void *) &(iq2000_cgen_ifld_table[13])} }, + { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, {0, {0}}, {0, {0}} } +/* sentinel */ + { 0, 0, 0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { 0 } } } }; #undef A @@ -1161,14 +1167,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = IQ2000_INSN_PKRL, "pkrl", "pkrl", 32, { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } } }, -/* pkrlr1 $rt,$index,$count */ +/* pkrlr1 $rt,$count */ { - IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32, + IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* pkrlr30 $rt,$index,$count */ +/* pkrlr30 $rt,$count */ { - IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32, + IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, /* rb $rd,$rt */ @@ -1176,14 +1182,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = IQ2000_INSN_RB, "rb", "rb", 32, { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } } }, -/* rbr1 $rt,$index,$count */ +/* rbr1 $rt,$count */ { - IQ2000_INSN_RBR1, "rbr1", "rbr1", 32, + IQ2000_INSN_RBR1, "rbr1", "rbr1", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* rbr30 $rt,$index,$count */ +/* rbr30 $rt,$count */ { - IQ2000_INSN_RBR30, "rbr30", "rbr30", 32, + IQ2000_INSN_RBR30, "rbr30", "rbr30", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, /* rfe */ @@ -1196,14 +1202,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = IQ2000_INSN_RX, "rx", "rx", 32, { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } } }, -/* rxr1 $rt,$index,$count */ +/* rxr1 $rt,$count */ { - IQ2000_INSN_RXR1, "rxr1", "rxr1", 32, + IQ2000_INSN_RXR1, "rxr1", "rxr1", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* rxr30 $rt,$index,$count */ +/* rxr30 $rt,$count */ { - IQ2000_INSN_RXR30, "rxr30", "rxr30", 32, + IQ2000_INSN_RXR30, "rxr30", "rxr30", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, /* sleep */ @@ -1261,24 +1267,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = IQ2000_INSN_WBU, "wbu", "wbu", 32, { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } } }, -/* wbr1 $rt,$index,$count */ +/* wbr1 $rt,$count */ { - IQ2000_INSN_WBR1, "wbr1", "wbr1", 32, + IQ2000_INSN_WBR1, "wbr1", "wbr1", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wbr1u $rt,$index,$count */ +/* wbr1u $rt,$count */ { - IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32, + IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wbr30 $rt,$index,$count */ +/* wbr30 $rt,$count */ { - IQ2000_INSN_WBR30, "wbr30", "wbr30", 32, + IQ2000_INSN_WBR30, "wbr30", "wbr30", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wbr30u $rt,$index,$count */ +/* wbr30u $rt,$count */ { - IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32, + IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, /* wx $rd,$rt */ @@ -1291,24 +1297,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = IQ2000_INSN_WXU, "wxu", "wxu", 32, { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } } }, -/* wxr1 $rt,$index,$count */ +/* wxr1 $rt,$count */ { - IQ2000_INSN_WXR1, "wxr1", "wxr1", 32, + IQ2000_INSN_WXR1, "wxr1", "wxr1", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wxr1u $rt,$index,$count */ +/* wxr1u $rt,$count */ { - IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32, + IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wxr30 $rt,$index,$count */ +/* wxr30 $rt,$count */ { - IQ2000_INSN_WXR30, "wxr30", "wxr30", 32, + IQ2000_INSN_WXR30, "wxr30", "wxr30", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, -/* wxr30u $rt,$index,$count */ +/* wxr30u $rt,$count */ { - IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32, + IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 23, { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } } }, /* ldw $rt,$lo16($base) */ @@ -2181,7 +2187,7 @@ iq2000_cgen_cpu_close (cd) CGEN_CPU_DESC cd; { unsigned int i; - CGEN_INSN *insns; + const CGEN_INSN *insns; if (cd->macro_insn_table.init_entries) { @@ -2189,7 +2195,7 @@ iq2000_cgen_cpu_close (cd) for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) { if (CGEN_INSN_RX ((insns))) - regfree(CGEN_INSN_RX (insns)); + regfree (CGEN_INSN_RX (insns)); } } @@ -2199,7 +2205,7 @@ iq2000_cgen_cpu_close (cd) for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) { if (CGEN_INSN_RX (insns)) - regfree(CGEN_INSN_RX (insns)); + regfree (CGEN_INSN_RX (insns)); } } diff --git a/opcodes/iq2000-desc.h b/opcodes/iq2000-desc.h index 584c3ded..13b4f56 100644 --- a/opcodes/iq2000-desc.h +++ b/opcodes/iq2000-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -42,7 +42,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INSN_LSB0_P 1 /* Minimum size of any insn (in bytes). */ -#define CGEN_MIN_INSN_SIZE 4 +#define CGEN_MIN_INSN_SIZE 3 /* Maximum size of any insn (in bytes). */ #define CGEN_MAX_INSN_SIZE 4 @@ -255,7 +255,7 @@ typedef enum cgen_operand_type { , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT - , IQ2000_OPERAND_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y + , IQ2000_OPERAND_F_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10 @@ -273,7 +273,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c index 49e0120..b1bfa0e 100644 --- a/opcodes/iq2000-dis.c +++ b/opcodes/iq2000-dis.c @@ -4,7 +4,8 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "dis-asm.h" #include "bfd.h" #include "symcat.h" +#include "libiberty.h" #include "iq2000-desc.h" #include "iq2000-opc.h" #include "opintl.h" @@ -127,15 +129,15 @@ iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) case IQ2000_OPERAND_EXECODE : print_normal (cd, info, fields->f_excode, 0, pc, length); break; + case IQ2000_OPERAND_F_INDEX : + print_normal (cd, info, fields->f_index, 0, pc, length); + break; case IQ2000_OPERAND_HI16 : print_normal (cd, info, fields->f_imm, 0, pc, length); break; case IQ2000_OPERAND_IMM : print_normal (cd, info, fields->f_imm, 0, pc, length); break; - case IQ2000_OPERAND_INDEX : - print_normal (cd, info, fields->f_index, 0, pc, length); - break; case IQ2000_OPERAND_JMPTARG : print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); break; diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c index 5a29228..4917d9f 100644 --- a/opcodes/iq2000-ibld.c +++ b/opcodes/iq2000-ibld.c @@ -35,9 +35,9 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -605,15 +605,15 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc) case IQ2000_OPERAND_EXECODE : errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer); break; + case IQ2000_OPERAND_F_INDEX : + errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer); + break; case IQ2000_OPERAND_HI16 : errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); break; case IQ2000_OPERAND_IMM : errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); break; - case IQ2000_OPERAND_INDEX : - errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer); - break; case IQ2000_OPERAND_JMPTARG : { long value = fields->f_jtarg; @@ -788,15 +788,15 @@ iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case IQ2000_OPERAND_EXECODE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode); break; + case IQ2000_OPERAND_F_INDEX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index); + break; case IQ2000_OPERAND_HI16 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); break; case IQ2000_OPERAND_IMM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); break; - case IQ2000_OPERAND_INDEX : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index); - break; case IQ2000_OPERAND_JMPTARG : { long value; @@ -961,15 +961,15 @@ iq2000_cgen_get_int_operand (cd, opindex, fields) case IQ2000_OPERAND_EXECODE : value = fields->f_excode; break; + case IQ2000_OPERAND_F_INDEX : + value = fields->f_index; + break; case IQ2000_OPERAND_HI16 : value = fields->f_imm; break; case IQ2000_OPERAND_IMM : value = fields->f_imm; break; - case IQ2000_OPERAND_INDEX : - value = fields->f_index; - break; case IQ2000_OPERAND_JMPTARG : value = fields->f_jtarg; break; @@ -1075,15 +1075,15 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields) case IQ2000_OPERAND_EXECODE : value = fields->f_excode; break; + case IQ2000_OPERAND_F_INDEX : + value = fields->f_index; + break; case IQ2000_OPERAND_HI16 : value = fields->f_imm; break; case IQ2000_OPERAND_IMM : value = fields->f_imm; break; - case IQ2000_OPERAND_INDEX : - value = fields->f_index; - break; case IQ2000_OPERAND_JMPTARG : value = fields->f_jtarg; break; @@ -1198,15 +1198,15 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value) case IQ2000_OPERAND_EXECODE : fields->f_excode = value; break; + case IQ2000_OPERAND_F_INDEX : + fields->f_index = value; + break; case IQ2000_OPERAND_HI16 : fields->f_imm = value; break; case IQ2000_OPERAND_IMM : fields->f_imm = value; break; - case IQ2000_OPERAND_INDEX : - fields->f_index = value; - break; case IQ2000_OPERAND_JMPTARG : fields->f_jtarg = value; break; @@ -1309,15 +1309,15 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value) case IQ2000_OPERAND_EXECODE : fields->f_excode = value; break; + case IQ2000_OPERAND_F_INDEX : + fields->f_index = value; + break; case IQ2000_OPERAND_HI16 : fields->f_imm = value; break; case IQ2000_OPERAND_IMM : fields->f_imm = value; break; - case IQ2000_OPERAND_INDEX : - fields->f_index = value; - break; case IQ2000_OPERAND_JMPTARG : fields->f_jtarg = value; break; diff --git a/opcodes/iq2000-opc.c b/opcodes/iq2000-opc.c index fe8cf64..35ffdf0 100644 --- a/opcodes/iq2000-opc.c +++ b/opcodes/iq2000-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -166,7 +166,7 @@ static const CGEN_IFMT ifmt_lulck = { }; static const CGEN_IFMT ifmt_pkrlr1 = { - 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { F (F_INDEX) }, { 0 } } + 23, 23, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { 0 } } }; static const CGEN_IFMT ifmt_rfe = { @@ -1070,16 +1070,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, & ifmt_chkhdr, { 0x4c200007 } }, -/* pkrlr1 $rt,$index,$count */ +/* pkrlr1 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4fa00000 } }, -/* pkrlr30 $rt,$index,$count */ +/* pkrlr30 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4fe00000 } }, /* rb $rd,$rt */ @@ -1088,16 +1088,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, & ifmt_chkhdr, { 0x4c200004 } }, -/* rbr1 $rt,$index,$count */ +/* rbr1 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4f000000 } }, -/* rbr30 $rt,$index,$count */ +/* rbr30 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4f400000 } }, /* rfe */ @@ -1112,16 +1112,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, & ifmt_chkhdr, { 0x4c200006 } }, -/* rxr1 $rt,$index,$count */ +/* rxr1 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4f800000 } }, -/* rxr30 $rt,$index,$count */ +/* rxr30 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4fc00000 } }, /* sleep */ @@ -1190,28 +1190,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, & ifmt_chkhdr, { 0x4c200001 } }, -/* wbr1 $rt,$index,$count */ +/* wbr1 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4e000000 } }, -/* wbr1u $rt,$index,$count */ +/* wbr1u $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4e200000 } }, -/* wbr30 $rt,$index,$count */ +/* wbr30 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4e400000 } }, -/* wbr30u $rt,$index,$count */ +/* wbr30u $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4e600000 } }, /* wx $rd,$rt */ @@ -1226,28 +1226,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, & ifmt_chkhdr, { 0x4c200003 } }, -/* wxr1 $rt,$index,$count */ +/* wxr1 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4e800000 } }, -/* wxr1u $rt,$index,$count */ +/* wxr1u $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4ea00000 } }, -/* wxr30 $rt,$index,$count */ +/* wxr30 $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4ec00000 } }, -/* wxr30u $rt,$index,$count */ +/* wxr30u $rt,$count */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, & ifmt_pkrlr1, { 0x4ee00000 } }, /* ldw $rt,$lo16($base) */ diff --git a/opcodes/iq2000-opc.h b/opcodes/iq2000-opc.h index 4dca525..1242cea 100644 --- a/opcodes/iq2000-opc.h +++ b/opcodes/iq2000-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 4abe187..2bd751a 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -659,10 +659,10 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! m32r_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c index 30a0719..023ab62 100644 --- a/opcodes/m32r-desc.c +++ b/opcodes/m32r-desc.c @@ -118,7 +118,7 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index 85e22ee..8781772 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -204,7 +204,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE , CGEN_INSN_END_NBOOLS diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index b60c1bf..8143b61 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -1187,7 +1187,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bc $disp24 */ { -1, "bc24r", "bc", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bl $disp8 */ { @@ -1197,7 +1197,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bl $disp24 */ { -1, "bl24r", "bl", 32, - { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bcl $disp8 */ { @@ -1207,7 +1207,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bcl $disp24 */ { -1, "bcl24r", "bcl", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, /* bnc $disp8 */ { @@ -1217,7 +1217,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bnc $disp24 */ { -1, "bnc24r", "bnc", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bra $disp8 */ { @@ -1227,7 +1227,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bra $disp24 */ { -1, "bra24r", "bra", 32, - { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bncl $disp8 */ { @@ -1237,7 +1237,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bncl $disp24 */ { -1, "bncl24r", "bncl", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, /* ld $dr,@($sr) */ { diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c index d47659b..26b2625 100644 --- a/opcodes/openrisc-asm.c +++ b/opcodes/openrisc-asm.c @@ -578,10 +578,10 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! openrisc_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c index 6de9107..989b195 100644 --- a/opcodes/openrisc-desc.c +++ b/opcodes/openrisc-desc.c @@ -112,7 +112,7 @@ const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h index d1edee2..0c7df17 100644 --- a/opcodes/openrisc-desc.h +++ b/opcodes/openrisc-desc.h @@ -223,7 +223,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; diff --git a/opcodes/po/Make-in b/opcodes/po/Make-in index 0552db1..6176dbf 100644 --- a/opcodes/po/Make-in +++ b/opcodes/po/Make-in @@ -24,6 +24,8 @@ gnulocaledir = $(prefix)/share/locale gettextsrcdir = $(prefix)/share/gettext/po subdir = po +DESTDIR = + INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ MKINSTALLDIRS = @MKINSTALLDIRS@ @@ -111,9 +113,9 @@ install-data: install-data-@USE_NLS@ install-data-no: all install-data-yes: all if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(datadir); \ + $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \ else \ - $(top_srcdir)/mkinstalldirs $(datadir); \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \ fi @catalogs='$(CATALOGS)'; \ for cat in $$catalogs; do \ @@ -123,7 +125,7 @@ install-data-yes: all *) destdir=$(localedir);; \ esac; \ lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$$destdir/$$lang/LC_MESSAGES; \ + dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \ if test -r $(MKINSTALLDIRS); then \ $(MKINSTALLDIRS) $$dir; \ else \ @@ -153,12 +155,12 @@ install-data-yes: all done if test "$(PACKAGE)" = "gettext"; then \ if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(gettextsrcdir); \ + $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \ else \ - $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \ fi; \ $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(gettextsrcdir)/Makefile.in.in; \ + $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \ else \ : ; \ fi @@ -171,12 +173,12 @@ uninstall: for cat in $$catalogs; do \ cat=`basename $$cat`; \ lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ done - rm -f $(gettextsrcdir)/po-Makefile.in.in + rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in check: all diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index 9a14a1d..df9060e 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -137,6 +137,7 @@ xstormy16-dis.c xstormy16-ibld.c xstormy16-opc.c xstormy16-opc.h +xtensa-dis.c z8k-dis.c z8k-opc.h z8kgen.c diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot index fbc549d..ee61ca6 100644 --- a/opcodes/po/opcodes.pot +++ b/opcodes/po/opcodes.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2002-02-08 03:24-0200\n" +"POT-Creation-Date: 2003-06-05 11:34+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -26,47 +26,47 @@ msgstr "" msgid "Illegal limm reference in last instruction!\n" msgstr "" -#: arm-dis.c:502 +#: arm-dis.c:554 msgid "<illegal precision>" msgstr "" -#: arm-dis.c:1012 +#: arm-dis.c:1162 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" -#: arm-dis.c:1019 +#: arm-dis.c:1169 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:1191 +#: arm-dis.c:1343 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" "the -M switch:\n" msgstr "" -#: avr-dis.c:118 avr-dis.c:128 +#: avr-dis.c:117 avr-dis.c:127 msgid "undefined" msgstr "" -#: avr-dis.c:180 +#: avr-dis.c:179 msgid "Internal disassembler error" msgstr "" -#: avr-dis.c:228 +#: avr-dis.c:227 #, c-format msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 -#: xstormy16-ibld.c:195 +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" -#: cgen-asm.c:367 +#: cgen-asm.c:369 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" @@ -87,112 +87,134 @@ msgstr "" msgid "Address 0x%x is out of bounds.\n" msgstr "" -#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231 +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:244 xstormy16-asm.c:284 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281 +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:294 xstormy16-asm.c:334 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 -#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 -#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 -#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 -#: xstormy16-asm.c:610 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464 +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:477 xstormy16-asm.c:517 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474 +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:487 xstormy16-asm.c:527 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502 +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:515 xstormy16-asm.c:555 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609 +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621 +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624 +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 -#: xstormy16-dis.c:39 +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169 +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "" -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 -#: xstormy16-ibld.c:1224 +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:384 +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "" + +#: h8300-dis.c:377 #, c-format -msgid "Hmmmm %x" +msgid "Hmmmm 0x%x" msgstr "" -#: h8300-dis.c:395 +#: h8300-dis.c:760 #, c-format -msgid "Don't understand %x \n" +msgid "Don't understand 0x%x \n" msgstr "" #: h8500-dis.c:143 @@ -206,10 +228,185 @@ msgstr "" msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:1649 +#: i386-dis.c:1650 msgid "<internal disassembler error>" msgstr "" +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "" + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "" + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "" + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "" + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "" + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "" + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "" + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "" + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +msgid "missing `)'" +msgstr "" + #: m10200-dis.c:199 #, c-format msgid "unknown\t0x%02x" @@ -235,21 +432,99 @@ msgstr "" msgid "<function code %d>" msgstr "" -#: m88k-dis.c:255 +#: m88k-dis.c:746 #, c-format msgid "# <dis error: %08x>" msgstr "" -#: mips-dis.c:290 +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "" + +#: mips-dis.c:1000 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" -#: mips-dis.c:1154 +#: mips-dis.c:1751 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "" +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" + #: mmix-dis.c:34 #, c-format msgid "Bad case %d (%s) in %s:%d\n" @@ -264,7 +539,7 @@ msgstr "" msgid "(unknown)" msgstr "" -#: mmix-dis.c:517 +#: mmix-dis.c:519 #, c-format msgid "*unknown operands type: %d*" msgstr "" @@ -275,76 +550,96 @@ msgstr "" #. * aoffsetp by since whatever generated this is broken #. * anyway! #. -#: ns32k-dis.c:628 +#: ns32k-dis.c:631 msgid "$<undefined>" msgstr "" -#: ppc-opc.c:765 ppc-opc.c:798 +#: ppc-opc.c:818 ppc-opc.c:851 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:800 +#: ppc-opc.c:853 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:832 ppc-opc.c:884 +#: ppc-opc.c:881 +msgid "offset not a multiple of 2" +msgstr "" + +#: ppc-opc.c:883 +msgid "offset greater than 62" +msgstr "" + +#: ppc-opc.c:904 ppc-opc.c:954 ppc-opc.c:1006 msgid "offset not a multiple of 4" msgstr "" -#: ppc-opc.c:857 +#: ppc-opc.c:906 +msgid "offset greater than 124" +msgstr "" + +#: ppc-opc.c:927 +msgid "offset not a multiple of 8" +msgstr "" + +#: ppc-opc.c:929 +msgid "offset greater than 248" +msgstr "" + +#: ppc-opc.c:979 msgid "offset not between -2048 and 2047" msgstr "" -#: ppc-opc.c:882 +#: ppc-opc.c:1004 msgid "offset not between -8192 and 8191" msgstr "" -#: ppc-opc.c:910 +#: ppc-opc.c:1032 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:944 ppc-opc.c:981 +#: ppc-opc.c:1066 ppc-opc.c:1103 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:1054 +#: ppc-opc.c:1176 msgid "value out of range" msgstr "" -#: ppc-opc.c:1130 +#: ppc-opc.c:1252 msgid "index register in load range" msgstr "" -#: ppc-opc.c:1146 +#: ppc-opc.c:1268 msgid "invalid register operand when updating" msgstr "" -#. Mark as non-valid instruction -#: sparc-dis.c:750 +#. Mark as non-valid instruction. +#: sparc-dis.c:760 msgid "unknown" msgstr "" -#: sparc-dis.c:825 +#: sparc-dis.c:835 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:836 +#: sparc-dis.c:846 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:885 +#: sparc-dis.c:895 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" -#: v850-dis.c:224 +#: v850-dis.c:221 #, c-format msgid "unknown operand shift: %x\n" msgstr "" -#: v850-dis.c:236 +#: v850-dis.c:233 #, c-format msgid "unknown pop reg: %d\n" msgstr "" @@ -398,30 +693,42 @@ msgstr "" msgid "immediate value must be even" msgstr "" -#: xstormy16-asm.c:74 +#: xstormy16-asm.c:76 msgid "Bad register in preincrement" msgstr "" -#: xstormy16-asm.c:79 +#: xstormy16-asm.c:81 msgid "Bad register in postincrement" msgstr "" -#: xstormy16-asm.c:81 +#: xstormy16-asm.c:83 msgid "Bad register name" msgstr "" -#: xstormy16-asm.c:85 +#: xstormy16-asm.c:87 msgid "Label conflicts with register name" msgstr "" -#: xstormy16-asm.c:89 +#: xstormy16-asm.c:91 msgid "Label conflicts with `Rx'" msgstr "" -#: xstormy16-asm.c:91 +#: xstormy16-asm.c:93 msgid "Bad immediate expression" msgstr "" -#: xstormy16-asm.c:120 +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "" + +#: xstormy16-asm.c:125 msgid "Small operand was not an immediate number" msgstr "" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 27eb23e..a6e9313 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -68,6 +68,10 @@ static unsigned long insert_boe PARAMS ((unsigned long, long, int, const char **)); static long extract_boe PARAMS ((unsigned long, int, int *)); +static unsigned long insert_dq + PARAMS ((unsigned long, long, int, const char **)); +static long extract_dq + PARAMS ((unsigned long, int, int *)); static unsigned long insert_ds PARAMS ((unsigned long, long, int, const char **)); static long extract_ds @@ -104,12 +108,18 @@ static unsigned long insert_ral PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_ram PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_raq + PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_ras PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_rbs PARAMS ((unsigned long, long, int, const char **)); static long extract_rbs PARAMS ((unsigned long, int, int *)); +static unsigned long insert_rsq + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_rtq + PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_sh6 PARAMS ((unsigned long, long, int, const char **)); static long extract_sh6 @@ -279,9 +289,15 @@ const struct powerpc_operand powerpc_operands[] = #define DES DE + 1 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ +#define DQ DES + 1 + { 16, 0, insert_dq, extract_dq, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ -#define DS DES + 1 +#define DS DQ + 1 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, @@ -389,15 +405,20 @@ const struct powerpc_operand powerpc_operands[] = { 16, 0, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ + /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ #define RA NSI + 1 #define RA_MASK (0x1f << 16) { 5, 16, 0, 0, PPC_OPERAND_GPR }, + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ +#define RAQ RA + 1 + { 5, 16, insert_raq, 0, PPC_OPERAND_GPR }, + /* The RA field in a D or X form instruction which is an updating load, which means that the RA field may not be zero and may not equal the RT field. */ -#define RAL RA + 1 +#define RAL RAQ + 1 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, /* The RA field in an lmw instruction, which has special value @@ -430,8 +451,18 @@ const struct powerpc_operand powerpc_operands[] = #define RT_MASK (0x1f << 21) { 5, 21, 0, 0, PPC_OPERAND_GPR }, + /* The RS field of the DS form stq instruction, which has special + value restrictions. */ +#define RSQ RS + 1 + { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR }, + + /* The RT field of the DQ form lq instruction, which has special + value restrictions. */ +#define RTQ RSQ + 1 + { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR }, + /* The SH field in an X or M form instruction. */ -#define SH RS + 1 +#define SH RTQ + 1 #define SH_MASK (0x1f << 11) { 5, 11, 0, 0, 0 }, @@ -870,6 +901,32 @@ extract_boe (insn, dialect, invalid) return value & 0x1e; } + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ + +/*ARGSUSED*/ +static unsigned long +insert_dq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char ** errmsg ATTRIBUTE_UNUSED; +{ + if ((value & 0xf) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 16"); + return insn | (value & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_dq (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn & 0xfff0) ^ 0x8000) - 0x8000; +} + static unsigned long insert_ev2 (insn, value, dialect, errmsg) unsigned long insn; @@ -1253,6 +1310,24 @@ insert_ram (insn, value, dialect, errmsg) return insn | ((value & 0x1f) << 16); } + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_raq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + long rtvalue = (insn & RT_MASK) >> 21; + + if (value == rtvalue && errmsg != NULL) + *errmsg = _("source and target register operands must be different"); + return insn | ((value & 0x1f) << 16); +} + /* The RA field in a D or X form instruction which is an updating store or an updating floating point load, which means that the RA field may not be zero. */ @@ -1298,6 +1373,38 @@ extract_rbs (insn, dialect, invalid) return 0; } + /* The RT field of the DQ form lq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_rtq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 1) != 0 && errmsg != NULL) + *errmsg = _("target register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + + /* The RS field of the DS form stq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_rsq (insn, value, dialect, errmsg) + unsigned long insn; + long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 1) != 0 && errmsg != NULL) + *errmsg = _("source register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + /* The SH field in an MD form instruction. This is split. */ /*ARGSUSED*/ @@ -1768,6 +1875,7 @@ extract_tbr (insn, dialect, invalid) sorted by major opcode. */ const struct powerpc_opcode powerpc_opcodes[] = { +{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, @@ -4335,6 +4443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, +{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, + { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, @@ -4411,6 +4521,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, +{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } }, + { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c index 324c091..810938c 100644 --- a/opcodes/xstormy16-asm.c +++ b/opcodes/xstormy16-asm.c @@ -618,10 +618,10 @@ xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg) if (! xstormy16_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c index 9c9f30b..1c94fd7 100644 --- a/opcodes/xstormy16-desc.c +++ b/opcodes/xstormy16-desc.c @@ -104,7 +104,7 @@ const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h index a880321..e613505 100644 --- a/opcodes/xstormy16-desc.h +++ b/opcodes/xstormy16-desc.h @@ -261,7 +261,7 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c index 69d1792..5d15ee8 100644 --- a/opcodes/z8k-dis.c +++ b/opcodes/z8k-dis.c @@ -1,5 +1,5 @@ /* Disassemble z8000 code. - Copyright 1992, 1993, 1998, 2000, 2001, 2002 + Copyright 1992, 1993, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of GNU Binutils. @@ -40,7 +40,7 @@ typedef struct bfd_vma insn_start; jmp_buf bailout; - long tabl_index; + int tabl_index; char instr_asmsrc[80]; unsigned long arg_reg[0x0f]; unsigned long immediate; @@ -169,7 +169,7 @@ print_insn_z8k (addr, info, is_segmented) info->display_endian = BFD_ENDIAN_BIG; instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); - if (instr_data.tabl_index > 0) + if (instr_data.tabl_index >= 0) { unpack_instr (&instr_data, is_segmented, info); unparse_instr (&instr_data, is_segmented); @@ -581,6 +581,10 @@ unparse_instr (instr_data, is_segmented) sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); strcat (out_str, tmp_str); break; + case CLASS_IRO: + sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; case CLASS_FLAGS: sprintf (tmp_str, "0x%0lx", instr_data->flags); strcat (out_str, tmp_str); diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h index 022f581..c714bde 100644 --- a/opcodes/z8k-opc.h +++ b/opcodes/z8k-opc.h @@ -26,7 +26,6 @@ #define ARG_NIM4 0x0c #define ARG_DISP8 0x0c #define ARG_IMM4M1 0x0d -#define CLASS_MASK 0x1fff0 #define CLASS_X 0x10 #define CLASS_BA 0x20 #define CLASS_DA 0x30 @@ -46,8 +45,9 @@ #define CLASS_BIT 0x500 #define CLASS_FLAGS 0x600 #define CLASS_IR 0x700 -#define CLASS_DISP8 0x800 -#define CLASS_BIT_1OR2 0x900 +#define CLASS_IRO 0x800 +#define CLASS_DISP8 0x900 +#define CLASS_BIT_1OR2 0xa00 #define CLASS_REG 0x7000 #define CLASS_REG_BYTE 0x2000 #define CLASS_REG_WORD 0x3000 @@ -55,6 +55,7 @@ #define CLASS_REG_LONG 0x5000 #define CLASS_REGN0 0x8000 #define CLASS_PR 0x10000 +#define CLASS_MASK 0x1fff0 #define OPC_adc 0 #define OPC_adcb 1 #define OPC_add 2 @@ -111,138 +112,154 @@ #define OPC_incb 53 #define OPC_ind 54 #define OPC_indb 55 -#define OPC_inib 56 -#define OPC_inibr 57 -#define OPC_iret 58 -#define OPC_jp 59 -#define OPC_jr 60 -#define OPC_ld 61 -#define OPC_lda 62 -#define OPC_ldar 63 -#define OPC_ldb 64 -#define OPC_ldctl 65 -#define OPC_ldir 66 -#define OPC_ldirb 67 -#define OPC_ldk 68 -#define OPC_ldl 69 -#define OPC_ldm 70 -#define OPC_ldps 71 -#define OPC_ldr 72 -#define OPC_ldrb 73 -#define OPC_ldrl 74 -#define OPC_mbit 75 -#define OPC_mreq 76 -#define OPC_mres 77 -#define OPC_mset 78 -#define OPC_mult 79 -#define OPC_multl 80 -#define OPC_neg 81 -#define OPC_negb 82 -#define OPC_nop 83 -#define OPC_or 84 -#define OPC_orb 85 -#define OPC_out 86 -#define OPC_outb 87 -#define OPC_outd 88 -#define OPC_outdb 89 -#define OPC_outib 90 -#define OPC_outibr 91 -#define OPC_pop 92 -#define OPC_popl 93 -#define OPC_push 94 -#define OPC_pushl 95 -#define OPC_res 96 -#define OPC_resb 97 -#define OPC_resflg 98 -#define OPC_ret 99 -#define OPC_rl 100 -#define OPC_rlb 101 -#define OPC_rlc 102 -#define OPC_rlcb 103 -#define OPC_rldb 104 -#define OPC_rr 105 -#define OPC_rrb 106 -#define OPC_rrc 107 -#define OPC_rrcb 108 -#define OPC_rrdb 109 -#define OPC_sbc 110 -#define OPC_sbcb 111 -#define OPC_sda 112 -#define OPC_sdab 113 -#define OPC_sdal 114 -#define OPC_sdl 115 -#define OPC_sdlb 116 -#define OPC_sdll 117 -#define OPC_set 118 -#define OPC_setb 119 -#define OPC_setflg 120 -#define OPC_sinb 121 -#define OPC_sind 122 -#define OPC_sindb 123 -#define OPC_sinib 124 -#define OPC_sinibr 125 -#define OPC_sla 126 -#define OPC_slab 127 -#define OPC_slal 128 -#define OPC_sll 129 -#define OPC_sllb 130 -#define OPC_slll 131 -#define OPC_sout 132 -#define OPC_soutb 133 -#define OPC_soutd 134 -#define OPC_soutdb 135 -#define OPC_soutib 136 -#define OPC_soutibr 137 -#define OPC_sra 138 -#define OPC_srab 139 -#define OPC_sral 140 -#define OPC_srl 141 -#define OPC_srlb 142 -#define OPC_srll 143 -#define OPC_sub 144 -#define OPC_subb 145 -#define OPC_subl 146 -#define OPC_tcc 147 -#define OPC_tccb 148 -#define OPC_test 149 -#define OPC_testb 150 -#define OPC_testl 151 -#define OPC_trdb 152 -#define OPC_trdrb 153 -#define OPC_trib 154 -#define OPC_trirb 155 -#define OPC_trtdrb 156 -#define OPC_trtib 157 -#define OPC_trtirb 158 -#define OPC_trtrb 159 -#define OPC_tset 160 -#define OPC_tsetb 161 -#define OPC_xor 162 -#define OPC_xorb 163 -#define OPC_ldd 164 -#define OPC_lddb 165 -#define OPC_lddr 166 -#define OPC_lddrb 167 -#define OPC_ldi 168 -#define OPC_ldib 169 -#define OPC_sc 170 -#define OPC_bpt 171 -#define OPC_ext0e 172 -#define OPC_ext0f 172 -#define OPC_ext8e 172 -#define OPC_ext8f 172 -#define OPC_rsvd36 172 -#define OPC_rsvd38 172 -#define OPC_rsvd78 172 -#define OPC_rsvd7e 172 -#define OPC_rsvd9d 172 -#define OPC_rsvd9f 172 -#define OPC_rsvdb9 172 -#define OPC_rsvdbf 172 -#define OPC_outi 173 -#define OPC_ldctlb 174 -#define OPC_sin 175 -#define OPC_trtdb 176 +#define OPC_indr 56 +#define OPC_indrb 57 +#define OPC_ini 58 +#define OPC_inib 59 +#define OPC_inir 60 +#define OPC_inirb 61 +#define OPC_iret 62 +#define OPC_jp 63 +#define OPC_jr 64 +#define OPC_ld 65 +#define OPC_lda 66 +#define OPC_ldar 67 +#define OPC_ldb 68 +#define OPC_ldctl 69 +#define OPC_ldir 70 +#define OPC_ldirb 71 +#define OPC_ldk 72 +#define OPC_ldl 73 +#define OPC_ldm 74 +#define OPC_ldps 75 +#define OPC_ldr 76 +#define OPC_ldrb 77 +#define OPC_ldrl 78 +#define OPC_mbit 79 +#define OPC_mreq 80 +#define OPC_mres 81 +#define OPC_mset 82 +#define OPC_mult 83 +#define OPC_multl 84 +#define OPC_neg 85 +#define OPC_negb 86 +#define OPC_nop 87 +#define OPC_or 88 +#define OPC_orb 89 +#define OPC_otdr 90 +#define OPC_otdrb 91 +#define OPC_otir 92 +#define OPC_otirb 93 +#define OPC_out 94 +#define OPC_outb 95 +#define OPC_outd 96 +#define OPC_outdb 97 +#define OPC_outi 98 +#define OPC_outib 99 +#define OPC_pop 100 +#define OPC_popl 101 +#define OPC_push 102 +#define OPC_pushl 103 +#define OPC_res 104 +#define OPC_resb 105 +#define OPC_resflg 106 +#define OPC_ret 107 +#define OPC_rl 108 +#define OPC_rlb 109 +#define OPC_rlc 110 +#define OPC_rlcb 111 +#define OPC_rldb 112 +#define OPC_rr 113 +#define OPC_rrb 114 +#define OPC_rrc 115 +#define OPC_rrcb 116 +#define OPC_rrdb 117 +#define OPC_sbc 118 +#define OPC_sbcb 119 +#define OPC_sda 120 +#define OPC_sdab 121 +#define OPC_sdal 122 +#define OPC_sdl 123 +#define OPC_sdlb 124 +#define OPC_sdll 125 +#define OPC_set 126 +#define OPC_setb 127 +#define OPC_setflg 128 +#define OPC_sin 129 +#define OPC_sinb 130 +#define OPC_sind 131 +#define OPC_sindb 132 +#define OPC_sindr 133 +#define OPC_sindrb 134 +#define OPC_sini 135 +#define OPC_sinib 136 +#define OPC_sinir 137 +#define OPC_sinirb 138 +#define OPC_sla 139 +#define OPC_slab 140 +#define OPC_slal 141 +#define OPC_sll 142 +#define OPC_sllb 143 +#define OPC_slll 144 +#define OPC_sotdr 145 +#define OPC_sotdrb 146 +#define OPC_sotir 147 +#define OPC_sotirb 148 +#define OPC_sout 149 +#define OPC_soutb 150 +#define OPC_soutd 151 +#define OPC_soutdb 152 +#define OPC_souti 153 +#define OPC_soutib 154 +#define OPC_sra 155 +#define OPC_srab 156 +#define OPC_sral 157 +#define OPC_srl 158 +#define OPC_srlb 159 +#define OPC_srll 160 +#define OPC_sub 161 +#define OPC_subb 162 +#define OPC_subl 163 +#define OPC_tcc 164 +#define OPC_tccb 165 +#define OPC_test 166 +#define OPC_testb 167 +#define OPC_testl 168 +#define OPC_trdb 169 +#define OPC_trdrb 170 +#define OPC_trib 171 +#define OPC_trirb 172 +#define OPC_trtdrb 173 +#define OPC_trtib 174 +#define OPC_trtirb 175 +#define OPC_trtrb 176 +#define OPC_tset 177 +#define OPC_tsetb 178 +#define OPC_xor 179 +#define OPC_xorb 180 +#define OPC_ldd 181 +#define OPC_lddb 182 +#define OPC_lddr 183 +#define OPC_lddrb 184 +#define OPC_ldi 185 +#define OPC_ldib 186 +#define OPC_sc 187 +#define OPC_bpt 188 +#define OPC_ext0e 188 +#define OPC_ext0f 188 +#define OPC_ext8e 188 +#define OPC_ext8f 188 +#define OPC_rsvd36 188 +#define OPC_rsvd38 188 +#define OPC_rsvd78 188 +#define OPC_rsvd7e 188 +#define OPC_rsvd9d 188 +#define OPC_rsvd9f 188 +#define OPC_rsvdb9 188 +#define OPC_rsvdbf 188 +#define OPC_ldctlb 189 +#define OPC_trtdb 190 +#define OPC_brk 191 typedef struct { #ifdef NICENAMES @@ -568,13 +585,21 @@ const opcode_entry_type z8k_table[] = { "bpt",OPC_bpt,0,{0}, {CLASS_BIT+3,CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,9}, +/* 0000 1111 0000 1100 *** brk */ +{ +#ifdef NICENAMES +"brk",8,10,0x00, +#endif +"brk",OPC_brk,0,{0}, + {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0xc,0,0,0,0,0,},0,2,10}, + /* 0001 1111 ddN0 0000 *** call @rd */ { #ifdef NICENAMES "call @rd",32,10,0x00, #endif "call",OPC_call,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,10}, + {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,11}, /* 0101 1111 0000 0000 address_dst *** call address_dst */ { @@ -582,7 +607,7 @@ const opcode_entry_type z8k_table[] = { "call address_dst",32,12,0x00, #endif "call",OPC_call,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,10}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,11}, /* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */ { @@ -590,7 +615,7 @@ const opcode_entry_type z8k_table[] = { "call address_dst(rd)",32,13,0x00, #endif "call",OPC_call,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,10}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,11}, /* 1101 disp12 *** calr disp12 */ { @@ -598,7 +623,7 @@ const opcode_entry_type z8k_table[] = { "calr disp12",16,10,0x00, #endif "calr",OPC_calr,0,{CLASS_DISP,}, - {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,11}, + {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,12}, /* 0000 1101 ddN0 1000 *** clr @rd */ { @@ -606,7 +631,7 @@ const opcode_entry_type z8k_table[] = { "clr @rd",16,8,0x00, #endif "clr",OPC_clr,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,12}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, /* 0100 1101 0000 1000 address_dst *** clr address_dst */ { @@ -614,7 +639,7 @@ const opcode_entry_type z8k_table[] = { "clr address_dst",16,11,0x00, #endif "clr",OPC_clr,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,12}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, /* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */ { @@ -622,7 +647,7 @@ const opcode_entry_type z8k_table[] = { "clr address_dst(rd)",16,12,0x00, #endif "clr",OPC_clr,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,12}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, /* 1000 1101 dddd 1000 *** clr rd */ { @@ -630,7 +655,7 @@ const opcode_entry_type z8k_table[] = { "clr rd",16,7,0x00, #endif "clr",OPC_clr,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,12}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, /* 0000 1100 ddN0 1000 *** clrb @rd */ { @@ -638,7 +663,7 @@ const opcode_entry_type z8k_table[] = { "clrb @rd",8,8,0x00, #endif "clrb",OPC_clrb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,14}, /* 0100 1100 0000 1000 address_dst *** clrb address_dst */ { @@ -646,7 +671,7 @@ const opcode_entry_type z8k_table[] = { "clrb address_dst",8,11,0x00, #endif "clrb",OPC_clrb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, /* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */ { @@ -654,7 +679,7 @@ const opcode_entry_type z8k_table[] = { "clrb address_dst(rd)",8,12,0x00, #endif "clrb",OPC_clrb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, /* 1000 1100 dddd 1000 *** clrb rbd */ { @@ -662,7 +687,7 @@ const opcode_entry_type z8k_table[] = { "clrb rbd",8,7,0x00, #endif "clrb",OPC_clrb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,14}, /* 0000 1101 ddN0 0000 *** com @rd */ { @@ -670,7 +695,7 @@ const opcode_entry_type z8k_table[] = { "com @rd",16,12,0x18, #endif "com",OPC_com,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,14}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, /* 0100 1101 0000 0000 address_dst *** com address_dst */ { @@ -678,7 +703,7 @@ const opcode_entry_type z8k_table[] = { "com address_dst",16,15,0x18, #endif "com",OPC_com,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, /* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */ { @@ -686,7 +711,7 @@ const opcode_entry_type z8k_table[] = { "com address_dst(rd)",16,16,0x18, #endif "com",OPC_com,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, /* 1000 1101 dddd 0000 *** com rd */ { @@ -694,7 +719,7 @@ const opcode_entry_type z8k_table[] = { "com rd",16,7,0x18, #endif "com",OPC_com,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,14}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, /* 0000 1100 ddN0 0000 *** comb @rd */ { @@ -702,7 +727,7 @@ const opcode_entry_type z8k_table[] = { "comb @rd",8,12,0x1c, #endif "comb",OPC_comb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,16}, /* 0100 1100 0000 0000 address_dst *** comb address_dst */ { @@ -710,7 +735,7 @@ const opcode_entry_type z8k_table[] = { "comb address_dst",8,15,0x1c, #endif "comb",OPC_comb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,16}, /* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */ { @@ -718,7 +743,7 @@ const opcode_entry_type z8k_table[] = { "comb address_dst(rd)",8,16,0x1c, #endif "comb",OPC_comb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,16}, /* 1000 1100 dddd 0000 *** comb rbd */ { @@ -726,7 +751,7 @@ const opcode_entry_type z8k_table[] = { "comb rbd",8,7,0x1c, #endif "comb",OPC_comb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,16}, /* 1000 1101 flags 0101 *** comflg flags */ { @@ -734,7 +759,7 @@ const opcode_entry_type z8k_table[] = { "comflg flags",16,7,0x3c, #endif "comflg",OPC_comflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,16}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,17}, /* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */ { @@ -742,7 +767,7 @@ const opcode_entry_type z8k_table[] = { "cp @rd,imm16",16,11,0x3c, #endif "cp",OPC_cp,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,17}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,18}, /* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */ { @@ -750,7 +775,7 @@ const opcode_entry_type z8k_table[] = { "cp address_dst(rd),imm16",16,15,0x3c, #endif "cp",OPC_cp,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,17}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,18}, /* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */ { @@ -758,7 +783,7 @@ const opcode_entry_type z8k_table[] = { "cp address_dst,imm16",16,14,0x3c, #endif "cp",OPC_cp,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,17}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,18}, /* 0000 1011 ssN0 dddd *** cp rd,@rs */ { @@ -766,7 +791,7 @@ const opcode_entry_type z8k_table[] = { "cp rd,@rs",16,7,0x3c, #endif "cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, /* 0100 1011 0000 dddd address_src *** cp rd,address_src */ { @@ -774,7 +799,7 @@ const opcode_entry_type z8k_table[] = { "cp rd,address_src",16,9,0x3c, #endif "cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,17}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, /* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */ { @@ -782,7 +807,7 @@ const opcode_entry_type z8k_table[] = { "cp rd,address_src(rs)",16,10,0x3c, #endif "cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,17}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, /* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */ { @@ -790,7 +815,7 @@ const opcode_entry_type z8k_table[] = { "cp rd,imm16",16,7,0x3c, #endif "cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,17}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,18}, /* 1000 1011 ssss dddd *** cp rd,rs */ { @@ -798,7 +823,7 @@ const opcode_entry_type z8k_table[] = { "cp rd,rs",16,4,0x3c, #endif "cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, + {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, /* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */ { @@ -806,7 +831,7 @@ const opcode_entry_type z8k_table[] = { "cpb @rd,imm8",8,11,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,18}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,19}, /* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */ { @@ -814,7 +839,7 @@ const opcode_entry_type z8k_table[] = { "cpb address_dst(rd),imm8",8,15,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,18}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,19}, /* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */ { @@ -822,7 +847,7 @@ const opcode_entry_type z8k_table[] = { "cpb address_dst,imm8",8,14,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,18}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,19}, /* 0000 1010 ssN0 dddd *** cpb rbd,@rs */ { @@ -830,7 +855,7 @@ const opcode_entry_type z8k_table[] = { "cpb rbd,@rs",8,7,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,19}, /* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */ { @@ -838,7 +863,7 @@ const opcode_entry_type z8k_table[] = { "cpb rbd,address_src",8,9,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, /* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */ { @@ -846,7 +871,7 @@ const opcode_entry_type z8k_table[] = { "cpb rbd,address_src(rs)",8,10,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, /* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */ { @@ -854,7 +879,7 @@ const opcode_entry_type z8k_table[] = { "cpb rbd,imm8",8,7,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,18}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,19}, /* 1000 1010 ssss dddd *** cpb rbd,rbs */ { @@ -862,7 +887,7 @@ const opcode_entry_type z8k_table[] = { "cpb rbd,rbs",8,4,0x3c, #endif "cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, + {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,19}, /* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */ { @@ -870,7 +895,7 @@ const opcode_entry_type z8k_table[] = { "cpd rd,@rs,rr,cc",16,11,0x3c, #endif "cpd",OPC_cpd,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,19}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,20}, /* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */ { @@ -878,7 +903,7 @@ const opcode_entry_type z8k_table[] = { "cpdb rbd,@rs,rr,cc",8,11,0x3c, #endif "cpdb",OPC_cpdb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,20}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,21}, /* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */ { @@ -886,7 +911,7 @@ const opcode_entry_type z8k_table[] = { "cpdr rd,@rs,rr,cc",16,11,0x3c, #endif "cpdr",OPC_cpdr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,21}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,22}, /* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */ { @@ -894,7 +919,7 @@ const opcode_entry_type z8k_table[] = { "cpdrb rbd,@rs,rr,cc",8,11,0x3c, #endif "cpdrb",OPC_cpdrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,22}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,23}, /* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */ { @@ -902,7 +927,7 @@ const opcode_entry_type z8k_table[] = { "cpi rd,@rs,rr,cc",16,11,0x3c, #endif "cpi",OPC_cpi,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,23}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,24}, /* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */ { @@ -910,7 +935,7 @@ const opcode_entry_type z8k_table[] = { "cpib rbd,@rs,rr,cc",8,11,0x3c, #endif "cpib",OPC_cpib,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,24}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,25}, /* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */ { @@ -918,7 +943,7 @@ const opcode_entry_type z8k_table[] = { "cpir rd,@rs,rr,cc",16,11,0x3c, #endif "cpir",OPC_cpir,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,25}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,26}, /* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */ { @@ -926,7 +951,7 @@ const opcode_entry_type z8k_table[] = { "cpirb rbd,@rs,rr,cc",8,11,0x3c, #endif "cpirb",OPC_cpirb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,26}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,27}, /* 0001 0000 ssN0 dddd *** cpl rrd,@rs */ { @@ -934,7 +959,7 @@ const opcode_entry_type z8k_table[] = { "cpl rrd,@rs",32,14,0x3c, #endif "cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,27}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,28}, /* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */ { @@ -942,7 +967,7 @@ const opcode_entry_type z8k_table[] = { "cpl rrd,address_src",32,15,0x3c, #endif "cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,27}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,28}, /* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */ { @@ -950,7 +975,7 @@ const opcode_entry_type z8k_table[] = { "cpl rrd,address_src(rs)",32,16,0x3c, #endif "cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,27}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,28}, /* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */ { @@ -958,7 +983,7 @@ const opcode_entry_type z8k_table[] = { "cpl rrd,imm32",32,14,0x3c, #endif "cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,27}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,28}, /* 1001 0000 ssss dddd *** cpl rrd,rrs */ { @@ -966,7 +991,7 @@ const opcode_entry_type z8k_table[] = { "cpl rrd,rrs",32,8,0x3c, #endif "cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,27}, + {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,28}, /* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */ { @@ -974,7 +999,7 @@ const opcode_entry_type z8k_table[] = { "cpsd @rd,@rs,rr,cc",16,11,0x3c, #endif "cpsd",OPC_cpsd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,28}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,29}, /* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */ { @@ -982,7 +1007,7 @@ const opcode_entry_type z8k_table[] = { "cpsdb @rd,@rs,rr,cc",8,11,0x3c, #endif "cpsdb",OPC_cpsdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,29}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,30}, /* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */ { @@ -990,7 +1015,7 @@ const opcode_entry_type z8k_table[] = { "cpsdr @rd,@rs,rr,cc",16,11,0x3c, #endif "cpsdr",OPC_cpsdr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,30}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,31}, /* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */ { @@ -998,7 +1023,7 @@ const opcode_entry_type z8k_table[] = { "cpsdrb @rd,@rs,rr,cc",8,11,0x3c, #endif "cpsdrb",OPC_cpsdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,31}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,32}, /* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */ { @@ -1006,7 +1031,7 @@ const opcode_entry_type z8k_table[] = { "cpsi @rd,@rs,rr,cc",16,11,0x3c, #endif "cpsi",OPC_cpsi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,32}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,33}, /* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */ { @@ -1014,7 +1039,7 @@ const opcode_entry_type z8k_table[] = { "cpsib @rd,@rs,rr,cc",8,11,0x3c, #endif "cpsib",OPC_cpsib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,33}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,34}, /* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */ { @@ -1022,7 +1047,7 @@ const opcode_entry_type z8k_table[] = { "cpsir @rd,@rs,rr,cc",16,11,0x3c, #endif "cpsir",OPC_cpsir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,34}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,35}, /* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */ { @@ -1030,7 +1055,7 @@ const opcode_entry_type z8k_table[] = { "cpsirb @rd,@rs,rr,cc",8,11,0x3c, #endif "cpsirb",OPC_cpsirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,35}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,36}, /* 1011 0000 dddd 0000 *** dab rbd */ { @@ -1038,7 +1063,7 @@ const opcode_entry_type z8k_table[] = { "dab rbd",8,5,0x38, #endif "dab",OPC_dab,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,36}, + {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,37}, /* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */ { @@ -1046,7 +1071,7 @@ const opcode_entry_type z8k_table[] = { "dbjnz rbd,disp7",16,11,0x00, #endif "dbjnz",OPC_dbjnz,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,37}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,38}, /* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */ { @@ -1054,7 +1079,7 @@ const opcode_entry_type z8k_table[] = { "dec @rd,imm4m1",16,11,0x1c, #endif "dec",OPC_dec,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,38}, + {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, /* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */ { @@ -1062,7 +1087,7 @@ const opcode_entry_type z8k_table[] = { "dec address_dst(rd),imm4m1",16,14,0x1c, #endif "dec",OPC_dec,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,38}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, /* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */ { @@ -1070,7 +1095,7 @@ const opcode_entry_type z8k_table[] = { "dec address_dst,imm4m1",16,13,0x1c, #endif "dec",OPC_dec,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,38}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, /* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */ { @@ -1078,7 +1103,7 @@ const opcode_entry_type z8k_table[] = { "dec rd,imm4m1",16,4,0x1c, #endif "dec",OPC_dec,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,38}, + {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, /* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */ { @@ -1086,7 +1111,7 @@ const opcode_entry_type z8k_table[] = { "decb @rd,imm4m1",8,11,0x1c, #endif "decb",OPC_decb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, + {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,40}, /* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */ { @@ -1094,7 +1119,7 @@ const opcode_entry_type z8k_table[] = { "decb address_dst(rd),imm4m1",8,14,0x1c, #endif "decb",OPC_decb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,40}, /* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */ { @@ -1102,7 +1127,7 @@ const opcode_entry_type z8k_table[] = { "decb address_dst,imm4m1",8,13,0x1c, #endif "decb",OPC_decb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,40}, /* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */ { @@ -1110,7 +1135,7 @@ const opcode_entry_type z8k_table[] = { "decb rbd,imm4m1",8,4,0x1c, #endif "decb",OPC_decb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, + {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,40}, /* 0111 1100 0000 00ii *** di i2 */ { @@ -1118,7 +1143,7 @@ const opcode_entry_type z8k_table[] = { "di i2",16,7,0x00, #endif "di",OPC_di,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,40}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,41}, /* 0001 1011 ssN0 dddd *** div rrd,@rs */ { @@ -1126,7 +1151,7 @@ const opcode_entry_type z8k_table[] = { "div rrd,@rs",16,107,0x3c, #endif "div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,41}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, /* 0101 1011 0000 dddd address_src *** div rrd,address_src */ { @@ -1134,7 +1159,7 @@ const opcode_entry_type z8k_table[] = { "div rrd,address_src",16,107,0x3c, #endif "div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,41}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, /* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */ { @@ -1142,7 +1167,7 @@ const opcode_entry_type z8k_table[] = { "div rrd,address_src(rs)",16,107,0x3c, #endif "div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,41}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, /* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */ { @@ -1150,7 +1175,7 @@ const opcode_entry_type z8k_table[] = { "div rrd,imm16",16,107,0x3c, #endif "div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,41}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,42}, /* 1001 1011 ssss dddd *** div rrd,rs */ { @@ -1158,7 +1183,7 @@ const opcode_entry_type z8k_table[] = { "div rrd,rs",16,107,0x3c, #endif "div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,41}, + {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, /* 0001 1010 ssN0 dddd *** divl rqd,@rs */ { @@ -1166,7 +1191,7 @@ const opcode_entry_type z8k_table[] = { "divl rqd,@rs",32,744,0x3c, #endif "divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,43}, /* 0101 1010 0000 dddd address_src *** divl rqd,address_src */ { @@ -1174,7 +1199,7 @@ const opcode_entry_type z8k_table[] = { "divl rqd,address_src",32,745,0x3c, #endif "divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,43}, /* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */ { @@ -1182,7 +1207,7 @@ const opcode_entry_type z8k_table[] = { "divl rqd,address_src(rs)",32,746,0x3c, #endif "divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,43}, /* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */ { @@ -1190,7 +1215,7 @@ const opcode_entry_type z8k_table[] = { "divl rqd,imm32",32,744,0x3c, #endif "divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,42}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,43}, /* 1001 1010 ssss dddd *** divl rqd,rrs */ { @@ -1198,7 +1223,7 @@ const opcode_entry_type z8k_table[] = { "divl rqd,rrs",32,744,0x3c, #endif "divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, + {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,43}, /* 1111 dddd 1disp7 *** djnz rd,disp7 */ { @@ -1206,7 +1231,7 @@ const opcode_entry_type z8k_table[] = { "djnz rd,disp7",16,11,0x00, #endif "djnz",OPC_djnz,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,43}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,44}, /* 0111 1100 0000 01ii *** ei i2 */ { @@ -1214,7 +1239,7 @@ const opcode_entry_type z8k_table[] = { "ei i2",16,7,0x00, #endif "ei",OPC_ei,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,44}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,45}, /* 0010 1101 ssN0 dddd *** ex rd,@rs */ { @@ -1222,7 +1247,7 @@ const opcode_entry_type z8k_table[] = { "ex rd,@rs",16,12,0x00, #endif "ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,45}, + {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, /* 0110 1101 0000 dddd address_src *** ex rd,address_src */ { @@ -1230,7 +1255,7 @@ const opcode_entry_type z8k_table[] = { "ex rd,address_src",16,15,0x00, #endif "ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,45}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, /* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */ { @@ -1238,7 +1263,7 @@ const opcode_entry_type z8k_table[] = { "ex rd,address_src(rs)",16,16,0x00, #endif "ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,45}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, /* 1010 1101 ssss dddd *** ex rd,rs */ { @@ -1246,7 +1271,7 @@ const opcode_entry_type z8k_table[] = { "ex rd,rs",16,6,0x00, #endif "ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,45}, + {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, /* 0010 1100 ssN0 dddd *** exb rbd,@rs */ { @@ -1254,7 +1279,7 @@ const opcode_entry_type z8k_table[] = { "exb rbd,@rs",8,12,0x00, #endif "exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, + {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,47}, /* 0110 1100 0000 dddd address_src *** exb rbd,address_src */ { @@ -1262,7 +1287,7 @@ const opcode_entry_type z8k_table[] = { "exb rbd,address_src",8,15,0x00, #endif "exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,47}, /* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */ { @@ -1270,7 +1295,7 @@ const opcode_entry_type z8k_table[] = { "exb rbd,address_src(rs)",8,16,0x00, #endif "exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,47}, /* 1010 1100 ssss dddd *** exb rbd,rbs */ { @@ -1278,7 +1303,7 @@ const opcode_entry_type z8k_table[] = { "exb rbd,rbs",8,6,0x00, #endif "exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, + {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,47}, /* 0000 1110 imm8 *** ext0e imm8 */ { @@ -1286,7 +1311,7 @@ const opcode_entry_type z8k_table[] = { "ext0e imm8",8,10,0x00, #endif "ext0e",OPC_ext0e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,47}, + {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,48}, /* 0000 1111 imm8 *** ext0f imm8 */ { @@ -1294,7 +1319,7 @@ const opcode_entry_type z8k_table[] = { "ext0f imm8",8,10,0x00, #endif "ext0f",OPC_ext0f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,48}, + {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,49}, /* 1000 1110 imm8 *** ext8e imm8 */ { @@ -1302,7 +1327,7 @@ const opcode_entry_type z8k_table[] = { "ext8e imm8",8,10,0x00, #endif "ext8e",OPC_ext8e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,49}, + {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,50}, /* 1000 1111 imm8 *** ext8f imm8 */ { @@ -1310,7 +1335,7 @@ const opcode_entry_type z8k_table[] = { "ext8f imm8",8,10,0x00, #endif "ext8f",OPC_ext8f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,50}, + {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,51}, /* 1011 0001 dddd 1010 *** exts rrd */ { @@ -1318,7 +1343,7 @@ const opcode_entry_type z8k_table[] = { "exts rrd",16,11,0x00, #endif "exts",OPC_exts,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,51}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,52}, /* 1011 0001 dddd 0000 *** extsb rd */ { @@ -1326,7 +1351,7 @@ const opcode_entry_type z8k_table[] = { "extsb rd",8,11,0x00, #endif "extsb",OPC_extsb,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,52}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, /* 1011 0001 dddd 0111 *** extsl rqd */ { @@ -1334,7 +1359,7 @@ const opcode_entry_type z8k_table[] = { "extsl rqd",32,11,0x00, #endif "extsl",OPC_extsl,0,{CLASS_REG_QUAD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,53}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,54}, /* 0111 1010 0000 0000 *** halt */ { @@ -1342,15 +1367,15 @@ const opcode_entry_type z8k_table[] = { "halt",16,8,0x00, #endif "halt",OPC_halt,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,54}, + {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,55}, -/* 0011 1101 ssN0 dddd *** in rd,@rs */ +/* 0011 1101 ssss dddd *** in rd,@ri */ { #ifdef NICENAMES -"in rd,@rs",16,10,0x00, +"in rd,@ri",16,10,0x00, #endif -"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,55}, +"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IRO+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,56}, /* 0011 1011 dddd 0100 imm16 *** in rd,imm16 */ { @@ -1358,15 +1383,15 @@ const opcode_entry_type z8k_table[] = { "in rd,imm16",16,12,0x00, #endif "in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,55}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,56}, -/* 0011 1100 ssN0 dddd *** inb rbd,@rs */ +/* 0011 1100 ssss dddd *** inb rbd,@ri */ { #ifdef NICENAMES -"inb rbd,@rs",8,12,0x00, +"inb rbd,@ri",8,12,0x00, #endif -"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,56}, +"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IRO+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,57}, /* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */ { @@ -1374,7 +1399,7 @@ const opcode_entry_type z8k_table[] = { "inb rbd,imm16",8,10,0x00, #endif "inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,56}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,57}, /* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */ { @@ -1382,7 +1407,7 @@ const opcode_entry_type z8k_table[] = { "inc @rd,imm4m1",16,11,0x1c, #endif "inc",OPC_inc,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,57}, + {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, /* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */ { @@ -1390,7 +1415,7 @@ const opcode_entry_type z8k_table[] = { "inc address_dst(rd),imm4m1",16,14,0x1c, #endif "inc",OPC_inc,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,57}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, /* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */ { @@ -1398,7 +1423,7 @@ const opcode_entry_type z8k_table[] = { "inc address_dst,imm4m1",16,13,0x1c, #endif "inc",OPC_inc,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,57}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, /* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */ { @@ -1406,7 +1431,7 @@ const opcode_entry_type z8k_table[] = { "inc rd,imm4m1",16,4,0x1c, #endif "inc",OPC_inc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,57}, + {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, /* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */ { @@ -1414,7 +1439,7 @@ const opcode_entry_type z8k_table[] = { "incb @rd,imm4m1",8,11,0x1c, #endif "incb",OPC_incb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, + {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,59}, /* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */ { @@ -1422,7 +1447,7 @@ const opcode_entry_type z8k_table[] = { "incb address_dst(rd),imm4m1",8,14,0x1c, #endif "incb",OPC_incb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,59}, /* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */ { @@ -1430,7 +1455,7 @@ const opcode_entry_type z8k_table[] = { "incb address_dst,imm4m1",8,13,0x1c, #endif "incb",OPC_incb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,59}, /* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */ { @@ -1438,39 +1463,71 @@ const opcode_entry_type z8k_table[] = { "incb rbd,imm4m1",8,4,0x1c, #endif "incb",OPC_incb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, + {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,59}, + +/* 0011 1011 ssss 1000 0000 aaaa ddN0 1000 *** ind @rd,@ri,ra */ +{ +#ifdef NICENAMES +"ind @rd,@ri,ra",16,21,0x04, +#endif +"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,60}, + +/* 0011 1010 ssss 1000 0000 aaaa ddN0 1000 *** indb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indb @rd,@ri,ra",8,21,0x04, +#endif +"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,61}, + +/* 0011 1011 ssss 1000 0000 aaaa ddN0 0000 *** indr @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indr @rd,@ri,ra",16,11,0x04, +#endif +"indr",OPC_indr,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,62}, + +/* 0011 1010 ssss 1000 0000 aaaa ddN0 0000 *** indrb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indrb @rd,@ri,ra",8,11,0x04, +#endif +"indrb",OPC_indrb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,63}, -/* 0011 1011 ssN0 1000 0000 aaaa ddN0 1000 *** ind @rd,@rs,ra */ +/* 0011 1011 ssss 0000 0000 aaaa ddN0 1000 *** ini @rd,@ri,ra */ { #ifdef NICENAMES -"ind @rd,@rs,ra",16,21,0x04, +"ini @rd,@ri,ra",16,21,0x04, #endif -"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,59}, +"ini",OPC_ini,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,64}, -/* 0011 1010 ssN0 1000 0000 aaaa ddN0 1000 *** indb @rd,@rs,rba */ +/* 0011 1010 ssss 0000 0000 aaaa ddN0 1000 *** inib @rd,@ri,ra */ { #ifdef NICENAMES -"indb @rd,@rs,rba",8,21,0x04, +"inib @rd,@ri,ra",8,21,0x04, #endif -"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,60}, +"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,65}, -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 1000 *** inib @rd,@rs,ra */ +/* 0011 1011 ssss 0000 0000 aaaa ddN0 0000 *** inir @rd,@ri,ra */ { #ifdef NICENAMES -"inib @rd,@rs,ra",8,21,0x04, +"inir @rd,@ri,ra",16,11,0x04, #endif -"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,61}, +"inir",OPC_inir,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,66}, -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 0000 *** inibr @rd,@rs,ra */ +/* 0011 1010 ssss 0000 0000 aaaa ddN0 0000 *** inirb @rd,@ri,ra */ { #ifdef NICENAMES -"inibr @rd,@rs,ra",16,21,0x04, +"inirb @rd,@ri,ra",8,11,0x04, #endif -"inibr",OPC_inibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,62}, +"inirb",OPC_inirb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,67}, /* 0111 1011 0000 0000 *** iret */ { @@ -1478,7 +1535,7 @@ const opcode_entry_type z8k_table[] = { "iret",16,13,0x3f, #endif "iret",OPC_iret,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,63}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,68}, /* 0001 1110 ddN0 cccc *** jp cc,@rd */ { @@ -1486,7 +1543,7 @@ const opcode_entry_type z8k_table[] = { "jp cc,@rd",16,10,0x00, #endif "jp",OPC_jp,0,{CLASS_CC,CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,64}, + {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,69}, /* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */ { @@ -1494,7 +1551,7 @@ const opcode_entry_type z8k_table[] = { "jp cc,address_dst",16,7,0x00, #endif "jp",OPC_jp,0,{CLASS_CC,CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,64}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, /* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */ { @@ -1502,7 +1559,7 @@ const opcode_entry_type z8k_table[] = { "jp cc,address_dst(rd)",16,8,0x00, #endif "jp",OPC_jp,0,{CLASS_CC,CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,64}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, /* 1110 cccc disp8 *** jr cc,disp8 */ { @@ -1510,7 +1567,7 @@ const opcode_entry_type z8k_table[] = { "jr cc,disp8",16,6,0x00, #endif "jr",OPC_jr,0,{CLASS_CC,CLASS_DISP,}, - {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,65}, + {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,70}, /* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */ { @@ -1518,7 +1575,7 @@ const opcode_entry_type z8k_table[] = { "ld @rd,imm16",16,7,0x00, #endif "ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,66}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, /* 0010 1111 ddN0 ssss *** ld @rd,rs */ { @@ -1526,7 +1583,7 @@ const opcode_entry_type z8k_table[] = { "ld @rd,rs",16,8,0x00, #endif "ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,66}, + {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,71}, /* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */ { @@ -1534,7 +1591,7 @@ const opcode_entry_type z8k_table[] = { "ld address_dst(rd),imm16",16,15,0x00, #endif "ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,66}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,71}, /* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */ { @@ -1542,7 +1599,7 @@ const opcode_entry_type z8k_table[] = { "ld address_dst(rd),rs",16,12,0x00, #endif "ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,66}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,71}, /* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */ { @@ -1550,7 +1607,7 @@ const opcode_entry_type z8k_table[] = { "ld address_dst,imm16",16,14,0x00, #endif "ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,66}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,71}, /* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */ { @@ -1558,7 +1615,7 @@ const opcode_entry_type z8k_table[] = { "ld address_dst,rs",16,11,0x00, #endif "ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,66}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,71}, /* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */ { @@ -1566,7 +1623,7 @@ const opcode_entry_type z8k_table[] = { "ld rd(imm16),rs",16,14,0x00, #endif "ld",OPC_ld,0,{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,66}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, /* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */ { @@ -1574,7 +1631,7 @@ const opcode_entry_type z8k_table[] = { "ld rd(rx),rs",16,14,0x00, #endif "ld",OPC_ld,0,{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,66}, + {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,71}, /* 0010 0001 ssN0 dddd *** ld rd,@rs */ { @@ -1582,7 +1639,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,@rs",16,7,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,66}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,71}, /* 0110 0001 0000 dddd address_src *** ld rd,address_src */ { @@ -1590,7 +1647,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,address_src",16,9,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,66}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, /* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */ { @@ -1598,7 +1655,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,address_src(rs)",16,10,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,66}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, /* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */ { @@ -1606,7 +1663,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,imm16",16,7,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,66}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, /* 1010 0001 ssss dddd *** ld rd,rs */ { @@ -1614,7 +1671,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,rs",16,3,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,66}, + {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,71}, /* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */ { @@ -1622,7 +1679,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,rs(imm16)",16,14,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,66}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, /* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */ { @@ -1630,7 +1687,7 @@ const opcode_entry_type z8k_table[] = { "ld rd,rs(rx)",16,14,0x00, #endif "ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,66}, + {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,71}, /* 0111 0110 0000 dddd address_src *** lda prd,address_src */ { @@ -1638,7 +1695,7 @@ const opcode_entry_type z8k_table[] = { "lda prd,address_src",16,12,0x00, #endif "lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,67}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, /* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */ { @@ -1646,7 +1703,7 @@ const opcode_entry_type z8k_table[] = { "lda prd,address_src(rs)",16,13,0x00, #endif "lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,67}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, /* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */ { @@ -1654,7 +1711,7 @@ const opcode_entry_type z8k_table[] = { "lda prd,rs(imm16)",16,15,0x00, #endif "lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,67}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,72}, /* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */ { @@ -1662,7 +1719,7 @@ const opcode_entry_type z8k_table[] = { "lda prd,rs(rx)",16,15,0x00, #endif "lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,67}, + {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,72}, /* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */ { @@ -1670,7 +1727,7 @@ const opcode_entry_type z8k_table[] = { "ldar prd,disp16",16,15,0x00, #endif "ldar",OPC_ldar,0,{CLASS_PR+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,68}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,73}, /* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */ { @@ -1678,7 +1735,7 @@ const opcode_entry_type z8k_table[] = { "ldb @rd,imm8",8,7,0x00, #endif "ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,69}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74}, /* 0010 1110 ddN0 ssss *** ldb @rd,rbs */ { @@ -1686,7 +1743,7 @@ const opcode_entry_type z8k_table[] = { "ldb @rd,rbs",8,8,0x00, #endif "ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,69}, + {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,74}, /* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */ { @@ -1694,7 +1751,7 @@ const opcode_entry_type z8k_table[] = { "ldb address_dst(rd),imm8",8,15,0x00, #endif "ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,69}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,74}, /* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */ { @@ -1702,7 +1759,7 @@ const opcode_entry_type z8k_table[] = { "ldb address_dst(rd),rbs",8,12,0x00, #endif "ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,74}, /* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */ { @@ -1710,7 +1767,7 @@ const opcode_entry_type z8k_table[] = { "ldb address_dst,imm8",8,14,0x00, #endif "ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,69}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,74}, /* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */ { @@ -1718,7 +1775,7 @@ const opcode_entry_type z8k_table[] = { "ldb address_dst,rbs",8,11,0x00, #endif "ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,74}, /* 0010 0000 ssN0 dddd *** ldb rbd,@rs */ { @@ -1726,7 +1783,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,@rs",8,7,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,69}, + {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, /* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */ { @@ -1734,7 +1791,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,address_src",8,9,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,69}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,74}, /* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */ { @@ -1742,7 +1799,15 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,address_src(rs)",8,10,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,69}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,74}, + +/* 0010 0000 0000 dddd imm8 imm8 *** ldb rbd,imm8 */ +{ +#ifdef NICENAMES +"ldb rbd,imm8",8,7,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74}, /* 1100 dddd imm8 *** ldb rbd,imm8 */ { @@ -1750,7 +1815,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,imm8",8,5,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,69}, + {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,74}, /* 1010 0000 ssss dddd *** ldb rbd,rbs */ { @@ -1758,7 +1823,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,rbs",8,3,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,69}, + {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, /* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */ { @@ -1766,7 +1831,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,rs(imm16)",8,14,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,69}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,74}, /* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */ { @@ -1774,7 +1839,7 @@ const opcode_entry_type z8k_table[] = { "ldb rbd,rs(rx)",8,14,0x00, #endif "ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,69}, + {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,74}, /* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */ { @@ -1782,7 +1847,7 @@ const opcode_entry_type z8k_table[] = { "ldb rd(imm16),rbs",8,14,0x00, #endif "ldb",OPC_ldb,0,{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,69}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,74}, /* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */ { @@ -1790,7 +1855,7 @@ const opcode_entry_type z8k_table[] = { "ldb rd(rx),rbs",8,14,0x00, #endif "ldb",OPC_ldb,0,{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,69}, + {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,74}, /* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */ { @@ -1798,7 +1863,7 @@ const opcode_entry_type z8k_table[] = { "ldctl ctrl,rs",32,7,0x00, #endif "ldctl",OPC_ldctl,0,{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,70}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,75}, /* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */ { @@ -1806,7 +1871,7 @@ const opcode_entry_type z8k_table[] = { "ldctl rd,ctrl",32,7,0x00, #endif "ldctl",OPC_ldctl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,70}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,75}, /* 1000 1100 ssss 1001 *** ldctlb ctrl,rbs */ { @@ -1814,7 +1879,7 @@ const opcode_entry_type z8k_table[] = { "ldctlb ctrl,rbs",32,7,0x3f, #endif "ldctlb",OPC_ldctlb,0,{CLASS_CTRL,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_BIT+9,0,0,0,0,0,},2,2,71}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_BIT+9,0,0,0,0,0,},2,2,76}, /* 1000 1100 dddd 0001 *** ldctlb rbd,ctrl */ { @@ -1822,7 +1887,7 @@ const opcode_entry_type z8k_table[] = { "ldctlb rbd,ctrl",32,7,0x00, #endif "ldctlb",OPC_ldctlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+1,0,0,0,0,0,},2,2,71}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+1,0,0,0,0,0,},2,2,76}, /* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */ { @@ -1830,7 +1895,7 @@ const opcode_entry_type z8k_table[] = { "ldd @rd,@rs,rr",16,11,0x04, #endif "ldd",OPC_ldd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,72}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,77}, /* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */ { @@ -1838,7 +1903,7 @@ const opcode_entry_type z8k_table[] = { "lddb @rd,@rs,rr",8,11,0x04, #endif "lddb",OPC_lddb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,73}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,78}, /* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */ { @@ -1846,7 +1911,7 @@ const opcode_entry_type z8k_table[] = { "lddr @rd,@rs,rr",16,11,0x04, #endif "lddr",OPC_lddr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,74}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,79}, /* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */ { @@ -1854,7 +1919,7 @@ const opcode_entry_type z8k_table[] = { "lddrb @rd,@rs,rr",8,11,0x04, #endif "lddrb",OPC_lddrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,75}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,80}, /* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */ { @@ -1862,7 +1927,7 @@ const opcode_entry_type z8k_table[] = { "ldi @rd,@rs,rr",16,11,0x04, #endif "ldi",OPC_ldi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,76}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,81}, /* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */ { @@ -1870,7 +1935,7 @@ const opcode_entry_type z8k_table[] = { "ldib @rd,@rs,rr",8,11,0x04, #endif "ldib",OPC_ldib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,77}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,82}, /* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */ { @@ -1878,7 +1943,7 @@ const opcode_entry_type z8k_table[] = { "ldir @rd,@rs,rr",16,11,0x04, #endif "ldir",OPC_ldir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,78}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,83}, /* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */ { @@ -1886,7 +1951,7 @@ const opcode_entry_type z8k_table[] = { "ldirb @rd,@rs,rr",8,11,0x04, #endif "ldirb",OPC_ldirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,79}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,84}, /* 1011 1101 dddd imm4 *** ldk rd,imm4 */ { @@ -1894,7 +1959,7 @@ const opcode_entry_type z8k_table[] = { "ldk rd,imm4",16,5,0x00, #endif "ldk",OPC_ldk,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,80}, + {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,85}, /* 0001 1101 ddN0 ssss *** ldl @rd,rrs */ { @@ -1902,7 +1967,7 @@ const opcode_entry_type z8k_table[] = { "ldl @rd,rrs",32,11,0x00, #endif "ldl",OPC_ldl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,81}, + {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,86}, /* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */ { @@ -1910,7 +1975,7 @@ const opcode_entry_type z8k_table[] = { "ldl address_dst(rd),rrs",32,14,0x00, #endif "ldl",OPC_ldl,0,{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,81}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,86}, /* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */ { @@ -1918,7 +1983,7 @@ const opcode_entry_type z8k_table[] = { "ldl address_dst,rrs",32,15,0x00, #endif "ldl",OPC_ldl,0,{CLASS_DA+(ARG_DST),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,81}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,86}, /* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */ { @@ -1926,7 +1991,7 @@ const opcode_entry_type z8k_table[] = { "ldl rd(imm16),rrs",32,17,0x00, #endif "ldl",OPC_ldl,0,{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,81}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,86}, /* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */ { @@ -1934,7 +1999,7 @@ const opcode_entry_type z8k_table[] = { "ldl rd(rx),rrs",32,17,0x00, #endif "ldl",OPC_ldl,0,{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,81}, + {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,86}, /* 0001 0100 ssN0 dddd *** ldl rrd,@rs */ { @@ -1942,7 +2007,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,@rs",32,11,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,81}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86}, /* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */ { @@ -1950,7 +2015,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,address_src",32,12,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,81}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,86}, /* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */ { @@ -1958,7 +2023,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,address_src(rs)",32,13,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,81}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,86}, /* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */ { @@ -1966,7 +2031,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,imm32",32,11,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,81}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,86}, /* 1001 0100 ssss dddd *** ldl rrd,rrs */ { @@ -1974,7 +2039,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,rrs",32,5,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,81}, + {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86}, /* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */ { @@ -1982,7 +2047,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,rs(imm16)",32,17,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,81}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,86}, /* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */ { @@ -1990,7 +2055,7 @@ const opcode_entry_type z8k_table[] = { "ldl rrd,rs(rx)",32,17,0x00, #endif "ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,81}, + {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,86}, /* 0001 1100 ddN0 1001 0000 ssss 0000 imm4m1 *** ldm @rd,rs,n */ { @@ -1998,7 +2063,7 @@ const opcode_entry_type z8k_table[] = { "ldm @rd,rs,n",16,11,0x00, #endif "ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,82}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,87}, /* 0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst(rd),rs,n */ { @@ -2006,7 +2071,7 @@ const opcode_entry_type z8k_table[] = { "ldm address_dst(rd),rs,n",16,15,0x00, #endif "ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,82}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,87}, /* 0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst,rs,n */ { @@ -2014,7 +2079,7 @@ const opcode_entry_type z8k_table[] = { "ldm address_dst,rs,n",16,14,0x00, #endif "ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,82}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,87}, /* 0001 1100 ssN0 0001 0000 dddd 0000 imm4m1 *** ldm rd,@rs,n */ { @@ -2022,7 +2087,7 @@ const opcode_entry_type z8k_table[] = { "ldm rd,@rs,n",16,11,0x00, #endif "ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,82}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,87}, /* 0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src(rs),n */ { @@ -2030,7 +2095,7 @@ const opcode_entry_type z8k_table[] = { "ldm rd,address_src(rs),n",16,15,0x00, #endif "ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,82}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,87}, /* 0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src,n */ { @@ -2038,7 +2103,7 @@ const opcode_entry_type z8k_table[] = { "ldm rd,address_src,n",16,14,0x00, #endif "ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMM4M1),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,82}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,87}, /* 0011 1001 ssN0 0000 *** ldps @rs */ { @@ -2046,7 +2111,7 @@ const opcode_entry_type z8k_table[] = { "ldps @rs",16,12,0x3f, #endif "ldps",OPC_ldps,0,{CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,83}, + {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,88}, /* 0111 1001 0000 0000 address_src *** ldps address_src */ { @@ -2054,7 +2119,7 @@ const opcode_entry_type z8k_table[] = { "ldps address_src",16,16,0x3f, #endif "ldps",OPC_ldps,0,{CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,83}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,88}, /* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */ { @@ -2062,7 +2127,7 @@ const opcode_entry_type z8k_table[] = { "ldps address_src(rs)",16,17,0x3f, #endif "ldps",OPC_ldps,0,{CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,83}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,88}, /* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */ { @@ -2070,7 +2135,7 @@ const opcode_entry_type z8k_table[] = { "ldr disp16,rs",16,14,0x00, #endif "ldr",OPC_ldr,0,{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,84}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,89}, /* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */ { @@ -2078,7 +2143,7 @@ const opcode_entry_type z8k_table[] = { "ldr rd,disp16",16,14,0x00, #endif "ldr",OPC_ldr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,84}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,89}, /* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */ { @@ -2086,7 +2151,7 @@ const opcode_entry_type z8k_table[] = { "ldrb disp16,rbs",8,14,0x00, #endif "ldrb",OPC_ldrb,0,{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,85}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,90}, /* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */ { @@ -2094,7 +2159,7 @@ const opcode_entry_type z8k_table[] = { "ldrb rbd,disp16",8,14,0x00, #endif "ldrb",OPC_ldrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,85}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,90}, /* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */ { @@ -2102,7 +2167,7 @@ const opcode_entry_type z8k_table[] = { "ldrl disp16,rrs",32,17,0x00, #endif "ldrl",OPC_ldrl,0,{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,86}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,91}, /* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */ { @@ -2110,7 +2175,7 @@ const opcode_entry_type z8k_table[] = { "ldrl rrd,disp16",32,17,0x00, #endif "ldrl",OPC_ldrl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,86}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,91}, /* 0111 1011 0000 1010 *** mbit */ { @@ -2118,7 +2183,7 @@ const opcode_entry_type z8k_table[] = { "mbit",16,7,0x38, #endif "mbit",OPC_mbit,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,87}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,92}, /* 0111 1011 dddd 1101 *** mreq rd */ { @@ -2126,7 +2191,7 @@ const opcode_entry_type z8k_table[] = { "mreq rd",16,12,0x18, #endif "mreq",OPC_mreq,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,88}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,93}, /* 0111 1011 0000 1001 *** mres */ { @@ -2134,7 +2199,7 @@ const opcode_entry_type z8k_table[] = { "mres",16,5,0x00, #endif "mres",OPC_mres,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,89}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,94}, /* 0111 1011 0000 1000 *** mset */ { @@ -2142,7 +2207,7 @@ const opcode_entry_type z8k_table[] = { "mset",16,5,0x00, #endif "mset",OPC_mset,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,90}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,95}, /* 0001 1001 ssN0 dddd *** mult rrd,@rs */ { @@ -2150,7 +2215,7 @@ const opcode_entry_type z8k_table[] = { "mult rrd,@rs",16,70,0x3c, #endif "mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,91}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, /* 0101 1001 0000 dddd address_src *** mult rrd,address_src */ { @@ -2158,7 +2223,7 @@ const opcode_entry_type z8k_table[] = { "mult rrd,address_src",16,70,0x3c, #endif "mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,91}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, /* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */ { @@ -2166,7 +2231,7 @@ const opcode_entry_type z8k_table[] = { "mult rrd,address_src(rs)",16,70,0x3c, #endif "mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,91}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, /* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */ { @@ -2174,7 +2239,7 @@ const opcode_entry_type z8k_table[] = { "mult rrd,imm16",16,70,0x3c, #endif "mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,91}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,96}, /* 1001 1001 ssss dddd *** mult rrd,rs */ { @@ -2182,7 +2247,7 @@ const opcode_entry_type z8k_table[] = { "mult rrd,rs",16,70,0x3c, #endif "mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,91}, + {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, /* 0001 1000 ssN0 dddd *** multl rqd,@rs */ { @@ -2190,7 +2255,7 @@ const opcode_entry_type z8k_table[] = { "multl rqd,@rs",32,282,0x3c, #endif "multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,92}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, /* 0101 1000 0000 dddd address_src *** multl rqd,address_src */ { @@ -2198,7 +2263,7 @@ const opcode_entry_type z8k_table[] = { "multl rqd,address_src",32,282,0x3c, #endif "multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,92}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, /* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */ { @@ -2206,7 +2271,7 @@ const opcode_entry_type z8k_table[] = { "multl rqd,address_src(rs)",32,282,0x3c, #endif "multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,92}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, /* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */ { @@ -2214,7 +2279,7 @@ const opcode_entry_type z8k_table[] = { "multl rqd,imm32",32,282,0x3c, #endif "multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,92}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,97}, /* 1001 1000 ssss dddd *** multl rqd,rrs */ { @@ -2222,7 +2287,7 @@ const opcode_entry_type z8k_table[] = { "multl rqd,rrs",32,282,0x3c, #endif "multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,92}, + {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, /* 0000 1101 ddN0 0010 *** neg @rd */ { @@ -2230,7 +2295,7 @@ const opcode_entry_type z8k_table[] = { "neg @rd",16,12,0x3c, #endif "neg",OPC_neg,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,93}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,98}, /* 0100 1101 0000 0010 address_dst *** neg address_dst */ { @@ -2238,7 +2303,7 @@ const opcode_entry_type z8k_table[] = { "neg address_dst",16,15,0x3c, #endif "neg",OPC_neg,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,93}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,98}, /* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */ { @@ -2246,7 +2311,7 @@ const opcode_entry_type z8k_table[] = { "neg address_dst(rd)",16,16,0x3c, #endif "neg",OPC_neg,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,93}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,98}, /* 1000 1101 dddd 0010 *** neg rd */ { @@ -2254,7 +2319,7 @@ const opcode_entry_type z8k_table[] = { "neg rd",16,7,0x3c, #endif "neg",OPC_neg,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,93}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,98}, /* 0000 1100 ddN0 0010 *** negb @rd */ { @@ -2262,7 +2327,7 @@ const opcode_entry_type z8k_table[] = { "negb @rd",8,12,0x3c, #endif "negb",OPC_negb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,94}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,99}, /* 0100 1100 0000 0010 address_dst *** negb address_dst */ { @@ -2270,7 +2335,7 @@ const opcode_entry_type z8k_table[] = { "negb address_dst",8,15,0x3c, #endif "negb",OPC_negb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,94}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,99}, /* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */ { @@ -2278,7 +2343,7 @@ const opcode_entry_type z8k_table[] = { "negb address_dst(rd)",8,16,0x3c, #endif "negb",OPC_negb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,94}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,99}, /* 1000 1100 dddd 0010 *** negb rbd */ { @@ -2286,7 +2351,7 @@ const opcode_entry_type z8k_table[] = { "negb rbd",8,7,0x3c, #endif "negb",OPC_negb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,94}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,99}, /* 1000 1101 0000 0111 *** nop */ { @@ -2294,7 +2359,7 @@ const opcode_entry_type z8k_table[] = { "nop",16,7,0x00, #endif "nop",OPC_nop,0,{0}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,95}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,100}, /* 0000 0101 ssN0 dddd *** or rd,@rs */ { @@ -2302,7 +2367,7 @@ const opcode_entry_type z8k_table[] = { "or rd,@rs",16,7,0x38, #endif "or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,101}, /* 0100 0101 0000 dddd address_src *** or rd,address_src */ { @@ -2310,7 +2375,7 @@ const opcode_entry_type z8k_table[] = { "or rd,address_src",16,9,0x38, #endif "or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,101}, /* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */ { @@ -2318,7 +2383,7 @@ const opcode_entry_type z8k_table[] = { "or rd,address_src(rs)",16,10,0x38, #endif "or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,101}, /* 0000 0101 0000 dddd imm16 *** or rd,imm16 */ { @@ -2326,7 +2391,7 @@ const opcode_entry_type z8k_table[] = { "or rd,imm16",16,7,0x38, #endif "or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,96}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,101}, /* 1000 0101 ssss dddd *** or rd,rs */ { @@ -2334,7 +2399,7 @@ const opcode_entry_type z8k_table[] = { "or rd,rs",16,4,0x38, #endif "or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, + {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,101}, /* 0000 0100 ssN0 dddd *** orb rbd,@rs */ { @@ -2342,7 +2407,7 @@ const opcode_entry_type z8k_table[] = { "orb rbd,@rs",8,7,0x3c, #endif "orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,102}, /* 0100 0100 0000 dddd address_src *** orb rbd,address_src */ { @@ -2350,7 +2415,7 @@ const opcode_entry_type z8k_table[] = { "orb rbd,address_src",8,9,0x3c, #endif "orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,102}, /* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */ { @@ -2358,7 +2423,7 @@ const opcode_entry_type z8k_table[] = { "orb rbd,address_src(rs)",8,10,0x3c, #endif "orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,102}, /* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */ { @@ -2366,7 +2431,7 @@ const opcode_entry_type z8k_table[] = { "orb rbd,imm8",8,7,0x3c, #endif "orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,97}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,102}, /* 1000 0100 ssss dddd *** orb rbd,rbs */ { @@ -2374,79 +2439,103 @@ const opcode_entry_type z8k_table[] = { "orb rbd,rbs",8,4,0x3c, #endif "orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, + {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,102}, -/* 0011 1111 ddN0 ssss *** out @rd,rs */ +/* 0011 1011 ssN0 1010 0000 aaaa dddd 0000 *** otdr @ro,@rs,ra */ { #ifdef NICENAMES -"out @rd,rs",16,0,0x04, +"otdr @ro,@rs,ra",16,11,0x04, #endif -"out",OPC_out,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,98}, +"otdr",OPC_otdr,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,103}, -/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ +/* 0011 1010 ssN0 1010 0000 aaaa dddd 0000 *** otdrb @ro,@rs,ra */ { #ifdef NICENAMES -"out imm16,rs",16,0,0x04, +"otdrb @ro,@rs,ra",8,11,0x04, #endif -"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,98}, +"otdrb",OPC_otdrb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,104}, -/* 0011 1110 ddN0 ssss *** outb @rd,rbs */ +/* 0011 1011 ssN0 0010 0000 aaaa dddd 0000 *** otir @ro,@rs,ra */ { #ifdef NICENAMES -"outb @rd,rbs",8,0,0x04, +"otir @ro,@rs,ra",16,11,0x04, #endif -"outb",OPC_outb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,99}, +"otir",OPC_otir,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,105}, -/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ +/* 0011 1010 ssN0 0010 0000 aaaa dddd 0000 *** otirb @ro,@rs,ra */ { #ifdef NICENAMES -"outb imm16,rbs",8,0,0x04, +"otirb @ro,@rs,ra",8,11,0x04, #endif -"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,99}, +"otirb",OPC_otirb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,106}, -/* 0011 1011 ssN0 1010 0000 aaaa ddN0 1000 *** outd @rd,@rs,ra */ +/* 0011 1111 dddd ssss *** out @ro,rs */ { #ifdef NICENAMES -"outd @rd,@rs,ra",16,0,0x04, +"out @ro,rs",16,10,0x00, #endif -"outd",OPC_outd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,100}, +"out",OPC_out,0,{CLASS_IRO+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,107}, -/* 0011 1010 ssN0 1010 0000 aaaa ddN0 1000 *** outdb @rd,@rs,rba */ +/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ { #ifdef NICENAMES -"outdb @rd,@rs,rba",16,0,0x04, +"out imm16,rs",16,12,0x00, #endif -"outdb",OPC_outdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,101}, +"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,107}, -/* 0011 1011 ssN0 0010 0000 aaaa ddN0 1000 *** outi @rd,@rs,ra */ +/* 0011 1110 dddd ssss *** outb @ro,rbs */ { #ifdef NICENAMES -"outi @rd,@rs,ra",16,0,0x04, +"outb @ro,rbs",8,10,0x00, #endif -"outi",OPC_outi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,102}, +"outb",OPC_outb,0,{CLASS_IRO+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,108}, -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 1000 *** outib @rd,@rs,ra */ +/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ { #ifdef NICENAMES -"outib @rd,@rs,ra",16,0,0x04, +"outb imm16,rbs",8,12,0x00, #endif -"outib",OPC_outib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,103}, +"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,108}, -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 0000 *** outibr @rd,@rs,ra */ +/* 0011 1011 ssN0 1010 0000 aaaa dddd 1000 *** outd @ro,@rs,ra */ { #ifdef NICENAMES -"outibr @rd,@rs,ra",16,0,0x04, +"outd @ro,@rs,ra",16,21,0x04, #endif -"outibr",OPC_outibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,104}, +"outd",OPC_outd,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,109}, + +/* 0011 1010 ssN0 1010 0000 aaaa dddd 1000 *** outdb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outdb @ro,@rs,ra",8,21,0x04, +#endif +"outdb",OPC_outdb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,110}, + +/* 0011 1011 ssN0 0010 0000 aaaa dddd 1000 *** outi @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outi @ro,@rs,ra",16,21,0x04, +#endif +"outi",OPC_outi,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,111}, + +/* 0011 1010 ssN0 0010 0000 aaaa dddd 1000 *** outib @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outib @ro,@rs,ra",8,21,0x04, +#endif +"outib",OPC_outib,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,112}, /* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */ { @@ -2454,7 +2543,7 @@ const opcode_entry_type z8k_table[] = { "pop @rd,@rs",16,12,0x00, #endif "pop",OPC_pop,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,105}, + {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,113}, /* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */ { @@ -2462,7 +2551,7 @@ const opcode_entry_type z8k_table[] = { "pop address_dst(rd),@rs",16,16,0x00, #endif "pop",OPC_pop,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,105}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,113}, /* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */ { @@ -2470,7 +2559,7 @@ const opcode_entry_type z8k_table[] = { "pop address_dst,@rs",16,16,0x00, #endif "pop",OPC_pop,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,105}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,113}, /* 1001 0111 ssN0 dddd *** pop rd,@rs */ { @@ -2478,7 +2567,7 @@ const opcode_entry_type z8k_table[] = { "pop rd,@rs",16,8,0x00, #endif "pop",OPC_pop,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,105}, + {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,113}, /* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */ { @@ -2486,7 +2575,7 @@ const opcode_entry_type z8k_table[] = { "popl @rd,@rs",32,19,0x00, #endif "popl",OPC_popl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,106}, + {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,114}, /* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */ { @@ -2494,7 +2583,7 @@ const opcode_entry_type z8k_table[] = { "popl address_dst(rd),@rs",32,23,0x00, #endif "popl",OPC_popl,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,106}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,114}, /* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */ { @@ -2502,7 +2591,7 @@ const opcode_entry_type z8k_table[] = { "popl address_dst,@rs",32,23,0x00, #endif "popl",OPC_popl,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,106}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,114}, /* 1001 0101 ssN0 dddd *** popl rrd,@rs */ { @@ -2510,7 +2599,7 @@ const opcode_entry_type z8k_table[] = { "popl rrd,@rs",32,12,0x00, #endif "popl",OPC_popl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,106}, + {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,114}, /* 0001 0011 ddN0 ssN0 *** push @rd,@rs */ { @@ -2518,7 +2607,7 @@ const opcode_entry_type z8k_table[] = { "push @rd,@rs",16,13,0x00, #endif "push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,107}, + {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,115}, /* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */ { @@ -2526,7 +2615,7 @@ const opcode_entry_type z8k_table[] = { "push @rd,address_src",16,14,0x00, #endif "push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,107}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,115}, /* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */ { @@ -2534,7 +2623,7 @@ const opcode_entry_type z8k_table[] = { "push @rd,address_src(rs)",16,14,0x00, #endif "push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,107}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,115}, /* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */ { @@ -2542,7 +2631,7 @@ const opcode_entry_type z8k_table[] = { "push @rd,imm16",16,12,0x00, #endif "push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,107}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,115}, /* 1001 0011 ddN0 ssss *** push @rd,rs */ { @@ -2550,7 +2639,7 @@ const opcode_entry_type z8k_table[] = { "push @rd,rs",16,9,0x00, #endif "push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,107}, + {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,115}, /* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */ { @@ -2558,7 +2647,7 @@ const opcode_entry_type z8k_table[] = { "pushl @rd,@rs",32,20,0x00, #endif "pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,108}, + {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,116}, /* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */ { @@ -2566,7 +2655,7 @@ const opcode_entry_type z8k_table[] = { "pushl @rd,address_src",32,21,0x00, #endif "pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,108}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,116}, /* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */ { @@ -2574,7 +2663,7 @@ const opcode_entry_type z8k_table[] = { "pushl @rd,address_src(rs)",32,21,0x00, #endif "pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,108}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,116}, /* 1001 0001 ddN0 ssss *** pushl @rd,rrs */ { @@ -2582,7 +2671,7 @@ const opcode_entry_type z8k_table[] = { "pushl @rd,rrs",32,12,0x00, #endif "pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,108}, + {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,116}, /* 0010 0011 ddN0 imm4 *** res @rd,imm4 */ { @@ -2590,7 +2679,7 @@ const opcode_entry_type z8k_table[] = { "res @rd,imm4",16,11,0x00, #endif "res",OPC_res,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,109}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,117}, /* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */ { @@ -2598,7 +2687,7 @@ const opcode_entry_type z8k_table[] = { "res address_dst(rd),imm4",16,14,0x00, #endif "res",OPC_res,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,109}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,117}, /* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */ { @@ -2606,7 +2695,7 @@ const opcode_entry_type z8k_table[] = { "res address_dst,imm4",16,13,0x00, #endif "res",OPC_res,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,109}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,117}, /* 1010 0011 dddd imm4 *** res rd,imm4 */ { @@ -2614,7 +2703,7 @@ const opcode_entry_type z8k_table[] = { "res rd,imm4",16,4,0x00, #endif "res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,109}, + {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,117}, /* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */ { @@ -2622,7 +2711,7 @@ const opcode_entry_type z8k_table[] = { "res rd,rs",16,10,0x00, #endif "res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,109}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,117}, /* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */ { @@ -2630,7 +2719,7 @@ const opcode_entry_type z8k_table[] = { "resb @rd,imm4",8,11,0x00, #endif "resb",OPC_resb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,110}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,118}, /* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */ { @@ -2638,7 +2727,7 @@ const opcode_entry_type z8k_table[] = { "resb address_dst(rd),imm4",8,14,0x00, #endif "resb",OPC_resb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,110}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,118}, /* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */ { @@ -2646,7 +2735,7 @@ const opcode_entry_type z8k_table[] = { "resb address_dst,imm4",8,13,0x00, #endif "resb",OPC_resb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,110}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,118}, /* 1010 0010 dddd imm4 *** resb rbd,imm4 */ { @@ -2654,7 +2743,7 @@ const opcode_entry_type z8k_table[] = { "resb rbd,imm4",8,4,0x00, #endif "resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,110}, + {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,118}, /* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */ { @@ -2662,7 +2751,7 @@ const opcode_entry_type z8k_table[] = { "resb rbd,rs",8,10,0x00, #endif "resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,110}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,118}, /* 1000 1101 flags 0011 *** resflg flags */ { @@ -2670,7 +2759,7 @@ const opcode_entry_type z8k_table[] = { "resflg flags",16,7,0x3c, #endif "resflg",OPC_resflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,111}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,119}, /* 1001 1110 0000 cccc *** ret cc */ { @@ -2678,7 +2767,7 @@ const opcode_entry_type z8k_table[] = { "ret cc",16,10,0x00, #endif "ret",OPC_ret,0,{CLASS_CC,}, - {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,112}, + {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,120}, /* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */ { @@ -2686,7 +2775,7 @@ const opcode_entry_type z8k_table[] = { "rl rd,imm1or2",16,6,0x3c, #endif "rl",OPC_rl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,113}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,121}, /* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */ { @@ -2694,7 +2783,7 @@ const opcode_entry_type z8k_table[] = { "rlb rbd,imm1or2",8,6,0x3c, #endif "rlb",OPC_rlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,114}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,122}, /* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */ { @@ -2702,7 +2791,7 @@ const opcode_entry_type z8k_table[] = { "rlc rd,imm1or2",16,6,0x3c, #endif "rlc",OPC_rlc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,115}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,123}, /* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */ { @@ -2710,7 +2799,7 @@ const opcode_entry_type z8k_table[] = { "rlcb rbd,imm1or2",8,9,0x10, #endif "rlcb",OPC_rlcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,116}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,124}, /* 1011 1110 aaaa bbbb *** rldb rbb,rba */ { @@ -2718,7 +2807,7 @@ const opcode_entry_type z8k_table[] = { "rldb rbb,rba",8,9,0x10, #endif "rldb",OPC_rldb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,117}, + {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,125}, /* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */ { @@ -2726,7 +2815,7 @@ const opcode_entry_type z8k_table[] = { "rr rd,imm1or2",16,6,0x3c, #endif "rr",OPC_rr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,118}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,126}, /* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */ { @@ -2734,7 +2823,7 @@ const opcode_entry_type z8k_table[] = { "rrb rbd,imm1or2",8,6,0x3c, #endif "rrb",OPC_rrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,119}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,127}, /* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */ { @@ -2742,7 +2831,7 @@ const opcode_entry_type z8k_table[] = { "rrc rd,imm1or2",16,6,0x3c, #endif "rrc",OPC_rrc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,120}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,128}, /* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */ { @@ -2750,7 +2839,7 @@ const opcode_entry_type z8k_table[] = { "rrcb rbd,imm1or2",8,9,0x10, #endif "rrcb",OPC_rrcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,121}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,129}, /* 1011 1100 aaaa bbbb *** rrdb rbb,rba */ { @@ -2758,7 +2847,7 @@ const opcode_entry_type z8k_table[] = { "rrdb rbb,rba",8,9,0x10, #endif "rrdb",OPC_rrdb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,122}, + {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,130}, /* 0011 0110 imm8 *** rsvd36 */ { @@ -2766,7 +2855,7 @@ const opcode_entry_type z8k_table[] = { "rsvd36",8,10,0x00, #endif "rsvd36",OPC_rsvd36,0,{0}, - {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,123}, + {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,131}, /* 0011 1000 imm8 *** rsvd38 */ { @@ -2774,7 +2863,7 @@ const opcode_entry_type z8k_table[] = { "rsvd38",8,10,0x00, #endif "rsvd38",OPC_rsvd38,0,{0}, - {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,124}, + {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,132}, /* 0111 1000 imm8 *** rsvd78 */ { @@ -2782,7 +2871,7 @@ const opcode_entry_type z8k_table[] = { "rsvd78",8,10,0x00, #endif "rsvd78",OPC_rsvd78,0,{0}, - {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,125}, + {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,133}, /* 0111 1110 imm8 *** rsvd7e */ { @@ -2790,7 +2879,7 @@ const opcode_entry_type z8k_table[] = { "rsvd7e",8,10,0x00, #endif "rsvd7e",OPC_rsvd7e,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,126}, + {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,134}, /* 1001 1101 imm8 *** rsvd9d */ { @@ -2798,7 +2887,7 @@ const opcode_entry_type z8k_table[] = { "rsvd9d",8,10,0x00, #endif "rsvd9d",OPC_rsvd9d,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,127}, + {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,135}, /* 1001 1111 imm8 *** rsvd9f */ { @@ -2806,7 +2895,7 @@ const opcode_entry_type z8k_table[] = { "rsvd9f",8,10,0x00, #endif "rsvd9f",OPC_rsvd9f,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,128}, + {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,136}, /* 1011 1001 imm8 *** rsvdb9 */ { @@ -2814,7 +2903,7 @@ const opcode_entry_type z8k_table[] = { "rsvdb9",8,10,0x00, #endif "rsvdb9",OPC_rsvdb9,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,129}, + {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,137}, /* 1011 1111 imm8 *** rsvdbf */ { @@ -2822,7 +2911,7 @@ const opcode_entry_type z8k_table[] = { "rsvdbf",8,10,0x00, #endif "rsvdbf",OPC_rsvdbf,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,130}, + {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,138}, /* 1011 0111 ssss dddd *** sbc rd,rs */ { @@ -2830,7 +2919,7 @@ const opcode_entry_type z8k_table[] = { "sbc rd,rs",16,5,0x3c, #endif "sbc",OPC_sbc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,131}, + {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,139}, /* 1011 0110 ssss dddd *** sbcb rbd,rbs */ { @@ -2838,7 +2927,7 @@ const opcode_entry_type z8k_table[] = { "sbcb rbd,rbs",8,5,0x3f, #endif "sbcb",OPC_sbcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,132}, + {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,140}, /* 0111 1111 imm8 *** sc imm8 */ { @@ -2846,7 +2935,7 @@ const opcode_entry_type z8k_table[] = { "sc imm8",8,33,0x3f, #endif "sc",OPC_sc,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,133}, + {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,141}, /* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */ { @@ -2854,7 +2943,7 @@ const opcode_entry_type z8k_table[] = { "sda rd,rs",16,15,0x3c, #endif "sda",OPC_sda,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,134}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,142}, /* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */ { @@ -2862,7 +2951,7 @@ const opcode_entry_type z8k_table[] = { "sdab rbd,rs",8,15,0x3c, #endif "sdab",OPC_sdab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,135}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,143}, /* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */ { @@ -2870,7 +2959,7 @@ const opcode_entry_type z8k_table[] = { "sdal rrd,rs",32,15,0x3c, #endif "sdal",OPC_sdal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,136}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,144}, /* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */ { @@ -2878,7 +2967,7 @@ const opcode_entry_type z8k_table[] = { "sdl rd,rs",16,15,0x38, #endif "sdl",OPC_sdl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,137}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,145}, /* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */ { @@ -2886,7 +2975,7 @@ const opcode_entry_type z8k_table[] = { "sdlb rbd,rs",8,15,0x38, #endif "sdlb",OPC_sdlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,138}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,146}, /* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */ { @@ -2894,7 +2983,7 @@ const opcode_entry_type z8k_table[] = { "sdll rrd,rs",32,15,0x38, #endif "sdll",OPC_sdll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,139}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,147}, /* 0010 0101 ddN0 imm4 *** set @rd,imm4 */ { @@ -2902,7 +2991,7 @@ const opcode_entry_type z8k_table[] = { "set @rd,imm4",16,11,0x00, #endif "set",OPC_set,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,140}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,148}, /* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */ { @@ -2910,7 +2999,7 @@ const opcode_entry_type z8k_table[] = { "set address_dst(rd),imm4",16,14,0x00, #endif "set",OPC_set,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,140}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,148}, /* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */ { @@ -2918,7 +3007,7 @@ const opcode_entry_type z8k_table[] = { "set address_dst,imm4",16,13,0x00, #endif "set",OPC_set,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,140}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,148}, /* 1010 0101 dddd imm4 *** set rd,imm4 */ { @@ -2926,7 +3015,7 @@ const opcode_entry_type z8k_table[] = { "set rd,imm4",16,4,0x00, #endif "set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,140}, + {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,148}, /* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */ { @@ -2934,7 +3023,7 @@ const opcode_entry_type z8k_table[] = { "set rd,rs",16,10,0x00, #endif "set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,140}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,148}, /* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */ { @@ -2942,7 +3031,7 @@ const opcode_entry_type z8k_table[] = { "setb @rd,imm4",8,11,0x00, #endif "setb",OPC_setb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,141}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,149}, /* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */ { @@ -2950,7 +3039,7 @@ const opcode_entry_type z8k_table[] = { "setb address_dst(rd),imm4",8,14,0x00, #endif "setb",OPC_setb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,141}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,149}, /* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */ { @@ -2958,7 +3047,7 @@ const opcode_entry_type z8k_table[] = { "setb address_dst,imm4",8,13,0x00, #endif "setb",OPC_setb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,141}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,149}, /* 1010 0100 dddd imm4 *** setb rbd,imm4 */ { @@ -2966,7 +3055,7 @@ const opcode_entry_type z8k_table[] = { "setb rbd,imm4",8,4,0x00, #endif "setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,141}, + {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,149}, /* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */ { @@ -2974,7 +3063,7 @@ const opcode_entry_type z8k_table[] = { "setb rbd,rs",8,10,0x00, #endif "setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,141}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,149}, /* 1000 1101 flags 0001 *** setflg flags */ { @@ -2982,55 +3071,87 @@ const opcode_entry_type z8k_table[] = { "setflg flags",16,7,0x3c, #endif "setflg",OPC_setflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,142}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,150}, /* 0011 1011 dddd 0101 imm16 *** sin rd,imm16 */ { #ifdef NICENAMES -"sin rd,imm16",8,0,0x00, +"sin rd,imm16",16,12,0x00, #endif "sin",OPC_sin,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,143}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,151}, /* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */ { #ifdef NICENAMES -"sinb rbd,imm16",8,0,0x00, +"sinb rbd,imm16",8,10,0x00, #endif "sinb",OPC_sinb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,144}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,152}, + +/* 0011 1011 ssss 1001 0000 aaaa ddN0 1000 *** sind @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sind @rd,@ri,ra",16,21,0x04, +#endif +"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,153}, + +/* 0011 1010 ssss 1001 0000 aaaa ddN0 1000 *** sindb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindb @rd,@ri,ra",8,21,0x04, +#endif +"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,154}, + +/* 0011 1011 ssss 1001 0000 aaaa ddN0 0000 *** sindr @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindr @rd,@ri,ra",16,11,0x04, +#endif +"sindr",OPC_sindr,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,155}, + +/* 0011 1010 ssss 1001 0000 aaaa ddN0 0000 *** sindrb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindrb @rd,@ri,ra",8,11,0x04, +#endif +"sindrb",OPC_sindrb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,156}, -/* 0011 1011 ssN0 1000 0001 aaaa ddN0 1000 *** sind @rd,@rs,ra */ +/* 0011 1011 ssss 0001 0000 aaaa ddN0 1000 *** sini @rd,@ri,ra */ { #ifdef NICENAMES -"sind @rd,@rs,ra",16,0,0x00, +"sini @rd,@ri,ra",16,21,0x04, #endif -"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,145}, +"sini",OPC_sini,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,157}, -/* 0011 1010 ssN0 1000 0001 aaaa ddN0 1000 *** sindb @rd,@rs,rba */ +/* 0011 1010 ssss 0001 0000 aaaa ddN0 1000 *** sinib @rd,@ri,ra */ { #ifdef NICENAMES -"sindb @rd,@rs,rba",8,0,0x00, +"sinib @rd,@ri,ra",8,21,0x04, #endif -"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,146}, +"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,158}, -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 1000 *** sinib @rd,@rs,ra */ +/* 0011 1011 ssss 0001 0000 aaaa ddN0 0000 *** sinir @rd,@ri,ra */ { #ifdef NICENAMES -"sinib @rd,@rs,ra",8,0,0x00, +"sinir @rd,@ri,ra",16,11,0x04, #endif -"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,147}, +"sinir",OPC_sinir,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,159}, -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 0000 *** sinibr @rd,@rs,ra */ +/* 0011 1010 ssss 0001 0000 aaaa ddN0 0000 *** sinirb @rd,@ri,ra */ { #ifdef NICENAMES -"sinibr @rd,@rs,ra",16,0,0x00, +"sinirb @rd,@ri,ra",8,11,0x04, #endif -"sinibr",OPC_sinibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,148}, +"sinirb",OPC_sinirb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,160}, /* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */ { @@ -3038,7 +3159,7 @@ const opcode_entry_type z8k_table[] = { "sla rd,imm8",16,13,0x3c, #endif "sla",OPC_sla,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,149}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,161}, /* 1011 0010 dddd 1001 iiii iiii 0000 imm4 *** slab rbd,imm4 */ { @@ -3046,7 +3167,7 @@ const opcode_entry_type z8k_table[] = { "slab rbd,imm4",8,13,0x3c, #endif "slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,150}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,162}, /* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */ { @@ -3054,7 +3175,7 @@ const opcode_entry_type z8k_table[] = { "slal rrd,imm8",32,13,0x3c, #endif "slal",OPC_slal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,151}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,163}, /* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */ { @@ -3062,7 +3183,7 @@ const opcode_entry_type z8k_table[] = { "sll rd,imm8",16,13,0x38, #endif "sll",OPC_sll,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,152}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,164}, /* 1011 0010 dddd 0001 iiii iiii 0000 imm4 *** sllb rbd,imm4 */ { @@ -3070,7 +3191,7 @@ const opcode_entry_type z8k_table[] = { "sllb rbd,imm4",8,13,0x38, #endif "sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,153}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,165}, /* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */ { @@ -3078,55 +3199,87 @@ const opcode_entry_type z8k_table[] = { "slll rrd,imm8",32,13,0x38, #endif "slll",OPC_slll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,154}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,166}, + +/* 0011 1011 ssN0 1011 0000 aaaa dddd 0000 *** sotdr @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotdr @ro,@rs,ra",16,11,0x04, +#endif +"sotdr",OPC_sotdr,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,167}, + +/* 0011 1010 ssN0 1011 0000 aaaa dddd 0000 *** sotdrb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotdrb @ro,@rs,ra",8,11,0x04, +#endif +"sotdrb",OPC_sotdrb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,168}, + +/* 0011 1011 ssN0 0011 0000 aaaa dddd 0000 *** sotir @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotir @ro,@rs,ra",16,11,0x04, +#endif +"sotir",OPC_sotir,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,169}, + +/* 0011 1010 ssN0 0011 0000 aaaa dddd 0000 *** sotirb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotirb @ro,@rs,ra",8,11,0x04, +#endif +"sotirb",OPC_sotirb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,170}, -/* 0011 1011 ssss 0111 imm16 *** sout imm16,rs */ +/* 0011 1011 ssss 0110 imm16 *** sout imm16,rs */ { #ifdef NICENAMES -"sout imm16,rs",16,0,0x00, +"sout imm16,rs",16,12,0x00, #endif "sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,155}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,171}, -/* 0011 1010 ssss 0111 imm16 *** soutb imm16,rbs */ +/* 0011 1010 ssss 0110 imm16 *** soutb imm16,rbs */ { #ifdef NICENAMES -"soutb imm16,rbs",8,0,0x00, +"soutb imm16,rbs",8,12,0x00, #endif "soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,156}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,172}, -/* 0011 1011 ssN0 1011 0000 aaaa ddN0 1000 *** soutd @rd,@rs,ra */ +/* 0011 1011 ssN0 1011 0000 aaaa dddd 1000 *** soutd @ro,@rs,ra */ { #ifdef NICENAMES -"soutd @rd,@rs,ra",16,0,0x00, +"soutd @ro,@rs,ra",16,21,0x04, #endif -"soutd",OPC_soutd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,157}, +"soutd",OPC_soutd,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,173}, -/* 0011 1010 ssN0 1011 0000 aaaa ddN0 1000 *** soutdb @rd,@rs,rba */ +/* 0011 1010 ssN0 1011 0000 aaaa dddd 1000 *** soutdb @ro,@rs,ra */ { #ifdef NICENAMES -"soutdb @rd,@rs,rba",8,0,0x00, +"soutdb @ro,@rs,ra",8,21,0x04, #endif -"soutdb",OPC_soutdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,158}, +"soutdb",OPC_soutdb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,174}, -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 1000 *** soutib @rd,@rs,ra */ +/* 0011 1011 ssN0 0011 0000 aaaa dddd 1000 *** souti @ro,@rs,ra */ { #ifdef NICENAMES -"soutib @rd,@rs,ra",8,0,0x00, +"souti @ro,@rs,ra",16,21,0x04, #endif -"soutib",OPC_soutib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,159}, +"souti",OPC_souti,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,175}, -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 0000 *** soutibr @rd,@rs,ra */ +/* 0011 1010 ssN0 0011 0000 aaaa dddd 1000 *** soutib @ro,@rs,ra */ { #ifdef NICENAMES -"soutibr @rd,@rs,ra",16,0,0x00, +"soutib @ro,@rs,ra",8,21,0x04, #endif -"soutibr",OPC_soutibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,160}, +"soutib",OPC_soutib,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,176}, /* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */ { @@ -3134,7 +3287,7 @@ const opcode_entry_type z8k_table[] = { "sra rd,imm8",16,13,0x3c, #endif "sra",OPC_sra,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,161}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,177}, /* 1011 0010 dddd 1001 iiii iiii 1111 nim4 *** srab rbd,imm4 */ { @@ -3142,7 +3295,7 @@ const opcode_entry_type z8k_table[] = { "srab rbd,imm4",8,13,0x3c, #endif "srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,162}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,178}, /* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */ { @@ -3150,7 +3303,7 @@ const opcode_entry_type z8k_table[] = { "sral rrd,imm8",32,13,0x3c, #endif "sral",OPC_sral,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,163}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,179}, /* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */ { @@ -3158,7 +3311,7 @@ const opcode_entry_type z8k_table[] = { "srl rd,imm8",16,13,0x3c, #endif "srl",OPC_srl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,164}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,180}, /* 1011 0010 dddd 0001 iiii iiii 1111 nim4 *** srlb rbd,imm4 */ { @@ -3166,7 +3319,7 @@ const opcode_entry_type z8k_table[] = { "srlb rbd,imm4",8,13,0x3c, #endif "srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,165}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,181}, /* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */ { @@ -3174,7 +3327,7 @@ const opcode_entry_type z8k_table[] = { "srll rrd,imm8",32,13,0x3c, #endif "srll",OPC_srll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,166}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,182}, /* 0000 0011 ssN0 dddd *** sub rd,@rs */ { @@ -3182,7 +3335,7 @@ const opcode_entry_type z8k_table[] = { "sub rd,@rs",16,7,0x3c, #endif "sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,167}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,183}, /* 0100 0011 0000 dddd address_src *** sub rd,address_src */ { @@ -3190,7 +3343,7 @@ const opcode_entry_type z8k_table[] = { "sub rd,address_src",16,9,0x3c, #endif "sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,167}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, /* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */ { @@ -3198,7 +3351,7 @@ const opcode_entry_type z8k_table[] = { "sub rd,address_src(rs)",16,10,0x3c, #endif "sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,167}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, /* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */ { @@ -3206,7 +3359,7 @@ const opcode_entry_type z8k_table[] = { "sub rd,imm16",16,7,0x3c, #endif "sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,167}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,183}, /* 1000 0011 ssss dddd *** sub rd,rs */ { @@ -3214,7 +3367,7 @@ const opcode_entry_type z8k_table[] = { "sub rd,rs",16,4,0x3c, #endif "sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,167}, + {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,183}, /* 0000 0010 ssN0 dddd *** subb rbd,@rs */ { @@ -3222,7 +3375,7 @@ const opcode_entry_type z8k_table[] = { "subb rbd,@rs",8,7,0x3f, #endif "subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,168}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,184}, /* 0100 0010 0000 dddd address_src *** subb rbd,address_src */ { @@ -3230,7 +3383,7 @@ const opcode_entry_type z8k_table[] = { "subb rbd,address_src",8,9,0x3f, #endif "subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,168}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, /* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */ { @@ -3238,7 +3391,7 @@ const opcode_entry_type z8k_table[] = { "subb rbd,address_src(rs)",8,10,0x3f, #endif "subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,168}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, /* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */ { @@ -3246,7 +3399,7 @@ const opcode_entry_type z8k_table[] = { "subb rbd,imm8",8,7,0x3f, #endif "subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,168}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,184}, /* 1000 0010 ssss dddd *** subb rbd,rbs */ { @@ -3254,7 +3407,7 @@ const opcode_entry_type z8k_table[] = { "subb rbd,rbs",8,4,0x3f, #endif "subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,168}, + {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,184}, /* 0001 0010 ssN0 dddd *** subl rrd,@rs */ { @@ -3262,7 +3415,7 @@ const opcode_entry_type z8k_table[] = { "subl rrd,@rs",32,14,0x3c, #endif "subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,169}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,185}, /* 0101 0010 0000 dddd address_src *** subl rrd,address_src */ { @@ -3270,7 +3423,7 @@ const opcode_entry_type z8k_table[] = { "subl rrd,address_src",32,15,0x3c, #endif "subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,169}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,185}, /* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */ { @@ -3278,7 +3431,7 @@ const opcode_entry_type z8k_table[] = { "subl rrd,address_src(rs)",32,16,0x3c, #endif "subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,169}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,185}, /* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */ { @@ -3286,7 +3439,7 @@ const opcode_entry_type z8k_table[] = { "subl rrd,imm32",32,14,0x3c, #endif "subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,169}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,185}, /* 1001 0010 ssss dddd *** subl rrd,rrs */ { @@ -3294,7 +3447,7 @@ const opcode_entry_type z8k_table[] = { "subl rrd,rrs",32,8,0x3c, #endif "subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,169}, + {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,185}, /* 1010 1111 dddd cccc *** tcc cc,rd */ { @@ -3302,7 +3455,7 @@ const opcode_entry_type z8k_table[] = { "tcc cc,rd",16,5,0x00, #endif "tcc",OPC_tcc,0,{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,170}, + {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,186}, /* 1010 1110 dddd cccc *** tccb cc,rbd */ { @@ -3310,7 +3463,7 @@ const opcode_entry_type z8k_table[] = { "tccb cc,rbd",8,5,0x00, #endif "tccb",OPC_tccb,0,{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,171}, + {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,187}, /* 0000 1101 ddN0 0100 *** test @rd */ { @@ -3318,7 +3471,7 @@ const opcode_entry_type z8k_table[] = { "test @rd",16,8,0x18, #endif "test",OPC_test,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,172}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,188}, /* 0100 1101 0000 0100 address_dst *** test address_dst */ { @@ -3326,7 +3479,7 @@ const opcode_entry_type z8k_table[] = { "test address_dst",16,11,0x00, #endif "test",OPC_test,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,172}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,188}, /* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */ { @@ -3334,7 +3487,7 @@ const opcode_entry_type z8k_table[] = { "test address_dst(rd)",16,12,0x00, #endif "test",OPC_test,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,172}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,188}, /* 1000 1101 dddd 0100 *** test rd */ { @@ -3342,7 +3495,7 @@ const opcode_entry_type z8k_table[] = { "test rd",16,7,0x00, #endif "test",OPC_test,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,172}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,188}, /* 0000 1100 ddN0 0100 *** testb @rd */ { @@ -3350,7 +3503,7 @@ const opcode_entry_type z8k_table[] = { "testb @rd",8,8,0x1c, #endif "testb",OPC_testb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,173}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,189}, /* 0100 1100 0000 0100 address_dst *** testb address_dst */ { @@ -3358,7 +3511,7 @@ const opcode_entry_type z8k_table[] = { "testb address_dst",8,11,0x1c, #endif "testb",OPC_testb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,173}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,189}, /* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */ { @@ -3366,7 +3519,7 @@ const opcode_entry_type z8k_table[] = { "testb address_dst(rd)",8,12,0x1c, #endif "testb",OPC_testb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,173}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,189}, /* 1000 1100 dddd 0100 *** testb rbd */ { @@ -3374,7 +3527,7 @@ const opcode_entry_type z8k_table[] = { "testb rbd",8,7,0x1c, #endif "testb",OPC_testb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,173}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,189}, /* 0001 1100 ddN0 1000 *** testl @rd */ { @@ -3382,7 +3535,7 @@ const opcode_entry_type z8k_table[] = { "testl @rd",32,13,0x18, #endif "testl",OPC_testl,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,174}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,190}, /* 0101 1100 0000 1000 address_dst *** testl address_dst */ { @@ -3390,7 +3543,7 @@ const opcode_entry_type z8k_table[] = { "testl address_dst",32,16,0x18, #endif "testl",OPC_testl,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,174}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,190}, /* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */ { @@ -3398,7 +3551,7 @@ const opcode_entry_type z8k_table[] = { "testl address_dst(rd)",32,17,0x18, #endif "testl",OPC_testl,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,174}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,190}, /* 1001 1100 dddd 1000 *** testl rrd */ { @@ -3406,7 +3559,7 @@ const opcode_entry_type z8k_table[] = { "testl rrd",32,13,0x18, #endif "testl",OPC_testl,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,174}, + {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,190}, /* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */ { @@ -3414,7 +3567,7 @@ const opcode_entry_type z8k_table[] = { "trdb @rd,@rs,rba",8,25,0x1c, #endif "trdb",OPC_trdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,175}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,191}, /* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */ { @@ -3422,7 +3575,7 @@ const opcode_entry_type z8k_table[] = { "trdrb @rd,@rs,rba",8,25,0x1c, #endif "trdrb",OPC_trdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,176}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,192}, /* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */ { @@ -3430,7 +3583,7 @@ const opcode_entry_type z8k_table[] = { "trib @rd,@rs,rbr",8,25,0x1c, #endif "trib",OPC_trib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,177}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,193}, /* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */ { @@ -3438,7 +3591,7 @@ const opcode_entry_type z8k_table[] = { "trirb @rd,@rs,rbr",8,25,0x1c, #endif "trirb",OPC_trirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,178}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,194}, /* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */ { @@ -3446,7 +3599,7 @@ const opcode_entry_type z8k_table[] = { "trtdb @ra,@rb,rbr",8,25,0x1c, #endif "trtdb",OPC_trtdb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,179}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,195}, /* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */ { @@ -3454,7 +3607,7 @@ const opcode_entry_type z8k_table[] = { "trtdrb @ra,@rb,rbr",8,25,0x1c, #endif "trtdrb",OPC_trtdrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,180}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,196}, /* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */ { @@ -3462,7 +3615,7 @@ const opcode_entry_type z8k_table[] = { "trtib @ra,@rb,rbr",8,25,0x1c, #endif "trtib",OPC_trtib,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,181}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,197}, /* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */ { @@ -3470,7 +3623,7 @@ const opcode_entry_type z8k_table[] = { "trtirb @ra,@rb,rbr",8,25,0x1c, #endif "trtirb",OPC_trtirb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,182}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,198}, /* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtrb @ra,@rb,rbr */ { @@ -3478,7 +3631,7 @@ const opcode_entry_type z8k_table[] = { "trtrb @ra,@rb,rbr",8,25,0x1c, #endif "trtrb",OPC_trtrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,183}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,199}, /* 0000 1101 ddN0 0110 *** tset @rd */ { @@ -3486,7 +3639,7 @@ const opcode_entry_type z8k_table[] = { "tset @rd",16,11,0x08, #endif "tset",OPC_tset,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,184}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,200}, /* 0100 1101 0000 0110 address_dst *** tset address_dst */ { @@ -3494,7 +3647,7 @@ const opcode_entry_type z8k_table[] = { "tset address_dst",16,14,0x08, #endif "tset",OPC_tset,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,184}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,200}, /* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */ { @@ -3502,7 +3655,7 @@ const opcode_entry_type z8k_table[] = { "tset address_dst(rd)",16,15,0x08, #endif "tset",OPC_tset,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,184}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,200}, /* 1000 1101 dddd 0110 *** tset rd */ { @@ -3510,7 +3663,7 @@ const opcode_entry_type z8k_table[] = { "tset rd",16,7,0x08, #endif "tset",OPC_tset,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,184}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,200}, /* 0000 1100 ddN0 0110 *** tsetb @rd */ { @@ -3518,7 +3671,7 @@ const opcode_entry_type z8k_table[] = { "tsetb @rd",8,11,0x08, #endif "tsetb",OPC_tsetb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,185}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,201}, /* 0100 1100 0000 0110 address_dst *** tsetb address_dst */ { @@ -3526,7 +3679,7 @@ const opcode_entry_type z8k_table[] = { "tsetb address_dst",8,14,0x08, #endif "tsetb",OPC_tsetb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,185}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,201}, /* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */ { @@ -3534,7 +3687,7 @@ const opcode_entry_type z8k_table[] = { "tsetb address_dst(rd)",8,15,0x08, #endif "tsetb",OPC_tsetb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,185}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,201}, /* 1000 1100 dddd 0110 *** tsetb rbd */ { @@ -3542,7 +3695,7 @@ const opcode_entry_type z8k_table[] = { "tsetb rbd",8,7,0x08, #endif "tsetb",OPC_tsetb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,185}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,201}, /* 0000 1001 ssN0 dddd *** xor rd,@rs */ { @@ -3550,7 +3703,7 @@ const opcode_entry_type z8k_table[] = { "xor rd,@rs",16,7,0x18, #endif "xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,186}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,202}, /* 0100 1001 0000 dddd address_src *** xor rd,address_src */ { @@ -3558,7 +3711,7 @@ const opcode_entry_type z8k_table[] = { "xor rd,address_src",16,9,0x18, #endif "xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,186}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,202}, /* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */ { @@ -3566,7 +3719,7 @@ const opcode_entry_type z8k_table[] = { "xor rd,address_src(rs)",16,10,0x18, #endif "xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,186}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,202}, /* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */ { @@ -3574,7 +3727,7 @@ const opcode_entry_type z8k_table[] = { "xor rd,imm16",16,7,0x18, #endif "xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,186}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,202}, /* 1000 1001 ssss dddd *** xor rd,rs */ { @@ -3582,7 +3735,7 @@ const opcode_entry_type z8k_table[] = { "xor rd,rs",16,4,0x18, #endif "xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,186}, + {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,202}, /* 0000 1000 ssN0 dddd *** xorb rbd,@rs */ { @@ -3590,7 +3743,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,@rs",8,7,0x1c, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,187}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,203}, /* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */ { @@ -3598,7 +3751,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,address_src",8,9,0x1c, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,187}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,203}, /* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */ { @@ -3606,7 +3759,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,address_src(rs)",8,10,0x1c, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,187}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,203}, /* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */ { @@ -3614,7 +3767,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,imm8",8,7,0x1c, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,187}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,203}, /* 1000 1000 ssss dddd *** xorb rbd,rbs */ { @@ -3622,7 +3775,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,rbs",8,4,0x1c, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,187}, + {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,203}, /* 1000 1000 ssss dddd *** xorb rbd,rbs */ { @@ -3630,7 +3783,7 @@ const opcode_entry_type z8k_table[] = { "xorb rbd,rbs",8,4,0x01, #endif "xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,187}, + {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,203}, /* end marker */ { diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c index efce2cf..df72791 100644 --- a/opcodes/z8kgen.c +++ b/opcodes/z8kgen.c @@ -1,4 +1,4 @@ -/* Copyright 2001, 2002 Free Software Foundation, Inc. +/* Copyright 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of GNU Binutils. @@ -17,7 +17,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* This program generates z8k-opc.h. */ +/* This program generates z8k-opc.h. Compile with -fwritable-strings. */ #include <stdio.h> #include "sysdep.h" @@ -38,6 +38,10 @@ struct op #define iswhite(x) ((x) == ' ' || (x) == '\t') struct op opt[] = { + {"------", 2, 8, "0011 0110 0000 0000", "bpt", 0}, /* Breakpoint used by the simulator. */ + {"------", 10, 8, "0000 1111 0000 1100", "brk", 0}, /* Breakpoint used by real hardware. + (ext0f #0x0c). */ + {"------", 10, 8, "0000 1110 imm8", "ext0e imm8", 0}, {"------", 10, 8, "0000 1111 imm8", "ext0f imm8", 0}, {"------", 10, 8, "1000 1110 imm8", "ext8e imm8", 0}, @@ -79,7 +83,6 @@ struct op opt[] = {"CZSV--", 11, 16, "1011 1011 ssN0 0110 0000 rrrr ddN0 cccc", "cpsir @rd,@rs,rr,cc", 0}, {"CZSV--", 11, 8, "1011 1010 ssN0 0110 0000 rrrr ddN0 cccc", "cpsirb @rd,@rs,rr,cc", 0}, - {"------", 2, 8, "0011 0110 0000 0000", "bpt", 0}, {"CZSV--", 5, 16, "1011 0101 ssss dddd", "adc rd,rs", 0}, {"CZSVDH", 5, 8, "1011 0100 ssss dddd", "adcb rbd,rbs", 0}, {"CZSV--", 7, 16, "0000 0001 ssN0 dddd", "add rd,@rs", 0}, @@ -209,8 +212,8 @@ struct op opt[] = {"------", 11, 32, "1011 0001 dddd 0111", "extsl rqd", 0}, {"------", 8, 16, "0111 1010 0000 0000", "halt", 0}, - {"------", 10, 16, "0011 1101 ssN0 dddd", "in rd,@rs", 0}, - {"------", 12, 8, "0011 1100 ssN0 dddd", "inb rbd,@rs", 0}, + {"------", 10, 16, "0011 1101 ssss dddd", "in rd,@ri", 0}, + {"------", 12, 8, "0011 1100 ssss dddd", "inb rbd,@ri", 0}, {"------", 12, 16, "0011 1011 dddd 0100 imm16", "in rd,imm16", 0}, {"------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0}, {"-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0}, @@ -221,10 +224,14 @@ struct op opt[] = {"-ZSV--", 14, 8, "0110 1000 ddN0 imm4m1 address_dst", "incb address_dst(rd),imm4m1", 0}, {"-ZSV--", 13, 8, "0110 1000 0000 imm4m1 address_dst", "incb address_dst,imm4m1", 0}, {"-ZSV--", 4, 8, "1010 1000 dddd imm4m1", "incb rbd,imm4m1", 0}, - {"---V--", 21, 16, "0011 1011 ssN0 1000 0000 aaaa ddN0 1000", "ind @rd,@rs,ra", 0}, - {"---V--", 21, 8, "0011 1010 ssN0 1000 0000 aaaa ddN0 1000", "indb @rd,@rs,rba", 0}, - {"---V--", 21, 8, "0011 1010 ssN0 0000 0000 aaaa ddN0 1000", "inib @rd,@rs,ra", 0}, - {"---V--", 21, 16, "0011 1010 ssN0 0000 0000 aaaa ddN0 0000", "inibr @rd,@rs,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 1000", "ind @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 1000 0000 aaaa ddN0 1000", "indb @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 0000", "indr @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 1000 0000 aaaa ddN0 0000", "indrb @rd,@ri,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssss 0000 0000 aaaa ddN0 1000", "ini @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 0000 0000 aaaa ddN0 1000", "inib @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 0000 0000 aaaa ddN0 0000", "inir @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 0000 0000 aaaa ddN0 0000", "inirb @rd,@ri,ra", 0}, {"CZSVDH", 13, 16, "0111 1011 0000 0000", "iret", 0}, {"------", 10, 16, "0001 1110 ddN0 cccc", "jp cc,@rd", 0}, {"------", 7, 16, "0101 1110 0000 cccc address_dst", "jp cc,address_dst", 0}, @@ -258,6 +265,7 @@ struct op opt[] = {"------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0}, {"------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0}, {"------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0}, + {"------", 7, 8, "0010 0000 0000 dddd imm8 imm8", "ldb rbd,imm8", 0}, {"------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0}, {"------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0}, {"------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0}, @@ -342,15 +350,18 @@ struct op opt[] = {"CZSP--", 7, 8, "0000 0100 0000 dddd imm8 imm8", "orb rbd,imm8", 0}, {"CZSP--", 4, 8, "1000 0100 ssss dddd", "orb rbd,rbs", 0}, - {"---V--", 0, 16, "0011 1111 ddN0 ssss", "out @rd,rs", 0}, - {"---V--", 0, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0}, - {"---V--", 0, 8, "0011 1110 ddN0 ssss", "outb @rd,rbs", 0}, - {"---V--", 0, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0}, - {"---V--", 0, 16, "0011 1011 ssN0 1010 0000 aaaa ddN0 1000", "outd @rd,@rs,ra", 0}, - {"---V--", 0, 16, "0011 1010 ssN0 1010 0000 aaaa ddN0 1000", "outdb @rd,@rs,rba", 0}, - {"---V--", 0, 16, "0011 1011 ssN0 0010 0000 aaaa ddN0 1000", "outi @rd,@rs,ra", 0}, - {"---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 1000", "outib @rd,@rs,ra", 0}, - {"---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 0000", "outibr @rd,@rs,ra", 0}, + {"------", 10, 16, "0011 1111 dddd ssss", "out @ro,rs", 0}, + {"------", 12, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0}, + {"------", 10, 8, "0011 1110 dddd ssss", "outb @ro,rbs", 0}, + {"------", 12, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 1010 0000 aaaa dddd 1000", "outd @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 1010 0000 aaaa dddd 1000", "outdb @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 1010 0000 aaaa dddd 0000", "otdr @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 1010 0000 aaaa dddd 0000", "otdrb @ro,@rs,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 0010 0000 aaaa dddd 1000", "outi @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 0010 0000 aaaa dddd 1000", "outib @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 0010 0000 aaaa dddd 0000", "otir @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 0010 0000 aaaa dddd 0000", "otirb @ro,@rs,ra", 0}, {"------", 12, 16, "0001 0111 ssN0 ddN0", "pop @rd,@rs", 0}, {"------", 16, 16, "0101 0111 ssN0 ddN0 address_dst", "pop address_dst(rd),@rs", 0}, @@ -427,12 +438,16 @@ struct op opt[] = {"CZSV--", 7, 16, "1000 1101 flags 0001", "setflg flags", 0}, - {"------", 0, 8, "0011 1010 dddd 0101 imm16", "sinb rbd,imm16", 0}, - {"------", 0, 8, "0011 1011 dddd 0101 imm16", "sin rd,imm16", 0}, - {"------", 0, 16, "0011 1011 ssN0 1000 0001 aaaa ddN0 1000", "sind @rd,@rs,ra", 0}, - {"------", 0, 8, "0011 1010 ssN0 1000 0001 aaaa ddN0 1000", "sindb @rd,@rs,rba", 0}, - {"------", 0, 8, "0011 1010 ssN0 0001 0000 aaaa ddN0 1000", "sinib @rd,@rs,ra", 0}, - {"------", 0, 16, "0011 1010 ssN0 0001 0000 aaaa ddN0 0000", "sinibr @rd,@rs,ra", 0}, + {"------", 12, 16, "0011 1011 dddd 0101 imm16", "sin rd,imm16", 0}, + {"------", 10, 8, "0011 1010 dddd 0101 imm16", "sinb rbd,imm16", 0}, + {"---V--", 21, 16, "0011 1011 ssss 1001 0000 aaaa ddN0 1000", "sind @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 1001 0000 aaaa ddN0 1000", "sindb @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 1001 0000 aaaa ddN0 0000", "sindr @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 1001 0000 aaaa ddN0 0000", "sindrb @rd,@ri,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssss 0001 0000 aaaa ddN0 1000", "sini @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 0001 0000 aaaa ddN0 1000", "sinib @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 0001 0000 aaaa ddN0 0000", "sinir @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 0001 0000 aaaa ddN0 0000", "sinirb @rd,@ri,ra", 0}, {"CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0}, {"CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 0000 imm4", "slab rbd,imm4", 0}, @@ -442,12 +457,16 @@ struct op opt[] = {"CZS---", 13, 8, "1011 0010 dddd 0001 iiii iiii 0000 imm4", "sllb rbd,imm4", 0}, {"CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0}, - {"------", 0, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0}, - {"------", 0, 8, "0011 1010 ssss 0111 imm16", "soutb imm16,rbs", 0}, - {"------", 0, 16, "0011 1011 ssN0 1011 0000 aaaa ddN0 1000", "soutd @rd,@rs,ra", 0}, - {"------", 0, 8, "0011 1010 ssN0 1011 0000 aaaa ddN0 1000", "soutdb @rd,@rs,rba", 0}, - {"------", 0, 8, "0011 1010 ssN0 0011 0000 aaaa ddN0 1000", "soutib @rd,@rs,ra", 0}, - {"------", 0, 16, "0011 1010 ssN0 0011 0000 aaaa ddN0 0000", "soutibr @rd,@rs,ra", 0}, + {"------", 12, 16, "0011 1011 ssss 0110 imm16", "sout imm16,rs", 0}, + {"------", 12, 8, "0011 1010 ssss 0110 imm16", "soutb imm16,rbs", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 1000", "soutd @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 1011 0000 aaaa dddd 1000", "soutdb @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 0000", "sotdr @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 1011 0000 aaaa dddd 0000", "sotdrb @ro,@rs,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 0011 0000 aaaa dddd 1000", "souti @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 0011 0000 aaaa dddd 1000", "soutib @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 0011 0000 aaaa dddd 0000", "sotir @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 0011 0000 aaaa dddd 0000", "sotirb @ro,@rs,ra", 0}, {"CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0}, {"CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 1111 nim4", "srab rbd,imm4", 0}, @@ -532,7 +551,7 @@ struct op opt[] = {"*", 0, 0, 0, 0, 0} }; -int +static int count () { struct op *p = opt; @@ -547,8 +566,7 @@ count () } -static -int +static int func (a, b) struct op *a; struct op *b; @@ -565,7 +583,6 @@ func (a, b) struct tok_struct { - char *match; char *token; int length; @@ -573,7 +590,6 @@ struct tok_struct struct tok_struct args[] = { - {"address_src(rs)", "CLASS_X+(ARG_RS)",}, {"address_dst(rd)", "CLASS_X+(ARG_RD)",}, @@ -616,6 +632,8 @@ struct tok_struct args[] = {"@ra", "CLASS_IR+(ARG_RA)",}, {"@rb", "CLASS_IR+(ARG_RB)",}, {"@rs", "CLASS_IR+(ARG_RS)",}, + {"@ri", "CLASS_IRO+(ARG_RS)",}, + {"@ro", "CLASS_IRO+(ARG_RD)",}, {"imm8", "CLASS_IMM+(ARG_IMM8)",}, {"i2", "CLASS_IMM+(ARG_IMM2)",}, @@ -741,7 +759,7 @@ translate (table, x, length) return x; } -void +static void chewbits (bits, length) char *bits; int *length; @@ -769,9 +787,7 @@ chewbits (bits, length) printf ("}"); } - -static -int +static int chewname (name) char **name; { @@ -813,8 +829,7 @@ chewname (name) return nargs; } -static -void +static void sub (x, c) char *x; char c; @@ -835,6 +850,7 @@ sub (x, c) #if 0 #define D(x) ((x) == '1' || (x) =='0') #define M(y) (strncmp(y,x,4)==0) +static void printmangled (x) char *x; { @@ -866,10 +882,10 @@ printmangled (x) } } - #endif + /*#define WORK_TYPE*/ -void +static void print_type (n) struct op *n; { @@ -896,8 +912,7 @@ print_type (n) #endif } - -void +static void internal () { int c = count (); @@ -905,15 +920,13 @@ internal () struct op *p = opt; memcpy (new, p, c * sizeof (struct op)); - /* sort all names in table alphabetically */ + /* Sort all names in table alphabetically. */ qsort (new, c, sizeof (struct op), func); p = new; - while (p->flags[0] != '*') + while (p->flags && p->flags[0] != '*') { - /* If there are any @rs, sub the ssss into a ssn0, - (rs), (ssn0) - */ + /* If there are any @rs, sub the ssss into a ssn0, (rs), (ssn0). */ int loop = 1; printf ("\"%s\",%2d, ", p->flags, p->cycles); @@ -928,7 +941,7 @@ internal () { char c; - /* skip the r and sub the string */ + /* Skip the r and sub the string. */ s++; c = s[1]; sub (p->bits, c); @@ -952,8 +965,7 @@ internal () } } -static -void +static void gas () { int c = count (); @@ -964,7 +976,7 @@ gas () memcpy (new, p, c * sizeof (struct op)); - /* sort all names in table alphabetically */ + /* Sort all names in table alphabetically. */ qsort (new, c, sizeof (struct op), func); printf ("/* DO NOT EDIT! -*- buffer-read-only: t -*-\n"); @@ -981,6 +993,7 @@ gas () printf ("#define ARG_RB 0x04\n"); printf ("#define ARG_RR 0x05\n"); printf ("#define ARG_RX 0x06\n"); + printf ("#define ARG_IMM4 0x01\n"); printf ("#define ARG_IMM8 0x02\n"); printf ("#define ARG_IMM16 0x03\n"); @@ -998,7 +1011,7 @@ gas () printf ("#define ARG_NIM4 0x0c\n"); printf ("#define ARG_DISP8 0x0c\n"); printf ("#define ARG_IMM4M1 0x0d\n"); - printf ("#define CLASS_MASK 0x1fff0\n"); + printf ("#define CLASS_X 0x10\n"); printf ("#define CLASS_BA 0x20\n"); printf ("#define CLASS_DA 0x30\n"); @@ -1018,9 +1031,10 @@ gas () printf ("#define CLASS_BIT 0x500\n"); printf ("#define CLASS_FLAGS 0x600\n"); printf ("#define CLASS_IR 0x700\n"); - printf ("#define CLASS_DISP8 0x800\n"); + printf ("#define CLASS_IRO 0x800\n"); + printf ("#define CLASS_DISP8 0x900\n"); - printf ("#define CLASS_BIT_1OR2 0x900\n"); + printf ("#define CLASS_BIT_1OR2 0xa00\n"); printf ("#define CLASS_REG 0x7000\n"); printf ("#define CLASS_REG_BYTE 0x2000\n"); printf ("#define CLASS_REG_WORD 0x3000\n"); @@ -1028,6 +1042,7 @@ gas () printf ("#define CLASS_REG_LONG 0x5000\n"); printf ("#define CLASS_REGN0 0x8000\n"); printf ("#define CLASS_PR 0x10000\n"); + printf ("#define CLASS_MASK 0x1fff0\n"); printf ("#define OPC_adc 0\n"); printf ("#define OPC_adcb 1\n"); @@ -1085,139 +1100,155 @@ gas () printf ("#define OPC_incb 53\n"); printf ("#define OPC_ind 54\n"); printf ("#define OPC_indb 55\n"); - printf ("#define OPC_inib 56\n"); - printf ("#define OPC_inibr 57\n"); - printf ("#define OPC_iret 58\n"); - printf ("#define OPC_jp 59\n"); - printf ("#define OPC_jr 60\n"); - printf ("#define OPC_ld 61\n"); - printf ("#define OPC_lda 62\n"); - printf ("#define OPC_ldar 63\n"); - printf ("#define OPC_ldb 64\n"); - printf ("#define OPC_ldctl 65\n"); - printf ("#define OPC_ldir 66\n"); - printf ("#define OPC_ldirb 67\n"); - printf ("#define OPC_ldk 68\n"); - printf ("#define OPC_ldl 69\n"); - printf ("#define OPC_ldm 70\n"); - printf ("#define OPC_ldps 71\n"); - printf ("#define OPC_ldr 72\n"); - printf ("#define OPC_ldrb 73\n"); - printf ("#define OPC_ldrl 74\n"); - printf ("#define OPC_mbit 75\n"); - printf ("#define OPC_mreq 76\n"); - printf ("#define OPC_mres 77\n"); - printf ("#define OPC_mset 78\n"); - printf ("#define OPC_mult 79\n"); - printf ("#define OPC_multl 80\n"); - printf ("#define OPC_neg 81\n"); - printf ("#define OPC_negb 82\n"); - printf ("#define OPC_nop 83\n"); - printf ("#define OPC_or 84\n"); - printf ("#define OPC_orb 85\n"); - printf ("#define OPC_out 86\n"); - printf ("#define OPC_outb 87\n"); - printf ("#define OPC_outd 88\n"); - printf ("#define OPC_outdb 89\n"); - printf ("#define OPC_outib 90\n"); - printf ("#define OPC_outibr 91\n"); - printf ("#define OPC_pop 92\n"); - printf ("#define OPC_popl 93\n"); - printf ("#define OPC_push 94\n"); - printf ("#define OPC_pushl 95\n"); - printf ("#define OPC_res 96\n"); - printf ("#define OPC_resb 97\n"); - printf ("#define OPC_resflg 98\n"); - printf ("#define OPC_ret 99\n"); - printf ("#define OPC_rl 100\n"); - printf ("#define OPC_rlb 101\n"); - printf ("#define OPC_rlc 102\n"); - printf ("#define OPC_rlcb 103\n"); - printf ("#define OPC_rldb 104\n"); - printf ("#define OPC_rr 105\n"); - printf ("#define OPC_rrb 106\n"); - printf ("#define OPC_rrc 107\n"); - printf ("#define OPC_rrcb 108\n"); - printf ("#define OPC_rrdb 109\n"); - printf ("#define OPC_sbc 110\n"); - printf ("#define OPC_sbcb 111\n"); - printf ("#define OPC_sda 112\n"); - printf ("#define OPC_sdab 113\n"); - printf ("#define OPC_sdal 114\n"); - printf ("#define OPC_sdl 115\n"); - printf ("#define OPC_sdlb 116\n"); - printf ("#define OPC_sdll 117\n"); - printf ("#define OPC_set 118\n"); - printf ("#define OPC_setb 119\n"); - printf ("#define OPC_setflg 120\n"); - printf ("#define OPC_sinb 121\n"); - printf ("#define OPC_sind 122\n"); - printf ("#define OPC_sindb 123\n"); - printf ("#define OPC_sinib 124\n"); - printf ("#define OPC_sinibr 125\n"); - printf ("#define OPC_sla 126\n"); - printf ("#define OPC_slab 127\n"); - printf ("#define OPC_slal 128\n"); - printf ("#define OPC_sll 129\n"); - printf ("#define OPC_sllb 130\n"); - printf ("#define OPC_slll 131\n"); - printf ("#define OPC_sout 132\n"); - printf ("#define OPC_soutb 133\n"); - printf ("#define OPC_soutd 134\n"); - printf ("#define OPC_soutdb 135\n"); - printf ("#define OPC_soutib 136\n"); - printf ("#define OPC_soutibr 137\n"); - printf ("#define OPC_sra 138\n"); - printf ("#define OPC_srab 139\n"); - printf ("#define OPC_sral 140\n"); - printf ("#define OPC_srl 141\n"); - printf ("#define OPC_srlb 142\n"); - printf ("#define OPC_srll 143\n"); - printf ("#define OPC_sub 144\n"); - printf ("#define OPC_subb 145\n"); - printf ("#define OPC_subl 146\n"); - printf ("#define OPC_tcc 147\n"); - printf ("#define OPC_tccb 148\n"); - printf ("#define OPC_test 149\n"); - printf ("#define OPC_testb 150\n"); - printf ("#define OPC_testl 151\n"); - printf ("#define OPC_trdb 152\n"); - printf ("#define OPC_trdrb 153\n"); - printf ("#define OPC_trib 154\n"); - printf ("#define OPC_trirb 155\n"); - printf ("#define OPC_trtdrb 156\n"); - printf ("#define OPC_trtib 157\n"); - printf ("#define OPC_trtirb 158\n"); - printf ("#define OPC_trtrb 159\n"); - printf ("#define OPC_tset 160\n"); - printf ("#define OPC_tsetb 161\n"); - printf ("#define OPC_xor 162\n"); - printf ("#define OPC_xorb 163\n"); - - printf ("#define OPC_ldd 164 \n"); - printf ("#define OPC_lddb 165 \n"); - printf ("#define OPC_lddr 166 \n"); - printf ("#define OPC_lddrb 167 \n"); - printf ("#define OPC_ldi 168 \n"); - printf ("#define OPC_ldib 169 \n"); - printf ("#define OPC_sc 170\n"); - printf ("#define OPC_bpt 171\n"); - printf ("#define OPC_ext0e 172\n"); - printf ("#define OPC_ext0f 172\n"); - printf ("#define OPC_ext8e 172\n"); - printf ("#define OPC_ext8f 172\n"); - printf ("#define OPC_rsvd36 172\n"); - printf ("#define OPC_rsvd38 172\n"); - printf ("#define OPC_rsvd78 172\n"); - printf ("#define OPC_rsvd7e 172\n"); - printf ("#define OPC_rsvd9d 172\n"); - printf ("#define OPC_rsvd9f 172\n"); - printf ("#define OPC_rsvdb9 172\n"); - printf ("#define OPC_rsvdbf 172\n"); - printf ("#define OPC_outi 173\n"); - printf ("#define OPC_ldctlb 174\n"); - printf ("#define OPC_sin 175\n"); - printf ("#define OPC_trtdb 176\n"); + printf ("#define OPC_indr 56\n"); + printf ("#define OPC_indrb 57\n"); + printf ("#define OPC_ini 58\n"); + printf ("#define OPC_inib 59\n"); + printf ("#define OPC_inir 60\n"); + printf ("#define OPC_inirb 61\n"); + printf ("#define OPC_iret 62\n"); + printf ("#define OPC_jp 63\n"); + printf ("#define OPC_jr 64\n"); + printf ("#define OPC_ld 65\n"); + printf ("#define OPC_lda 66\n"); + printf ("#define OPC_ldar 67\n"); + printf ("#define OPC_ldb 68\n"); + printf ("#define OPC_ldctl 69\n"); + printf ("#define OPC_ldir 70\n"); + printf ("#define OPC_ldirb 71\n"); + printf ("#define OPC_ldk 72\n"); + printf ("#define OPC_ldl 73\n"); + printf ("#define OPC_ldm 74\n"); + printf ("#define OPC_ldps 75\n"); + printf ("#define OPC_ldr 76\n"); + printf ("#define OPC_ldrb 77\n"); + printf ("#define OPC_ldrl 78\n"); + printf ("#define OPC_mbit 79\n"); + printf ("#define OPC_mreq 80\n"); + printf ("#define OPC_mres 81\n"); + printf ("#define OPC_mset 82\n"); + printf ("#define OPC_mult 83\n"); + printf ("#define OPC_multl 84\n"); + printf ("#define OPC_neg 85\n"); + printf ("#define OPC_negb 86\n"); + printf ("#define OPC_nop 87\n"); + printf ("#define OPC_or 88\n"); + printf ("#define OPC_orb 89\n"); + printf ("#define OPC_otdr 90\n"); + printf ("#define OPC_otdrb 91\n"); + printf ("#define OPC_otir 92\n"); + printf ("#define OPC_otirb 93\n"); + printf ("#define OPC_out 94\n"); + printf ("#define OPC_outb 95\n"); + printf ("#define OPC_outd 96\n"); + printf ("#define OPC_outdb 97\n"); + printf ("#define OPC_outi 98\n"); + printf ("#define OPC_outib 99\n"); + printf ("#define OPC_pop 100\n"); + printf ("#define OPC_popl 101\n"); + printf ("#define OPC_push 102\n"); + printf ("#define OPC_pushl 103\n"); + printf ("#define OPC_res 104\n"); + printf ("#define OPC_resb 105\n"); + printf ("#define OPC_resflg 106\n"); + printf ("#define OPC_ret 107\n"); + printf ("#define OPC_rl 108\n"); + printf ("#define OPC_rlb 109\n"); + printf ("#define OPC_rlc 110\n"); + printf ("#define OPC_rlcb 111\n"); + printf ("#define OPC_rldb 112\n"); + printf ("#define OPC_rr 113\n"); + printf ("#define OPC_rrb 114\n"); + printf ("#define OPC_rrc 115\n"); + printf ("#define OPC_rrcb 116\n"); + printf ("#define OPC_rrdb 117\n"); + printf ("#define OPC_sbc 118\n"); + printf ("#define OPC_sbcb 119\n"); + printf ("#define OPC_sda 120\n"); + printf ("#define OPC_sdab 121\n"); + printf ("#define OPC_sdal 122\n"); + printf ("#define OPC_sdl 123\n"); + printf ("#define OPC_sdlb 124\n"); + printf ("#define OPC_sdll 125\n"); + printf ("#define OPC_set 126\n"); + printf ("#define OPC_setb 127\n"); + printf ("#define OPC_setflg 128\n"); + printf ("#define OPC_sin 129\n"); + printf ("#define OPC_sinb 130\n"); + printf ("#define OPC_sind 131\n"); + printf ("#define OPC_sindb 132\n"); + printf ("#define OPC_sindr 133\n"); + printf ("#define OPC_sindrb 134\n"); + printf ("#define OPC_sini 135\n"); + printf ("#define OPC_sinib 136\n"); + printf ("#define OPC_sinir 137\n"); + printf ("#define OPC_sinirb 138\n"); + printf ("#define OPC_sla 139\n"); + printf ("#define OPC_slab 140\n"); + printf ("#define OPC_slal 141\n"); + printf ("#define OPC_sll 142\n"); + printf ("#define OPC_sllb 143\n"); + printf ("#define OPC_slll 144\n"); + printf ("#define OPC_sotdr 145\n"); + printf ("#define OPC_sotdrb 146\n"); + printf ("#define OPC_sotir 147\n"); + printf ("#define OPC_sotirb 148\n"); + printf ("#define OPC_sout 149\n"); + printf ("#define OPC_soutb 150\n"); + printf ("#define OPC_soutd 151\n"); + printf ("#define OPC_soutdb 152\n"); + printf ("#define OPC_souti 153\n"); + printf ("#define OPC_soutib 154\n"); + printf ("#define OPC_sra 155\n"); + printf ("#define OPC_srab 156\n"); + printf ("#define OPC_sral 157\n"); + printf ("#define OPC_srl 158\n"); + printf ("#define OPC_srlb 159\n"); + printf ("#define OPC_srll 160\n"); + printf ("#define OPC_sub 161\n"); + printf ("#define OPC_subb 162\n"); + printf ("#define OPC_subl 163\n"); + printf ("#define OPC_tcc 164\n"); + printf ("#define OPC_tccb 165\n"); + printf ("#define OPC_test 166\n"); + printf ("#define OPC_testb 167\n"); + printf ("#define OPC_testl 168\n"); + printf ("#define OPC_trdb 169\n"); + printf ("#define OPC_trdrb 170\n"); + printf ("#define OPC_trib 171\n"); + printf ("#define OPC_trirb 172\n"); + printf ("#define OPC_trtdrb 173\n"); + printf ("#define OPC_trtib 174\n"); + printf ("#define OPC_trtirb 175\n"); + printf ("#define OPC_trtrb 176\n"); + printf ("#define OPC_tset 177\n"); + printf ("#define OPC_tsetb 178\n"); + printf ("#define OPC_xor 179\n"); + printf ("#define OPC_xorb 180\n"); + + printf ("#define OPC_ldd 181\n"); + printf ("#define OPC_lddb 182\n"); + printf ("#define OPC_lddr 183\n"); + printf ("#define OPC_lddrb 184\n"); + printf ("#define OPC_ldi 185\n"); + printf ("#define OPC_ldib 186\n"); + printf ("#define OPC_sc 187\n"); + printf ("#define OPC_bpt 188\n"); + printf ("#define OPC_ext0e 188\n"); + printf ("#define OPC_ext0f 188\n"); + printf ("#define OPC_ext8e 188\n"); + printf ("#define OPC_ext8f 188\n"); + printf ("#define OPC_rsvd36 188\n"); + printf ("#define OPC_rsvd38 188\n"); + printf ("#define OPC_rsvd78 188\n"); + printf ("#define OPC_rsvd7e 188\n"); + printf ("#define OPC_rsvd9d 188\n"); + printf ("#define OPC_rsvd9f 188\n"); + printf ("#define OPC_rsvdb9 188\n"); + printf ("#define OPC_rsvdbf 188\n"); + printf ("#define OPC_ldctlb 189\n"); + printf ("#define OPC_trtdb 190\n"); + printf ("#define OPC_brk 191\n"); #if 0 for (i = 0; toks[i].token; i++) printf ("#define %s\t0x%x\n", toks[i].token, i * 16); @@ -1290,7 +1321,6 @@ gas () printf ("#endif\n"); } - int main (ac, av) int ac; @@ -1315,16 +1345,11 @@ main (ac, av) { gas (); } - else if (ac == 2 && strcmp (av[1], "-d") == 0) - { - /*dis();*/ - } else { printf ("Usage: %s -t\n", av[0]); - printf ("-t : generate new z8.c internal table\n"); + printf ("-t : generate new internal table\n"); printf ("-a : generate new table for gas\n"); - printf ("-d : generate new table for disassemble\n"); printf ("-h : generate new table for humans\n"); } return 0; |