This commit was manufactured by cvs2svn to create branch 'jimb-jimb-macro-020506-branchpoint

macro-020506-branch'.

Sprout from gdb_5_2-branch 2002-03-27 05:12:36 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.'
Cherrypick from gdb_5_2-branch 2002-03-02 23:00:05 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.':
    intl/ChangeLog
    intl/Makefile.in
Cherrypick from master 2002-05-06 21:00:21 UTC Jim Blandy <jimb@codesourcery.com> 'Separate the job of reading the line number info statement program':
    ChangeLog
    MAINTAINERS
    Makefile.in
    bfd/ChangeLog
    bfd/ChangeLog-9495
    bfd/Makefile.am
    bfd/Makefile.in
    bfd/aix5ppc-core.c
    bfd/aout-adobe.c
    bfd/aout-target.h
    bfd/aout-tic30.c
    bfd/aoutx.h
    bfd/archive.c
    bfd/archures.c
    bfd/bfd-in.h
    bfd/bfd-in2.h
    bfd/bfd.c
    bfd/binary.c
    bfd/bout.c
    bfd/coff-arm.c
    bfd/coff-h8300.c
    bfd/coff-mcore.c
    bfd/coff-ppc.c
    bfd/coff-rs6000.c
    bfd/coff-sh.c
    bfd/coff-z8k.c
    bfd/coff64-rs6000.c
    bfd/coffcode.h
    bfd/cofflink.c
    bfd/coffswap.h
    bfd/config.bfd
    bfd/configure
    bfd/configure.in
    bfd/cpu-h8300.c
    bfd/cpu-i370.c
    bfd/cpu-i386.c
    bfd/cpu-mips.c
    bfd/cpu-powerpc.c
    bfd/cpu-s390.c
    bfd/cpu-sh.c
    bfd/cpu-sparc.c
    bfd/dep-in.sed
    bfd/doc/ChangeLog
    bfd/doc/Makefile.in
    bfd/dwarf2.c
    bfd/ecoff.c
    bfd/elf-bfd.h
    bfd/elf-eh-frame.c
    bfd/elf-hppa.h
    bfd/elf-m10300.c
    bfd/elf.c
    bfd/elf32-arm.h
    bfd/elf32-cris.c
    bfd/elf32-hppa.c
    bfd/elf32-hppa.h
    bfd/elf32-i370.c
    bfd/elf32-i386.c
    bfd/elf32-m32r.c
    bfd/elf32-m68k.c
    bfd/elf32-mips.c
    bfd/elf32-ppc.c
    bfd/elf32-s390.c
    bfd/elf32-sh.c
    bfd/elf32-sh64.c
    bfd/elf32-sparc.c
    bfd/elf32-xstormy16.c
    bfd/elf64-alpha.c
    bfd/elf64-hppa.c
    bfd/elf64-mips.c
    bfd/elf64-mmix.c
    bfd/elf64-ppc.c
    bfd/elf64-ppc.h
    bfd/elf64-s390.c
    bfd/elf64-sh64.c
    bfd/elf64-sparc.c
    bfd/elf64-x86-64.c
    bfd/elfarm-nabi.c
    bfd/elflink.c
    bfd/elflink.h
    bfd/elfxx-ia64.c
    bfd/elfxx-mips.c
    bfd/elfxx-mips.h
    bfd/elfxx-target.h
    bfd/i386linux.c
    bfd/i386msdos.c
    bfd/i386os9k.c
    bfd/ieee.c
    bfd/ihex.c
    bfd/libbfd-in.h
    bfd/libbfd.c
    bfd/libbfd.h
    bfd/libcoff-in.h
    bfd/libcoff.h
    bfd/libecoff.h
    bfd/libxcoff.h
    bfd/linker.c
    bfd/m68klinux.c
    bfd/merge.c
    bfd/mmo.c
    bfd/nlm-target.h
    bfd/oasys.c
    bfd/opncls.c
    bfd/pdp11.c
    bfd/po/SRC-POTFILES.in
    bfd/po/fr.po
    bfd/ppcboot.c
    bfd/reloc.c
    bfd/rs6000-core.c
    bfd/som.c
    bfd/sparclinux.c
    bfd/srec.c
    bfd/sunos.c
    bfd/syms.c
    bfd/targets.c
    bfd/tekhex.c
    bfd/versados.c
    bfd/version.h
    bfd/vms.c
    bfd/xcofflink.c
    config.guess
    config.sub
    config/ChangeLog
    config/acinclude.m4
    config/mh-a68bsd
    config/mh-apollo68
    config/mh-cxux
    config/mh-decstation
    config/mh-dgux
    config/mh-dgux386
    config/mh-djgpp
    config/mh-hp300
    config/mh-hpux
    config/mh-hpux8
    config/mh-interix
    config/mh-irix5
    config/mh-irix6
    config/mh-lynxrs6k
    config/mh-mingw32
    config/mh-ncr3000
    config/mh-ncrsvr43
    config/mh-necv4
    config/mh-openedition
    config/mh-riscos
    config/mh-sco
    config/mh-solaris
    config/mh-sysv
    config/mh-sysv4
    config/mh-sysv5
    config/mt-aix43
    config/mt-alphaieee
    config/mt-linux
    configure
    configure.in
    gdb/ChangeLog
    gdb/MAINTAINERS
    gdb/Makefile.in
    gdb/NEWS
    gdb/PROBLEMS
    gdb/README
    gdb/acconfig.h
    gdb/acinclude.m4
    gdb/aclocal.m4
    gdb/alpha-linux-tdep.c
    gdb/alpha-nat.c
    gdb/alpha-osf1-tdep.c
    gdb/alpha-tdep.c
    gdb/alpha-tdep.h
    gdb/alphabsd-nat.c
    gdb/alphafbsd-tdep.c
    gdb/alphanbsd-nat.c
    gdb/alphanbsd-tdep.c
    gdb/arc-tdep.c
    gdb/arch-utils.c
    gdb/arch-utils.h
    gdb/arm-tdep.c
    gdb/arm-tdep.h
    gdb/avr-tdep.c
    gdb/bcache.c
    gdb/blockframe.c
    gdb/breakpoint.c
    gdb/builtin-regs.c
    gdb/builtin-regs.h
    gdb/c-exp.y
    gdb/c-lang.c
    gdb/cli-out.c
    gdb/cli/cli-cmds.c
    gdb/cli/cli-decode.c
    gdb/cli/cli-decode.h
    gdb/cli/cli-dump.c
    gdb/cli/cli-dump.h
    gdb/cli/cli-script.c
    gdb/coffread.c
    gdb/command.h
    gdb/completer.c
    gdb/config.in
    gdb/config/alpha/alpha-linux.mt
    gdb/config/alpha/alpha-osf1.mt
    gdb/config/alpha/nbsd.mh
    gdb/config/alpha/nbsd.mt
    gdb/config/alpha/nm-linux.h
    gdb/config/alpha/nm-nbsd.h
    gdb/config/alpha/nm-osf.h
    gdb/config/alpha/tm-alpha.h
    gdb/config/alpha/tm-alphalinux.h
    gdb/config/alpha/tm-fbsd.h
    gdb/config/alpha/tm-nbsd.h
    gdb/config/arc/tm-arc.h
    gdb/config/avr/avr.mt
    gdb/config/djgpp/README
    gdb/config/h8500/tm-h8500.h
    gdb/config/i386/fbsd.mh
    gdb/config/i386/i386gnu.mh
    gdb/config/i386/i386lynx.mh
    gdb/config/i386/i386v42mp.mh
    gdb/config/i386/nbsd.mt
    gdb/config/i386/nbsdelf.mt
    gdb/config/i386/nm-fbsd.h
    gdb/config/i386/nm-x86-64.h
    gdb/config/i386/tm-linux.h
    gdb/config/i386/x86-64linux.mt
    gdb/config/i960/tm-i960.h
    gdb/config/m32r/m32r.mt
    gdb/config/m68k/m68klynx.mh
    gdb/config/m68k/nbsd.mt
    gdb/config/m68k/sun3os4.mh
    gdb/config/m68k/tm-nbsd.h
    gdb/config/mcore/tm-mcore.h
    gdb/config/mips/vr5000.mt
    gdb/config/mn10200/tm-mn10200.h
    gdb/config/ns32k/nbsd.mt
    gdb/config/pa/hppabsd.mh
    gdb/config/pa/hppaosf.mh
    gdb/config/pa/hpux1020.mh
    gdb/config/pa/hpux11.mh
    gdb/config/pa/hpux11w.mh
    gdb/config/pa/tm-hppa.h
    gdb/config/powerpc/nbsd.mt
    gdb/config/powerpc/tm-ppc-eabi.h
    gdb/config/rs6000/rs6000lynx.mh
    gdb/config/rs6000/tm-rs6000.h
    gdb/config/s390/s390.mh
    gdb/config/s390/s390.mt
    gdb/config/s390/s390x.mt
    gdb/config/sparc/fbsd.mh
    gdb/config/sparc/fbsd.mt
    gdb/config/sparc/linux.mh
    gdb/config/sparc/sparclynx.mh
    gdb/config/sparc/sun4os4.mh
    gdb/config/sparc/tm-linux.h
    gdb/config/sparc/tm-sp64.h
    gdb/config/sparc/tm-sp64linux.h
    gdb/config/sparc/tm-sparc.h
    gdb/config/v850/tm-v850.h
    gdb/config/vax/tm-vax.h
    gdb/configure
    gdb/configure.host
    gdb/configure.in
    gdb/configure.tgt
    gdb/core-sol2.c
    gdb/corefile.c
    gdb/corelow.c
    gdb/cp-valprint.c
    gdb/cris-tdep.c
    gdb/d10v-tdep.c
    gdb/d30v-tdep.c
    gdb/dbxread.c
    gdb/defs.h
    gdb/doc/ChangeLog
    gdb/doc/gdb.texinfo
    gdb/doc/gdbint.texinfo
    gdb/dwarf2cfi.c
    gdb/dwarf2read.c
    gdb/elfread.c
    gdb/eval.c
    gdb/event-top.c
    gdb/exec.c
    gdb/f-exp.y
    gdb/f-lang.c
    gdb/fbsd-proc.c
    gdb/findvar.c
    gdb/frame.c
    gdb/frame.h
    gdb/gcore.c
    gdb/gdb-events.c
    gdb/gdb-events.h
    gdb/gdb-events.sh
    gdb/gdbarch.c
    gdb/gdbarch.h
    gdb/gdbarch.sh
    gdb/gdbserver/Makefile.in
    gdb/gdbserver/config.in
    gdb/gdbserver/configure
    gdb/gdbserver/configure.in
    gdb/gdbserver/gdbreplay.c
    gdb/gdbserver/inferiors.c
    gdb/gdbserver/linux-arm-low.c
    gdb/gdbserver/linux-i386-low.c
    gdb/gdbserver/linux-ia64-low.c
    gdb/gdbserver/linux-low.c
    gdb/gdbserver/linux-low.h
    gdb/gdbserver/linux-m68k-low.c
    gdb/gdbserver/linux-mips-low.c
    gdb/gdbserver/linux-ppc-low.c
    gdb/gdbserver/linux-s390-low.c
    gdb/gdbserver/linux-sh-low.c
    gdb/gdbserver/linux-x86-64-low.c
    gdb/gdbserver/mem-break.c
    gdb/gdbserver/mem-break.h
    gdb/gdbserver/regcache.c
    gdb/gdbserver/regcache.h
    gdb/gdbserver/remote-utils.c
    gdb/gdbserver/server.c
    gdb/gdbserver/server.h
    gdb/gdbserver/target.c
    gdb/gdbserver/target.h
    gdb/gdbserver/utils.c
    gdb/gdbtypes.c
    gdb/gdbtypes.h
    gdb/gnu-nat.c
    gdb/gnu-v3-abi.c
    gdb/go32-nat.c
    gdb/gregset.h
    gdb/h8300-tdep.c
    gdb/h8500-tdep.c
    gdb/hppa-tdep.c
    gdb/hpread.c
    gdb/i386-linux-tdep.c
    gdb/i386-tdep.c
    gdb/i386gnu-nat.c
    gdb/i387-nat.c
    gdb/i960-tdep.c
    gdb/ia64-tdep.c
    gdb/infcmd.c
    gdb/inferior.h
    gdb/inflow.c
    gdb/infrun.c
    gdb/jv-exp.y
    gdb/kod.c
    gdb/language.c
    gdb/lin-lwp.c
    gdb/linespec.c
    gdb/linux-proc.c
    gdb/m2-exp.y
    gdb/m3-nat.c
    gdb/m68hc11-tdep.c
    gdb/m68klinux-nat.c
    gdb/maint.c
    gdb/mcore-tdep.c
    gdb/mdebugread.c
    gdb/mem-break.c
    gdb/mi/ChangeLog
    gdb/mi/mi-cmd-break.c
    gdb/mi/mi-cmd-disas.c
    gdb/mi/mi-cmd-stack.c
    gdb/mi/mi-cmd-var.c
    gdb/mi/mi-console.c
    gdb/mi/mi-main.c
    gdb/mi/mi-out.c
    gdb/mi/mi-parse.c
    gdb/minsyms.c
    gdb/mips-tdep.c
    gdb/mipsread.c
    gdb/mn10300-tdep.c
    gdb/monitor.c
    gdb/ocd.c
    gdb/p-exp.y
    gdb/p-lang.c
    gdb/p-lang.h
    gdb/p-typeprint.c
    gdb/p-valprint.c
    gdb/parse.c
    gdb/parser-defs.h
    gdb/ppc-bdm.c
    gdb/ppc-linux-nat.c
    gdb/ppc-linux-tdep.c
    gdb/ppc-tdep.h
    gdb/printcmd.c
    gdb/proc-api.c
    gdb/regcache.c
    gdb/regformats/reg-ppc.dat
    gdb/regformats/reg-x86-64.dat
    gdb/remote-array.c
    gdb/remote-e7000.c
    gdb/remote-es.c
    gdb/remote-mips.c
    gdb/remote-os9k.c
    gdb/remote-rdi.c
    gdb/remote-rdp.c
    gdb/remote-st.c
    gdb/remote-utils.c
    gdb/remote-vxsparc.c
    gdb/remote.c
    gdb/rs6000-nat.c
    gdb/rs6000-tdep.c
    gdb/s390-tdep.c
    gdb/scm-lang.c
    gdb/ser-unix.h
    gdb/serial.c
    gdb/sh-tdep.c
    gdb/solib-legacy.c
    gdb/solib-svr4.c
    gdb/solib.c
    gdb/somread.c
    gdb/source.c
    gdb/sparc-nat.c
    gdb/sparc-tdep.c
    gdb/stabsread.c
    gdb/stack.c
    gdb/std-regs.c
    gdb/symfile.c
    gdb/symfile.h
    gdb/symmisc.c
    gdb/symtab.c
    gdb/symtab.h
    gdb/target.c
    gdb/target.h
    gdb/testsuite/ChangeLog
    gdb/testsuite/config/sid.exp
    gdb/testsuite/gdb.asm/Makefile.in
    gdb/testsuite/gdb.asm/asm-source.exp
    gdb/testsuite/gdb.asm/configure
    gdb/testsuite/gdb.asm/configure.in
    gdb/testsuite/gdb.asm/powerpc.inc
    gdb/testsuite/gdb.asm/sparc64.inc
    gdb/testsuite/gdb.base/annota1.exp
    gdb/testsuite/gdb.base/attach.exp
    gdb/testsuite/gdb.base/bar.c
    gdb/testsuite/gdb.base/baz.c
    gdb/testsuite/gdb.base/completion.exp
    gdb/testsuite/gdb.base/cvexpr.c
    gdb/testsuite/gdb.base/dbx.exp
    gdb/testsuite/gdb.base/default.exp
    gdb/testsuite/gdb.base/dump.c
    gdb/testsuite/gdb.base/dump.exp
    gdb/testsuite/gdb.base/ending-run.exp
    gdb/testsuite/gdb.base/foo.c
    gdb/testsuite/gdb.base/funcargs.c
    gdb/testsuite/gdb.base/funcargs.exp
    gdb/testsuite/gdb.base/gcore.exp
    gdb/testsuite/gdb.base/grbx.c
    gdb/testsuite/gdb.base/help.exp
    gdb/testsuite/gdb.base/list.exp
    gdb/testsuite/gdb.base/long_long.exp
    gdb/testsuite/gdb.base/maint.exp
    gdb/testsuite/gdb.base/opaque.exp
    gdb/testsuite/gdb.base/overlays.exp
    gdb/testsuite/gdb.base/ovlymgr.c
    gdb/testsuite/gdb.base/printcmds.exp
    gdb/testsuite/gdb.base/ptype.exp
    gdb/testsuite/gdb.base/relocate.c
    gdb/testsuite/gdb.base/relocate.exp
    gdb/testsuite/gdb.base/scope.exp
    gdb/testsuite/gdb.base/shlib-call.exp
    gdb/testsuite/gdb.base/step-test.exp
    gdb/testsuite/gdb.base/watchpoint.exp
    gdb/testsuite/gdb.base/whatis.exp
    gdb/testsuite/gdb.c++/classes.exp
    gdb/testsuite/gdb.c++/cplusfuncs.exp
    gdb/testsuite/gdb.c++/hang.H
    gdb/testsuite/gdb.c++/hang.exp
    gdb/testsuite/gdb.c++/hang1.C
    gdb/testsuite/gdb.c++/hang2.C
    gdb/testsuite/gdb.c++/hang3.C
    gdb/testsuite/gdb.c++/local.cc
    gdb/testsuite/gdb.c++/local.exp
    gdb/testsuite/gdb.c++/method.exp
    gdb/testsuite/gdb.c++/misc.exp
    gdb/testsuite/gdb.c++/ovldbreak.exp
    gdb/testsuite/gdb.gdb/xfullpath.exp
    gdb/testsuite/gdb.java/jmisc1.exp
    gdb/testsuite/gdb.java/jmisc2.exp
    gdb/testsuite/gdb.mi/ChangeLog
    gdb/testsuite/gdb.mi/mi-var-cmd.exp
    gdb/testsuite/gdb.mi/mi0-var-cmd.exp
    gdb/testsuite/gdb.threads/linux-dp.exp
    gdb/testsuite/gdb.trace/gdb_c_test.c
    gdb/testsuite/lib/gdb.exp
    gdb/thread-db.c
    gdb/thread.c
    gdb/top.c
    gdb/top.h
    gdb/tracepoint.c
    gdb/tui/ChangeLog
    gdb/tui/tui-out.c
    gdb/ui-file.c
    gdb/ui-out.c
    gdb/utils.c
    gdb/valarith.c
    gdb/valops.c
    gdb/valprint.c
    gdb/value.h
    gdb/varobj.c
    gdb/vax-tdep.c
    gdb/vax-tdep.h
    gdb/version.in
    gdb/win32-nat.c
    gdb/x86-64-linux-nat.c
    gdb/x86-64-tdep.c
    gdb/x86-64-tdep.h
    gdb/xcoffread.c
    gdb/xstormy16-tdep.c
    gdb/z8k-tdep.c
    include/ChangeLog
    include/coff/ChangeLog
    include/coff/rs6k64.h
    include/dyn-string.h
    include/elf/ChangeLog
    include/elf/dwarf2.h
    include/floatformat.h
    include/opcode/ChangeLog
    include/opcode/i386.h
    include/opcode/mips.h
    include/opcode/pdp11.h
    include/xregex2.h
    libiberty/ChangeLog
    libiberty/Makefile.in
    libiberty/config.table
    libiberty/configure
    libiberty/configure.in
    libiberty/cp-demangle.c
    libiberty/dyn-string.c
    libiberty/floatformat.c
    libiberty/functions.texi
    libiberty/hashtab.c
    libiberty/hex.c
    libiberty/splay-tree.c
    libiberty/strtod.c
    libiberty/xatexit.c
    libiberty/xmalloc.c
    ltmain.sh
    mmalloc/ChangeLog
    mmalloc/mmap-sup.c
    opcodes/ChangeLog
    opcodes/Makefile.am
    opcodes/Makefile.in
    opcodes/configure
    opcodes/configure.in
    opcodes/dep-in.sed
    opcodes/i386-dis.c
    opcodes/mips-dis.c
    opcodes/mips-opc.c
    opcodes/pdp11-dis.c
    opcodes/pdp11-opc.c
    opcodes/po/fr.po
    opcodes/po/id.po
    opcodes/ppc-opc.c
    opcodes/s390-dis.c
    opcodes/z8k-dis.c
    opcodes/z8k-opc.h
    opcodes/z8kgen.c
    sim/ChangeLog
    sim/MAINTAINERS
    sim/arm/ChangeLog
    sim/arm/wrapper.c
    sim/common/ChangeLog
    sim/common/callback.c
    sim/igen/ChangeLog
    sim/igen/gen.c
    sim/igen/igen.c
    sim/m68hc11/ChangeLog
    sim/m68hc11/dv-m68hc11.c
    sim/m68hc11/dv-m68hc11spi.c
    sim/m68hc11/dv-m68hc11tim.c
    sim/m68hc11/interp.c
    sim/m68hc11/interrupts.c
    sim/m68hc11/interrupts.h
    sim/m68hc11/m68hc11_sim.c
    sim/m68hc11/sim-main.h
    sim/mips/ChangeLog
    sim/mips/Makefile.in
    sim/mips/configure
    sim/mips/configure.in
    sim/mips/cp1.c
    sim/mips/interp.c
    sim/mips/mips.igen
    sim/mips/sim-main.h
    sim/ppc/ChangeLog
    sim/ppc/hw_disk.c
    sim/ppc/ppc-instructions
    sim/ppc/sim_calls.c
    sim/z8k/ChangeLog
    sim/z8k/writecode.c
Delete:
    config/mh-irix4
    config/mh-lynxos
    config/mh-sun3
    config/mh-vaxult2
    config/mt-armpic
    config/mt-elfalphapic
    config/mt-i370pic
    config/mt-ia64pic
    config/mt-m68kpic
    config/mt-papic
    config/mt-ppcpic
    config/mt-s390pic
    config/mt-sparcpic
    config/mt-x86pic
    gdb/a29k-tdep.c
    gdb/config/a29k/a29k-udi.mt
    gdb/config/a29k/a29k.mt
    gdb/config/a29k/tm-a29k.h
    gdb/config/a29k/tm-vx29k.h
    gdb/config/a29k/vx29k.mt
    gdb/remote-adapt.c
    gdb/remote-eb.c
    gdb/remote-mm.c
    gdb/remote-udi.c
    gdb/signals.c
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthbasic.c
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthbasic.exp
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthcore.c
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthcore.exp
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthfork.c
    gdb/testsuite/gdb.hp/gdb.threads-hp/usrthfork.exp

18 files changed, 1067 insertions, 342 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a7b5e13..80f094c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,141 @@
+2002-05-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke.
+
+2002-04-24  Christian Groessler <chris@groessler.org>
+
+	* z8k-dis.c (print_insn_z8k): Set disassemble_info to 2
+	bytes_per_chunk, 6 bytes_per_line for nicer display of the hex
+	codes.
+	(z8k_lookup_instr): CLASS_IGNORE case added.
+	(output_instr): Don't print hex codes, they are already
+	printed.
+	(unpack_instr): ARG_NIM4 case added.  ARG_NIM8 case
+	fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases.
+	(unparse_instr): Fix base and indexed addressing disassembly:
+	The index is inside the brackets.
+	* z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines.
+	(opt): Fix shift left/right arithmetic/logical byte defines:
+	The high byte of the immediate word is ignored by the
+	processor.
+	Fix n parameter of ldm opcodes: The opcode contains (n-1).
+	(args): Fix "n" entry.
+	(toks): Add "nim4" and "iiii" entries.
+	* z8k-opc.h: Regenerated with new z8kgen.c.
+
+2002-04-24  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/id.po: New Indonesian translation.
+	* configure.in (ALL_LIGUAS): Add id.po
+	* configure: Regenerate.
+
+2002-04-17  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (powerpc_opcode): Fix dssall operand list.
+
+2002-04-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* dep-in.sed: Cope with absolute paths.
+	* Makefile.am (dep.sed): Subst TOPDIR.
+	Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* ppc-opc.c: Whitespace.
+	* s390-dis.c: Fix copyright date.
+
+2002-03-23  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (vmaddfp): Fix operand order.
+
+2002-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2002-03-21  Anton Blanchard  <anton@samba.org>
+
+	* ppc-opc.c: Add optional field to mtmsrd.
+	(MTMSRD_L, XRLARB_MASK): Define.
+
+Mon Mar 18 21:10:43 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (prefix_name): Fix handling of 32bit address prefix
+	in 64bit mode.
+	(print_insn) Likewise.
+	(putop): Fix handling of 'E'
+	(OP_E, OP_OFF): handle 32bit addressing mode in 64bit.
+	(ptr_reg): Likewise.
+
+2002-03-18  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/fr.po: Updated version.
+
+2002-03-16  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (M3D): Tweak comment.
+	(mips_builtin_op): Add comment indicating that opcodes of the
+	same name must be placed together in the table, and sort
+	the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt",
+	"rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name.
+
+2002-03-16  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* Makefile.am: Tidy up sh64 rules.
+        * Makefile.in: Regenerate.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c: Update copyright years.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
+	bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64.  Add
+	comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
+	indicate that they should dissassemble all applicable
+	MIPS-specified ASEs.
+	* mips-opc.c: Add support for MIPS-3D instructions.
+	(M3D): New definition.
+
+	* mips-opc.c: Update copyright years.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name.
+
+2002-03-15  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (is_newabi): Fix ABI decoding.
+
+2002-03-14  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32
+	and bfd_mach_mipsisa64 cases to match the rest.
+
+2002-03-13  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/fr.po: Updated version.
+
+2002-03-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Add optional `L' field to tlbie.
+	(XRTLRA_MASK): Define.
+
+2002-03-06  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Mark "pref" as being
+	present on I4.
+
+	* mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps".
+
+2002-03-05  Paul Koning  <pkoning@equallogic.com>
+
+	* pdp11-opc.c: Fix "mark" operand type.  Fix operand types
+	for float opcodes that take float operands.  Add alternate
+	names (xxxD vs. xxxF) for float opcodes.
+	* pdp11-dis.c (print_operand): Clean up formatting for mode 67.
+	(print_foperand): New function to handle float opcode operands.
+	(print_insn_pdp11): Use print_foperand to disassemble float ops.
+
 2002-02-27  Nick Clifton  <nickc@cambridge.redhat.com>
 
 	* po/de.po: Updated.
@@ -786,7 +924,7 @@
 	* arc-opc.c: Include "sysdep.h" to get stdio.h as include file.
 	* arc-ext.c: Likewise.
 
-2001-08-28  matthew gren  <mrg@redhat.com>
+2001-08-28  matthew green  <mrg@redhat.com>
 
 	* ppc-opc.c (icbt): Order correctly.
 
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 00edf82..ad3bdf4 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -24,14 +24,14 @@ HFILES = \
 	arm-opc.h \
 	fr30-desc.h fr30-opc.h \
 	h8500-opc.h \
+	ia64-asmtab.h \
+	ia64-opc.h \
 	m32r-desc.h m32r-opc.h \
 	mcore-opc.h \
 	openrisc-desc.h openrisc-opc.h \
 	sh-opc.h \
+	sh64-opc.h \
 	sysdep.h \
-	ia64-asmtab.h \
-	ia64-opc.h \
-	  sh64-opc.h \
 	w65-opc.h \
 	xstormy16-desc.h xstormy16-opc.h \
 	z8k-opc.h
@@ -119,6 +119,8 @@ CFILES = \
 	s390-opc.c \
 	s390-dis.c \
 	sh-dis.c \
+	sh64-dis.c \
+	sh64-opc.c \
 	sparc-dis.c \
 	sparc-opc.c \
 	tic30-dis.c \
@@ -129,8 +131,6 @@ CFILES = \
 	v850-dis.c \
 	v850-opc.c \
 	vax-dis.c \
-	  sh64-dis.c \
-	  sh64-opc.c \
 	w65-dis.c \
 	xstormy16-asm.c \
 	xstormy16-desc.c \
@@ -211,6 +211,8 @@ ALL_MACHINES = \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
+	sh64-dis.lo \
+	sh64-opc.lo \
 	sparc-dis.lo \
 	sparc-opc.lo \
 	tic30-dis.lo \
@@ -221,8 +223,6 @@ ALL_MACHINES = \
 	v850-dis.lo \
 	v850-opc.lo \
 	vax-dis.lo \
-	  sh64-dis.lo \
-	  sh64-opc.lo \
 	w65-dis.lo \
 	xstormy16-asm.lo \
 	xstormy16-desc.lo \
@@ -325,10 +325,6 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-
 stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
 	$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
 
-sh64-opc.lo: sh64-opc.c sh64-opc.h
-sh64-dis.lo: sh64-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  sh64-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
-
 $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
 	@true
 stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
@@ -380,7 +376,8 @@ dep.sed: dep-in.sed config.status
 		-e 's!@BFD_H@!$(BFD_H)!'	\
 		-e 's!@INCDIR@!$(INCDIR)!'	\
 		-e 's!@BFDDIR@!$(BFDDIR)!'	\
-		-e 's!@SRCDIR@!$(srcdir)!'
+		-e 's!@SRCDIR@!$(srcdir)!'	\
+		-e 's!@TOPDIR@!'`echo $(srcdir) | sed -e s,/opcodes$$,,`'!'
 
 dep: DEP
 	sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile
@@ -410,11 +407,11 @@ alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \
   opintl.h
-arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
-  opintl.h arc-dis.h arc-ext.h
+arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
+  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/arc.h
 arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
@@ -492,19 +489,25 @@ i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h
-ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \
-  ia64-asmtab.c
+  $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \
-  $(INCDIR)/opcode/ia64.h ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c \
-  ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
+  $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \
+  ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \
+  ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
 ia64-asmtab.lo: ia64-asmtab.c
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
@@ -532,7 +535,7 @@ m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h
 m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \
-  opintl.h $(INCDIR)/opcode/m68k.h
+  $(INCDIR)/libiberty.h opintl.h $(INCDIR)/opcode/m68k.h
 m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68k.h
 m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
@@ -608,6 +611,12 @@ s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
   $(INCDIR)/opcode/s390.h
 sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
+  sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h
+sh64-opc.lo: sh64-opc.c sh64-opc.h
 sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h
@@ -633,12 +642,6 @@ v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/symcat.h
-sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h
-sh64-opc.lo: sh64-opc.c sh64-opc.h
 w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 824e9aa..48c8630 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -134,14 +134,14 @@ HFILES = \
 	arm-opc.h \
 	fr30-desc.h fr30-opc.h \
 	h8500-opc.h \
+	ia64-asmtab.h \
+	ia64-opc.h \
 	m32r-desc.h m32r-opc.h \
 	mcore-opc.h \
 	openrisc-desc.h openrisc-opc.h \
 	sh-opc.h \
+	sh64-opc.h \
 	sysdep.h \
-	ia64-asmtab.h \
-	ia64-opc.h \
-	  sh64-opc.h \
 	w65-opc.h \
 	xstormy16-desc.h xstormy16-opc.h \
 	z8k-opc.h
@@ -230,6 +230,8 @@ CFILES = \
 	s390-opc.c \
 	s390-dis.c \
 	sh-dis.c \
+	sh64-dis.c \
+	sh64-opc.c \
 	sparc-dis.c \
 	sparc-opc.c \
 	tic30-dis.c \
@@ -240,8 +242,6 @@ CFILES = \
 	v850-dis.c \
 	v850-opc.c \
 	vax-dis.c \
-	  sh64-dis.c \
-	  sh64-opc.c \
 	w65-dis.c \
 	xstormy16-asm.c \
 	xstormy16-desc.c \
@@ -323,6 +323,8 @@ ALL_MACHINES = \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
+	sh64-dis.lo \
+	sh64-opc.lo \
 	sparc-dis.lo \
 	sparc-opc.lo \
 	tic30-dis.lo \
@@ -333,8 +335,6 @@ ALL_MACHINES = \
 	v850-dis.lo \
 	v850-opc.lo \
 	vax-dis.lo \
-	  sh64-dis.lo \
-	  sh64-opc.lo \
 	w65-dis.lo \
 	xstormy16-asm.lo \
 	xstormy16-desc.lo \
@@ -416,7 +416,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
 
 DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
 
-TAR = gtar
+TAR = tar
 GZIP_ENV = --best
 SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
 OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
@@ -836,10 +836,6 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-
 stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
 	$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
 
-sh64-opc.lo: sh64-opc.c sh64-opc.h
-sh64-dis.lo: sh64-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  sh64-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
-
 $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
 	@true
 stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
@@ -891,7 +887,8 @@ dep.sed: dep-in.sed config.status
 		-e 's!@BFD_H@!$(BFD_H)!'	\
 		-e 's!@INCDIR@!$(INCDIR)!'	\
 		-e 's!@BFDDIR@!$(BFDDIR)!'	\
-		-e 's!@SRCDIR@!$(srcdir)!'
+		-e 's!@SRCDIR@!$(srcdir)!'	\
+		-e 's!@TOPDIR@!'`echo $(srcdir) | sed -e s,/opcodes$$,,`'!'
 
 dep: DEP
 	sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile
@@ -921,11 +918,11 @@ alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \
   opintl.h
-arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
-  opintl.h arc-dis.h arc-ext.h
+arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
+  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/arc.h
 arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
@@ -1003,19 +1000,25 @@ i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h
-ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h
-ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \
-  ia64-asmtab.c
+  $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \
-  $(INCDIR)/opcode/ia64.h ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c \
-  ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
+  $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \
+  ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \
+  ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
 ia64-asmtab.lo: ia64-asmtab.c
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
@@ -1043,7 +1046,7 @@ m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h
 m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \
-  opintl.h $(INCDIR)/opcode/m68k.h
+  $(INCDIR)/libiberty.h opintl.h $(INCDIR)/opcode/m68k.h
 m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68k.h
 m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
@@ -1119,6 +1122,12 @@ s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
   $(INCDIR)/opcode/s390.h
 sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
+  sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h
+sh64-opc.lo: sh64-opc.c sh64-opc.h
 sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h
@@ -1144,12 +1153,6 @@ v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/symcat.h
-sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h
-sh64-opc.lo: sh64-opc.c sh64-opc.h
 w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \
diff --git a/opcodes/configure b/opcodes/configure
index 2e978ad..d8f162a 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -2588,7 +2588,7 @@ else
 fi
 
 
-ALL_LINGUAS="fr sv tr es da de"
+ALL_LINGUAS="fr sv tr es da de id"
 echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
 echo "configure:2594: checking how to run the C preprocessor" >&5
 # On Suns, sometimes $CPP names a directory.
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 0088fe9..699f9be 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -77,7 +77,7 @@ AC_EXEEXT
 
 AC_PROG_CC
 
-ALL_LINGUAS="fr sv tr es da de"
+ALL_LINGUAS="fr sv tr es da de id"
 CY_GNU_GETTEXT
 
 . ${srcdir}/../bfd/configure.host
diff --git a/opcodes/dep-in.sed b/opcodes/dep-in.sed
index c30dee56..e373d4c 100644
--- a/opcodes/dep-in.sed
+++ b/opcodes/dep-in.sed
@@ -6,7 +6,9 @@ t loop
 s!\.o:!.lo:!
 s! @BFD_H@! $(BFD_H)!g
 s!@INCDIR@!$(INCDIR)!g
+s!@TOPDIR@/include!$(INCDIR)!g
 s!@BFDDIR@!$(BFDDIR)!g
+s!@TOPDIR@/bfd!$(BFDDIR)!g
 s!@SRCDIR@/!!g
 
 s/\\\n */ /g
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 7b4b858..d2271d8 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1807,7 +1807,10 @@ prefix_name (pref, sizeflag)
     case 0x66:
       return (sizeflag & DFLAG) ? "data16" : "data32";
     case 0x67:
-      return (sizeflag & AFLAG) ? "addr16" : "addr32";
+      if (mode_64bit)
+        return (sizeflag & AFLAG) ? "addr32" : "addr64";
+      else
+        return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32";
     case FWAIT_OPCODE:
       return "fwait";
     default:
@@ -2081,7 +2084,7 @@ print_insn (pc, info)
       sizeflag ^= AFLAG;
       if (dp->bytemode3 != loop_jcxz_mode || intel_syntax)
 	{
-	  if (sizeflag & AFLAG)
+	  if ((sizeflag & AFLAG) || mode_64bit)
 	    oappend ("addr32 ");
 	  else
 	    oappend ("addr16 ");
@@ -2626,8 +2629,16 @@ putop (template, sizeflag)
 	    *obufp++ = 'b';
 	  break;
 	case 'E':		/* For jcxz/jecxz */
-	  if (sizeflag & AFLAG)
-	    *obufp++ = 'e';
+	  if (mode_64bit)
+	    {
+	      if (sizeflag & AFLAG)
+		*obufp++ = 'r';
+	      else
+		*obufp++ = 'e';
+	    }
+	  else
+	    if (sizeflag & AFLAG)
+	      *obufp++ = 'e';
 	  used_prefixes |= (prefixes & PREFIX_ADDR);
 	  break;
 	case 'F':
@@ -2636,9 +2647,9 @@ putop (template, sizeflag)
 	  if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
 	    {
 	      if (sizeflag & AFLAG)
-		*obufp++ = 'l';
+		*obufp++ = mode_64bit ? 'q' : 'l';
 	      else
-		*obufp++ = 'w';
+		*obufp++ = mode_64bit ? 'l' : 'w';
 	      used_prefixes |= (prefixes & PREFIX_ADDR);
 	    }
 	  break;
@@ -3014,7 +3025,7 @@ OP_E (bytemode, sizeflag)
   disp = 0;
   append_seg ();
 
-  if (sizeflag & AFLAG) /* 32 bit address mode */
+  if ((sizeflag & AFLAG) || mode_64bit) /* 32 bit address mode */
     {
       int havesib;
       int havebase;
@@ -3048,7 +3059,7 @@ OP_E (bytemode, sizeflag)
 	  if ((base & 7) == 5)
 	    {
 	      havebase = 0;
-	      if (mode_64bit && !havesib)
+	      if (mode_64bit && !havesib && (sizeflag & AFLAG))
 		riprel = 1;
 	      disp = get32s ();
 	    }
@@ -3115,7 +3126,8 @@ OP_E (bytemode, sizeflag)
 	  if (!havesib && (rex & REX_EXTZ))
 	    base += 8;
 	  if (havebase)
-	    oappend (mode_64bit ? names64[base] : names32[base]);
+	    oappend (mode_64bit && (sizeflag & AFLAG)
+		     ? names64[base] : names32[base]);
 	  if (havesib)
 	    {
 	      if (index != 4)
@@ -3128,11 +3140,13 @@ OP_E (bytemode, sizeflag)
                           *obufp = '\0';
                         }
                       sprintf (scratchbuf, "%s",
-			       mode_64bit ? names64[index] : names32[index]);
+			       mode_64bit && (sizeflag & AFLAG)
+			       ? names64[index] : names32[index]);
                     }
                   else
 		    sprintf (scratchbuf, ",%s",
-			     mode_64bit ? names64[index] : names32[index]);
+			     mode_64bit && (sizeflag & AFLAG)
+			     ? names64[index] : names32[index]);
 		  oappend (scratchbuf);
 		}
               if (!intel_syntax
@@ -3703,7 +3717,7 @@ OP_OFF (bytemode, sizeflag)
 
   append_seg ();
 
-  if (sizeflag & AFLAG)
+  if ((sizeflag & AFLAG) || mode_64bit)
     off = get32 ();
   else
     off = get16 ();
@@ -3764,7 +3778,12 @@ ptr_reg (code, sizeflag)
 
   USED_REX (REX_MODE64);
   if (rex & REX_MODE64)
-    s = names64[code - eAX_reg];
+    {
+      if (!(sizeflag & AFLAG))
+        s = names32[code - eAX_reg];
+      else
+        s = names64[code - eAX_reg];
+    }
   else if (sizeflag & AFLAG)
     s = names32[code - eAX_reg];
   else
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 13eb728..9931a18 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1,6 +1,6 @@
 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001
+   2000, 2001, 2002
    Free Software Foundation, Inc.
    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
 
@@ -373,15 +373,21 @@ mips_isa_type (mach, isa, cputype)
       break;
     case bfd_mach_mips_sb1:
       *cputype = CPU_SB1;
-      *isa = ISA_MIPS64 | INSN_SB1;
+      *isa = ISA_MIPS64 | INSN_MIPS3D | INSN_SB1;
       break;
     case bfd_mach_mipsisa32:
-      * cputype = CPU_MIPS32;
-      * isa = ISA_MIPS32;
+      *cputype = CPU_MIPS32;
+      /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
+	 Note that MIPS-3D is not applicable to MIPS32.  (See _MIPS32
+	 Architecture For Programmers Volume I: Introduction to the
+	 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
+	 page 1.  */
+      *isa = ISA_MIPS32;
       break;
     case bfd_mach_mipsisa64:
-      * cputype = CPU_MIPS64;
-      * isa = ISA_MIPS64;
+      *cputype = CPU_MIPS64;
+      /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
+      *isa = ISA_MIPS64 | INSN_MIPS3D;
       break;
 
     default:
@@ -397,10 +403,14 @@ static int
 is_newabi (header)
      Elf_Internal_Ehdr *header;
 {
-  if ((header->e_flags
-       & (E_MIPS_ABI_EABI32 | E_MIPS_ABI_EABI64 | EF_MIPS_ABI2)) != 0
-      || (header->e_ident[EI_CLASS] == ELFCLASS64
-	  && (header->e_flags & E_MIPS_ABI_O64) == 0))
+  /* There are no old-style ABIs which use 64-bit ELF.  */
+  if (header->e_ident[EI_CLASS] == ELFCLASS64)
+    return 1;
+
+  /* If a 32-bit ELF file, N32, EABI32, and EABI64 are new-style ABIs.  */
+  if ((header->e_flags & EF_MIPS_ABI2) != 0
+      || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32
+      || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64)
     return 1;
 
   return 0;
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index e2386e8..d3776d6 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,9 +1,10 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
+   MIPS-3D support added by Broadcom Corporation (SiByte).
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -82,6 +83,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I32	INSN_ISA32
 #define I64     INSN_ISA64
 
+/* MIPS64 MIPS-3D ASE support.  */
+#define M3D     INSN_MIPS3D
+
 #define P3	INSN_4650
 #define L1	INSN_4010
 #define V1      INSN_4100
@@ -105,6 +109,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
    immediate operands must apear after the same instruction with
    registers.
 
+   Because of the lookup algorithm used, entries with the same opcode
+   name must be contiguous.
+ 
    Many instructions are short hand for other instructions (i.e., The
    jal <register> instruction is short for jalr <register>).  */
 
@@ -114,7 +121,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,	match,	    mask,	pinfo,          	membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	I32|G3	},
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	I4|I32|G3	},
 {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,		I4	},
 {"nop",     "",         0x00000000, 0xffffffff, 0,              	I1      },
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,              	I32	},
@@ -140,6 +147,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
 {"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		I1	},
 {"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"addr.ps", "D,S,T",	0x46c00018, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	M3D	},
 {"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
 {"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		I1	},
 {"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
@@ -150,22 +158,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* bal is at the top of the table.  */
 {"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC,		I1	},
 {"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc1any2f", "N,p",	0x45200000, 0xffe30000,	CBD|RD_CC|FP_S,		M3D	},
+{"bc1any2t", "N,p",	0x45210000, 0xffe30000,	CBD|RD_CC|FP_S,		M3D	},
+{"bc1any4f", "N,p",	0x45400000, 0xffe30000,	CBD|RD_CC|FP_S,		M3D	},
+{"bc1any4t", "N,p",	0x45410000, 0xffe30000,	CBD|RD_CC|FP_S,		M3D	},
 {"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},
 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},
 {"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},
 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},
-{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		I1	},
-{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
-{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		I1	},
-{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
-{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,		I1	},
-{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
 {"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},
 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},
 {"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},
 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},
+{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
 {"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		I1	},
 {"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
 {"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		I1	},
 {"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
 {"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,		I1	},
@@ -324,6 +336,54 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
+{"cabs.eq.d",  "M,S,T",	0x46200072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.eq.ps", "M,S,T",	0x46c00072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.eq.s",  "M,S,T",	0x46000072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.f.d",   "M,S,T",	0x46200070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.f.ps",  "M,S,T",	0x46c00070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.f.s",   "M,S,T",	0x46000070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.le.d",  "M,S,T",	0x4620007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.le.ps", "M,S,T",	0x46c0007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.le.s",  "M,S,T",	0x4600007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.lt.d",  "M,S,T",	0x4620007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.lt.ps", "M,S,T",	0x46c0007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.lt.s",  "M,S,T",	0x4600007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.nge.d", "M,S,T",	0x4620007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.nge.ps","M,S,T",	0x46c0007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.nge.s", "M,S,T",	0x4600007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ngl.d", "M,S,T",	0x4620007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngl.ps","M,S,T",	0x46c0007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngl.s", "M,S,T",	0x4600007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ngle.d","M,S,T",	0x46200079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngle.s","M,S,T",	0x46000079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ngt.d", "M,S,T",	0x4620007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngt.ps","M,S,T",	0x46c0007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ngt.s", "M,S,T",	0x4600007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ole.d", "M,S,T",	0x46200076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ole.ps","M,S,T",	0x46c00076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ole.s", "M,S,T",	0x46000076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.olt.d", "M,S,T",	0x46200074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.olt.ps","M,S,T",	0x46c00074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.olt.s", "M,S,T",	0x46000074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.seq.d", "M,S,T",	0x4620007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.seq.ps","M,S,T",	0x46c0007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.seq.s", "M,S,T",	0x4600007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.sf.d",  "M,S,T",	0x46200078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.sf.ps", "M,S,T",	0x46c00078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.sf.s",  "M,S,T",	0x46000078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ueq.d", "M,S,T",	0x46200073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ueq.ps","M,S,T",	0x46c00073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ueq.s", "M,S,T",	0x46000073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ule.d", "M,S,T",	0x46200077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ule.ps","M,S,T",	0x46c00077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ule.s", "M,S,T",	0x46000077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.ult.d", "M,S,T",	0x46200075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ult.ps","M,S,T",	0x46c00075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.ult.s", "M,S,T",	0x46000075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
+{"cabs.un.d",  "M,S,T",	0x46200071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.un.ps", "M,S,T",	0x46c00071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	M3D	},
+{"cabs.un.s",  "M,S,T",	0x46000071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	M3D	},
 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	I3|I32|T3},
 {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
 {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
@@ -353,7 +413,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cvt.s.pu","D,S",	0x46c00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	I5	},
 {"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
 {"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
+{"cvt.ps.pw", "D,S",	0x46800026, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	M3D	},
 {"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"cvt.pw.ps", "D,S",	0x46c00024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	M3D	},
 {"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		I3	},
 {"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		I3	},
 {"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		I3	},
@@ -583,6 +645,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		L1	},
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32	},
 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32	},
+{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I5	},
 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32	},
 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32	},
 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32	},
@@ -591,6 +654,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		L1	},
 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32	},
 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32	},
+{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I5	},
 /* move is at the top of the table.  */
 {"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4	},
 {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4	},
@@ -621,6 +685,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulo",    "d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		I1	},
 {"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		I1	},
 {"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		I1	},
+{"mulr.ps", "D,S,T",	0x46c0001a, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	M3D	},
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1	},
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1	},
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1	},
@@ -653,8 +718,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
 
 {"recip.d", "D,S",	0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		I4	},
-{"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
 {"recip.ps","D,S",	0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,		SB1	},
+{"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
+{"recip1.d",  "D,S",	0x4620001d, 0xffff003f,	WR_D|RD_S|FP_D,		M3D	},
+{"recip1.ps", "D,S",	0x46c0001d, 0xffff003f,	WR_D|RD_S|FP_S,		M3D	},
+{"recip1.s",  "D,S",	0x4600001d, 0xffff003f,	WR_D|RD_S|FP_S,		M3D	},
+{"recip2.d",  "D,S,T",	0x4620001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	M3D	},
+{"recip2.ps", "D,S,T",	0x46c0001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	M3D	},
+{"recip2.s",  "D,S,T",	0x4600001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	M3D	},
 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1	},
 {"rem",     "d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		I1	},
 {"rem",     "d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		I1	},
@@ -671,8 +742,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
 {"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		I2	},
 {"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		I4	},
-{"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
 {"rsqrt.ps","D,S",	0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,		SB1	},
+{"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
+{"rsqrt1.d",  "D,S",	0x4620001e, 0xffff003f,	WR_D|RD_S|FP_D,		M3D	},
+{"rsqrt1.ps", "D,S",	0x46c0001e, 0xffff003f,	WR_D|RD_S|FP_S,		M3D	},
+{"rsqrt1.s",  "D,S",	0x4600001e, 0xffff003f,	WR_D|RD_S|FP_S,		M3D	},
+{"rsqrt2.d",  "D,S,T",	0x4620001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	M3D	},
+{"rsqrt2.ps", "D,S,T",	0x46c0001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	M3D	},
+{"rsqrt2.s",  "D,S,T",	0x4600001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	M3D	},
 {"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
 {"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		I1	},
 {"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	I2	},
diff --git a/opcodes/pdp11-dis.c b/opcodes/pdp11-dis.c
index 850248e..507db93 100644
--- a/opcodes/pdp11-dis.c
+++ b/opcodes/pdp11-dis.c
@@ -1,5 +1,5 @@
 /* Print DEC PDP-11 instructions.
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2002 Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -38,6 +38,8 @@ static void print_reg PARAMS ((int reg, disassemble_info *info));
 static void print_freg PARAMS ((int freg, disassemble_info *info));
 static int print_operand PARAMS ((bfd_vma *memaddr, int code,
 				  disassemble_info *info));
+static int print_foperand PARAMS ((bfd_vma *memaddr, int code,
+                                   disassemble_info *info));
 int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
 
 static int
@@ -165,8 +167,10 @@ print_operand (memaddr, code, info)
       if (reg == 7)
 	{
 	  bfd_vma address = *memaddr + sign_extend (disp);
+	  if (mode == 7)
+	    FPRINTF (F, "*");
 	  if (!(code & JUMP))
-	    FPRINTF (F, "*$");
+	    FPRINTF (F, "$");
 	  (*info->print_address_func) (address, info);
 	}
       else
@@ -184,6 +188,23 @@ print_operand (memaddr, code, info)
   return 0;
 }
 
+static int
+print_foperand (memaddr, code, info)
+     bfd_vma *memaddr;
+     int code;
+     disassemble_info *info;
+{
+  int mode = (code >> 3) & 7;
+  int reg = code & 7;
+
+  if (mode == 0)
+    print_freg (reg, info);
+  else
+    return print_operand (memaddr, code, info);
+
+  return 0;
+}
+
 /* Print the PDP-11 instruction at address MEMADDR in debugged memory,
    on INFO->STREAM.  Returns length of the instruction, in bytes.  */
 
@@ -230,6 +251,14 @@ print_insn_pdp11 (memaddr, info)
 	    if (print_operand (&memaddr, dst, info) < 0)
 	      return -1;
 	    goto done;
+	  case PDP11_OPCODE_FOP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (strcmp (OP.name, "jmp") == 0)
+	      dst |= JUMP;
+	    if (print_foperand (&memaddr, dst, info) < 0)
+	      return -1;
+	    goto done;
 	  case PDP11_OPCODE_REG_OP:
 	    FPRINTF (F, OP.name);
 	    FPRINTF (F, AFTER_INSTRUCTION);
@@ -248,6 +277,28 @@ print_insn_pdp11 (memaddr, info)
 	    FPRINTF (F, OPERAND_SEPARATOR);
 	    print_reg (src, info);
 	    goto done;
+	  case PDP11_OPCODE_AC_FOP:
+	    {
+	      int ac = (opcode & 0xe0) >> 6;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      print_freg (ac, info);
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      if (print_foperand (&memaddr, dst, info) < 0)
+		return -1;
+	      goto done;
+	    }
+	  case PDP11_OPCODE_FOP_AC:
+	    {
+	      int ac = (opcode & 0xe0) >> 6;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      if (print_foperand (&memaddr, dst, info) < 0)
+		return -1;
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      print_freg (ac, info);
+	      goto done;
+	    }
 	  case PDP11_OPCODE_AC_OP:
 	    {
 	      int ac = (opcode & 0xe0) >> 6;
@@ -259,6 +310,17 @@ print_insn_pdp11 (memaddr, info)
 		return -1;
 	      goto done;
 	    }
+	  case PDP11_OPCODE_OP_AC:
+	    {
+	      int ac = (opcode & 0xe0) >> 6;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      if (print_operand (&memaddr, dst, info) < 0)
+		return -1;
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      print_freg (ac, info);
+	      goto done;
+	    }
 	  case PDP11_OPCODE_OP_OP:
 	    FPRINTF (F, OP.name);
 	    FPRINTF (F, AFTER_INSTRUCTION);
diff --git a/opcodes/pdp11-opc.c b/opcodes/pdp11-opc.c
index 3517dee..7445cde 100644
--- a/opcodes/pdp11-opc.c
+++ b/opcodes/pdp11-opc.c
@@ -1,5 +1,5 @@
 /* Opcode table for PDP-11.
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2002 Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -86,7 +86,7 @@ const struct pdp11_opcode pdp11_opcodes[] =
   { "rol",	0x0c40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
   { "asr",	0x0c80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
   { "asl",	0x0cc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
-  { "mark",	0x0d00, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
+  { "mark",	0x0d00, 0xffc0, PDP11_OPCODE_IMM6,	PDP11_LEIS },
   { "mfpi",	0x0d40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
   { "mtpi",	0x0d80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
   { "sxt",	0x0dc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
@@ -211,24 +211,28 @@ const struct pdp11_opcode pdp11_opcodes[] =
   { "ldfps",	0xf040, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
   { "stfps",	0xf080, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
   { "stst",	0xf0c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
-  { "clrf",	0xf100, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
-  { "tstf",	0xf140, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
-  { "absf",	0xf180, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
-  { "negf",	0xf1c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
-  { "mulf",	0xf200, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "modf",	0xf300, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "addf",	0xf400, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "ldf",	0xf500, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movif*/
-  { "subf",	0xf600, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "cmpf",	0xf700, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "stf",	0xf800, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movfi*/
-  { "divf",	0xf900, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "clrf",	0xf100, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "tstf",	0xf140, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "absf",	0xf180, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "negf",	0xf1c0, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "mulf",	0xf200, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "modf",	0xf300, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "addf",	0xf400, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "ldf",	0xf500, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },/*movif*/
+  { "subf",	0xf600, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "cmpf",	0xf700, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "stf",	0xf800, 0xff00, PDP11_OPCODE_AC_FOP,	PDP11_FPP },/*movfi*/
+  { "divf",	0xf900, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
   { "stexp",	0xfa00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
   { "stcfi",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "stcff",	0xfc00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
-  { "ldexp",	0xfd00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "ldcif",	0xfe00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
-  { "ldcff",	0xff00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
+  { "stcff",	0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,	PDP11_FPP },/* ? */
+  { "ldexp",	0xfd00, 0xff00, PDP11_OPCODE_OP_AC,	PDP11_FPP },
+  { "ldcif",	0xfe00, 0xff00, PDP11_OPCODE_OP_AC,	PDP11_FPP },
+  { "ldcff",	0xff00, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },/* ? */
+/* This entry MUST be last; it is a "catch-all" entry that will match when no
+ * other opcode entry matches during disassembly.
+ */
+  { "",		0x0000, 0x0000, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },
 };
 
 const struct pdp11_opcode pdp11_aliases[] =
@@ -239,6 +243,29 @@ const struct pdp11_opcode pdp11_aliases[] =
   { "bhis",	0x8600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
   { "blo",	0x8700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
   { "trap",	0x8900, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },
+  /* fpp xxxd alternate names to xxxf opcodes */
+  { "clrd",	0xf100, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "tstd",	0xf140, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "absd",	0xf180, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "negd",	0xf1c0, 0xffc0, PDP11_OPCODE_FOP,	PDP11_FPP },
+  { "muld",	0xf200, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "modd",	0xf300, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "addd",	0xf400, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "ldd",	0xf500, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },/*movif*/
+  { "subd",	0xf600, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "cmpd",	0xf700, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "std",	0xf800, 0xff00, PDP11_OPCODE_AC_FOP,	PDP11_FPP },/*movfi*/
+  { "divd",	0xf900, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },
+  { "stcfl",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcdi",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcdl",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcfd",	0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,	PDP11_FPP },/* ? */
+  { "stcdf",	0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,	PDP11_FPP },/* ? */
+  { "ldcid",	0xfe00, 0xff00, PDP11_OPCODE_OP_AC,	PDP11_FPP },
+  { "ldclf",	0xfe00, 0xff00, PDP11_OPCODE_OP_AC,	PDP11_FPP },
+  { "ldcld",	0xfe00, 0xff00, PDP11_OPCODE_OP_AC,	PDP11_FPP },
+  { "ldcfd",	0xff00, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },/* ? */
+  { "ldcdf",	0xff00, 0xff00, PDP11_OPCODE_FOP_AC,	PDP11_FPP },/* ? */
 };
 
 const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0];
diff --git a/opcodes/po/fr.po b/opcodes/po/fr.po
index 3853414..e1806b0 100644
--- a/opcodes/po/fr.po
+++ b/opcodes/po/fr.po
@@ -5,8 +5,8 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: opcodes 2.12-pre020121\n"
-"POT-Creation-Date: 2002-01-31 17:10+0000\n"
-"PO-Revision-Date: 2002-01-25 08:00-0500\n"
+"POT-Creation-Date: 2002-01-17 13:58+0000\n"
+"PO-Revision-Date: 2002-03-17 20:00-0500\n"
 "Last-Translator: Michel Robitaille <robitail@IRO.UMontreal.CA>\n"
 "Language-Team: French <traduc@traduc.org>\n"
 "MIME-Version: 1.0\n"
@@ -25,21 +25,21 @@ msgstr "saut indicé non aligné"
 msgid "Illegal limm reference in last instruction!\n"
 msgstr "Référence limite illégale dans la dernière instruction!\n"
 
-#: arm-dis.c:502
+#: arm-dis.c:509
 msgid "<illegal precision>"
 msgstr "<précision illégale>"
 
-#: arm-dis.c:1012
+#: arm-dis.c:1019
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr "Nom de jeu de registres inconnu: %s\n"
 
-#: arm-dis.c:1019
+#: arm-dis.c:1026
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr "Option du désassembleur non reconnue: %s\n"
 
-#: arm-dis.c:1191
+#: arm-dis.c:1198
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
@@ -60,10 +60,9 @@ msgstr "Erreur interne du désassembleur"
 #: avr-dis.c:228
 #, c-format
 msgid "unknown constraint `%c'"
-msgstr "contrainte inconnue `%c'"
+msgstr "contrainte inconnue Ğ %c ğ"
 
 #: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195
-#: xstormy16-ibld.c:195
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr "opérande hors gamme (%ld n'est pas entre %ld et %ld)"
@@ -89,101 +88,94 @@ msgstr "Erreur inconnue %d\n"
 msgid "Address 0x%x is out of bounds.\n"
 msgstr "Adresse 0x%x est hors gamme.\n"
 
-#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231
+#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr "Champ non reconnu %d lors de l'analyse.\n"
 
-#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281
+#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295
 msgid "missing mnemonic in syntax string"
 msgstr "mnémonique manquante dans la syntaxe de la chaîne"
 
 #. We couldn't parse it.
-#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511
-#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430
-#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623
-#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508
-#: xstormy16-asm.c:610
+#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624
 msgid "unrecognized instruction"
 msgstr "instruction non reconnue"
 
-#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464
+#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
-msgstr "erreur de syntaxe (caractère `%c' attendu,  `%c' obtenu)"
+msgstr "erreur de syntaxe (caractère Ğ %c ğ attendu,  Ğ %c ğ obtenu)"
 
-#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474
+#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
-msgstr ""
-"erreur de syntaxe (caractère `%c' attendu, fin de l'instruction obtenue)"
+msgstr "erreur de syntaxe (caractère Ğ %c ğ attendu, fin de l'instruction obtenue)"
 
-#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502
+#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516
 msgid "junk at end of line"
 msgstr "rebut à la fin de la ligne"
 
-#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609
+#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623
 msgid "unrecognized form of instruction"
 msgstr "forme d'instruction non reconnue"
 
-#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621
+#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635
 #, c-format
 msgid "bad instruction `%.50s...'"
-msgstr "instruction erronée `%.50s...'"
+msgstr "instruction erronée Ğ %.50s... ğ"
 
-#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624
+#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638
 #, c-format
 msgid "bad instruction `%.50s'"
-msgstr "instruction erronée `%.50s'"
+msgstr "instruction erronée Ğ %.50s ğ"
 
 #. Default text to print if an instruction isn't recognized.
 #: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
-#: xstormy16-dis.c:39
 msgid "*unknown*"
 msgstr "*inconnu*"
 
-#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169
+#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr "Champ non reconnu %d lors de l'impression insn.\n"
 
-#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr "opérande hors gamme (%ld n'est pas entre %ld et %lu)"
 
-#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179
 #, c-format
 msgid "operand out of range (%lu not between 0 and %lu)"
 msgstr "opérande hors gamme (%lu n'est pas entre 0 et %lu)"
 
-#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr "Champ non reconnu %d lors de la construction de insn.\n"
 
-#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr "Champ non reconnu %d lors du décodage de insn.\n"
 
-#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr "Champ non reconnu %d lors de la prise d'une opérande int.\n"
 
-#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr "Champ non reconnu %d lors de la prise d'une opérande vma.\n"
 
-#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande int.\n"
 
-#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001
-#: xstormy16-ibld.c:1224
+#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande vma.\n"
@@ -289,9 +281,7 @@ msgstr "option conditionnelle invalide"
 
 #: ppc-opc.c:800
 msgid "attempt to set y bit when using + or - modifier"
-msgstr ""
-"tentative d'initialisation du bit y lorsque le modificateur + ou - a été "
-"utilisé"
+msgstr "tentative d'initialisation du bit y lorsque le modificateur + ou - a été utilisé"
 
 #: ppc-opc.c:832 ppc-opc.c:884
 msgid "offset not a multiple of 4"
@@ -307,9 +297,7 @@ msgstr "décalage n'est pas entre -8192 et 8191"
 
 #: ppc-opc.c:910
 msgid "ignoring least significant bits in branch offset"
-msgstr ""
-"Les derniers bits les moins significatifs sont ignorés dans le décalage de "
-"branchement"
+msgstr "Les derniers bits les moins significatifs sont ignorés dans le décalage de branchement"
 
 #: ppc-opc.c:944 ppc-opc.c:981
 msgid "illegal bitmask"
@@ -335,17 +323,17 @@ msgstr "inconnu"
 #: sparc-dis.c:824
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
-msgstr "Erreur interne:  sparc-opcode.h erroné: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erreur interne:  sparc-opcode.h erroné: Ğ %s ğ, %#.8lx, %#.8lx\n"
 
 #: sparc-dis.c:835
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
-msgstr "Erreur interne: sparc-opcode.h erroné: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erreur interne: sparc-opcode.h erroné: Ğ %s ğ, %#.8lx, %#.8lx\n"
 
 #: sparc-dis.c:884
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
-msgstr "Erreur interne: sparc-opcode.h erroné: \"%s\" == \"%s\"\n"
+msgstr "Erreur interne: sparc-opcode.h erroné: Ğ %s ğ == Ğ %s ğ\n"
 
 #: v850-dis.c:224
 #, c-format
@@ -406,36 +394,5 @@ msgstr "La valeur immédiate est hors gamme et est impaire."
 msgid "immediate value must be even"
 msgstr "La valeur immédiate doit être paire."
 
-#: xstormy16-asm.c:74
-#, fuzzy
-msgid "Bad register in preincrement"
-msgstr "registre index n'est pas dans la plage de chargement"
-
-#: xstormy16-asm.c:79
-#, fuzzy
-msgid "Bad register in postincrement"
-msgstr "registre invalide pour un ajustement de la pile"
-
-#: xstormy16-asm.c:81
-#, fuzzy
-msgid "Bad register name"
-msgstr "registre index n'est pas dans la plage de chargement"
-
-#: xstormy16-asm.c:85
-msgid "Label conflicts with register name"
-msgstr ""
-
-#: xstormy16-asm.c:89
-msgid "Label conflicts with `Rx'"
-msgstr ""
-
-#: xstormy16-asm.c:91
-msgid "Bad immediate expression"
-msgstr ""
-
-#: xstormy16-asm.c:120
-msgid "Small operand was not an immediate number"
-msgstr ""
-
 #~ msgid "unrecognized keyword/register name"
 #~ msgstr "nom de mot clé ou de registre non reconnu"
diff --git a/opcodes/po/id.po b/opcodes/po/id.po
new file mode 100644
index 0000000..3c69b4b
--- /dev/null
+++ b/opcodes/po/id.po
@@ -0,0 +1,395 @@
+# opcodes 2.12-pre020121 (Indonesian)
+# Copyright (C) 2002 Free Software Foundation, Inc.
+# Tedi Heriyanto <tedi_h@gmx.net>, 2002.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.12-pre020121\n"
+"POT-Creation-Date: 2002-01-17 13:58+0000\n"
+"PO-Revision-Date: 2002-04-02 08:20GMT+0700\n"
+"Last-Translator: Tedi Heriyanto <tedi_h@gmx.net>\n"
+"Language-Team: Indonesian <translation-team-id@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"X-Generator: KBabel 0.9.5\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "operand cabang tidak rata"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "petunjuk lompat tidak rata"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "referensi limm ilegal dalam instruksi terakhir!\n"
+
+#: arm-dis.c:509
+msgid "<illegal precision>"
+msgstr "<presisi ilegal>"
+
+#: arm-dis.c:1019
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Set nama register tidak dikenal: %s\n"
+
+#: arm-dis.c:1026
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Option disasembler tidak dikenal: %s\n"
+
+#: arm-dis.c:1198
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Option disablembler khusus ARM berikut ini didukung untuk digunakan dengan\n"
+"switch -M:\n"
+
+#: avr-dis.c:118 avr-dis.c:128
+msgid "undefined"
+msgstr "tidak didefinisikan"
+
+#: avr-dis.c:180
+msgid "Internal disassembler error"
+msgstr "Kesalahan disasembler internal"
+
+#: avr-dis.c:228
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "konstrain tidak dikenal `%c'"
+
+#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operand keluar batas (%ld tidak antara %ld dan %ld)"
+
+#: cgen-asm.c:367
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operand keluar batas (%lu tidak antara %lu dan %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<register tidak dikenal %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Kesalahan tidak dikenal %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Alamat 0x%x di luar batas.\n"
+
+#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Field tidak dikenal %d saat parsing.\n"
+
+#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295
+msgid "missing mnemonic in syntax string"
+msgstr "mnemonik hilang dalam string sintaks"
+
+#. We couldn't parse it.
+#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624
+msgid "unrecognized instruction"
+msgstr "instruksti tidak dikenal"
+
+#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan `%c')"
+
+#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan akhir instruksi)"
+
+#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516
+msgid "junk at end of line"
+msgstr "sampah di akhir baris"
+
+#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623
+msgid "unrecognized form of instruction"
+msgstr "bentuk instruksi tidak dikenal"
+
+#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instruksi buruk `%.50s...'"
+
+#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instruksi buruk `%.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
+msgid "*unknown*"
+msgstr "*tidak dikenal*"
+
+#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Field tidak dikenal %d saat mencetak insn.\n"
+
+#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operand di luar batas (%ld tidak antara %ld dan %lu)"
+
+#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operand di luar batas (%lu tidak antara 0 dan %lu)"
+
+#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Field tidak dikenal %d saat membuild insn.\n"
+
+#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Field tidak dikenal %d saat mendekode insn.\n"
+
+#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Field tidak dikenal %d saat memperoleh operand int.\n"
+
+#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Field tidak dikenal %d saat memperoleh operand vma.\n"
+
+#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Field tidak dikenal %d saat menset operand int.\n"
+
+#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Field tidak dikenal %d saat menset operand vma.\n"
+
+#: h8300-dis.c:384
+#, c-format
+msgid "Hmmmm %x"
+msgstr "Hmmmm %x"
+
+#: h8300-dis.c:395
+#, c-format
+msgid "Don't understand %x \n"
+msgstr "Tidak mengerti %x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "tidak dapat menangani insert %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*tidak dikenal*"
+
+#: i386-dis.c:1649
+msgid "<internal disassembler error>"
+msgstr "<kesalahan asembler internal>"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "tidak dikenal\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "tidak dikenal\t0x%04lx"
+
+#: m10300-dis.c:685
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "tidak dikenal\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<kesalahan internal dalam tabel opcode: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<kode fungsi %d>"
+
+#: m88k-dis.c:255
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <kesalahan dis: %08x>"
+
+#: mips-dis.c:290
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# kesalahan internal, modifier tidak didefinisikan(%c)"
+
+#: mips-dis.c:1154
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# kesalahan internal disasembler, modifier tidak dikenal (%c)"
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Case buruk %d (%s) dalam %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Internal: Kode belum didebug (tidak ada test-case): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(tidak dikenal)"
+
+#: mmix-dis.c:517
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*tipe operand tidak dikenal: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:628
+msgid "$<undefined>"
+msgstr "$<tidak didefinisikan>"
+
+#: ppc-opc.c:765 ppc-opc.c:798
+msgid "invalid conditional option"
+msgstr "option kondisional tidak valid"
+
+#: ppc-opc.c:800
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "berusaha menset bit y saat menggunakan modifier + atau -"
+
+#: ppc-opc.c:832 ppc-opc.c:884
+msgid "offset not a multiple of 4"
+msgstr "offset bukan kelipatan 4"
+
+#: ppc-opc.c:857
+msgid "offset not between -2048 and 2047"
+msgstr "offset tidak berada antara -2048 dan 2047"
+
+#: ppc-opc.c:882
+msgid "offset not between -8192 and 8191"
+msgstr "offset tidak berada antara -8192 dan 8191"
+
+#: ppc-opc.c:910
+msgid "ignoring least significant bits in branch offset"
+msgstr "mengabaikan least significant bit dalam offset cabang"
+
+#: ppc-opc.c:944 ppc-opc.c:981
+msgid "illegal bitmask"
+msgstr "bitmask ilegal"
+
+#: ppc-opc.c:1054
+msgid "value out of range"
+msgstr "nilai di luar batas"
+
+#: ppc-opc.c:1130
+msgid "index register in load range"
+msgstr "register indeks dalam daerah pemuatan"
+
+#: ppc-opc.c:1146
+msgid "invalid register operand when updating"
+msgstr "operand register tidak valid saat mengupdate"
+
+#. Mark as non-valid instruction
+#: sparc-dis.c:749
+msgid "unknown"
+msgstr "tidak dikenal"
+
+#: sparc-dis.c:824
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Kesalahan internal:  sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:884
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:224
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "shift operand tidak dikenal: %x\n"
+
+#: v850-dis.c:236
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "reg pop tidak dikenal: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "nilai displacement tidak dalam jangkauan dan tidak rata"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "nilai displacement di luar batas"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "nilai displacement tidak rata"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "nilai langsung di luar batas"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "nilai cabang tidak dalam jangkauan"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "nilai cabang di luar jangkauan"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "cabang offset ganjil"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "nilai cabang di luar jangkauan dan offset ganjil"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "register tidak valid untuk penyesuaian stack"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "nilai langsung tidak dalam jangkauan dan tidak genap"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "nilai langsung harus genap"
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 6597066..1e49597 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -510,6 +510,10 @@ const struct powerpc_operand powerpc_operands[] =
 #define WS_MASK (0x7 << 11)
   { 3, 11, 0, 0, 0 },
 
+  /* The L field in an mtmsrd instruction */
+#define MTMSRD_L WS + 1
+  { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
+
 };
 
 /* The functions used to insert and extract complicated operands.  */
@@ -1412,9 +1416,15 @@ extract_tbr (insn, dialect, invalid)
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
+/* An XRARB_MASK, but with the L bit clear. */
+#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
+
 /* An X_MASK with the RT and RA fields fixed.  */
 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
 
+/* An XRTRA_MASK, but with L bit clear.  */
+#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
+
 /* An X form comparison instruction.  */
 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
 
@@ -1803,7 +1813,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
 { "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
 { "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
-{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
 { "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
 { "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
 { "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
@@ -2947,7 +2957,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "wrteei",  X(31,163),	XE_MASK,	PPC403,		{ E } },
 { "wrteei",  X(31,163),	XE_MASK,	BOOKE,		{ E } },
 
-{ "mtmsrd",  X(31,178),	XRARB_MASK,	PPC64,		{ RS } },
+{ "mtmsrd",  X(31,178),	XRLARB_MASK,	PPC64,		{ RS, MTMSRD_L } },
 
 { "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
 
@@ -3071,7 +3081,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
 
-{ "tlbie",   X(31,306),	XRTRA_MASK,	PPC,		{ RB } },
+{ "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
 { "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA, RB } },
 
 { "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
@@ -3662,7 +3672,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "rac",     X(31,818),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
 { "dss",     XDSS(31,822,0), XDSS_MASK,	PPCVEC,		{ STRM } },
-{ "dssall",  XDSS(31,822,1), XDSS_MASK,	PPCVEC,		{ STRM } },
+{ "dssall",  XDSS(31,822,1), XDSS_MASK,	PPCVEC,		{ 0 } },
 
 { "srawi",   XRC(31,824,0), X_MASK,	PPCCOM,		{ RA, RS, SH } },
 { "srai",    XRC(31,824,0), X_MASK,	PWRCOM,		{ RA, RS, SH } },
@@ -3678,7 +3688,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "tlbsx.",  XRC(31,914,1), X_MASK, 	PPC403,		{ RT, RA, RB } },
 
 { "tlbsx",   XRC(31,914,0), X_MASK,	BOOKE,		{ RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK,	BOOKE,		{ RA, RB } },
 { "tlbsxe",  XRC(31,915,0), X_MASK,	BOOKE,		{ RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK,	BOOKE,		{ RA, RB } },
 
 { "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
 
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 2f2311b..8745a89 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -1,5 +1,5 @@
 /* s390-dis.c -- Disassemble S390 instructions
-   Copyright 2000, 2001 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
    This file is part of GDB, GAS and the GNU binutils.
diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c
index 091d937..d375e69 100644
--- a/opcodes/z8k-dis.c
+++ b/opcodes/z8k-dis.c
@@ -1,22 +1,23 @@
 /* Disassemble z8000 code.
-   Copyright 1992, 1993, 1998, 2000, 2001
+   Copyright 1992, 1993, 1998, 2000, 2001, 2002
    Free Software Foundation, Inc.
 
-This file is part of GNU Binutils.
+   This file is part of GNU Binutils.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+   USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -26,7 +27,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include <setjmp.h>
 
-typedef struct {
+typedef struct
+{
   /* These are all indexed by nibble number (i.e only every other entry
      of bytes is used, and every 4th entry of words).  */
   unsigned char nibbles[24];
@@ -48,7 +50,8 @@ typedef struct {
   unsigned long ctrl_code;
   unsigned long flags;
   unsigned long interrupts;
-} instr_data_s;
+}
+instr_data_s;
 
 static int fetch_data PARAMS ((struct disassemble_info *, int));
 
@@ -106,35 +109,37 @@ fetch_data (info, nibble)
   return 1;
 }
 
-static char *codes[16] = {
-  "f",
-  "lt",
-  "le",
-  "ule",
-  "ov/pe",
-  "mi",
-  "eq",
-  "c/ult",
-  "t",
-  "ge",
-  "gt",
-  "ugt",
-  "nov/po",
-  "pl",
-  "ne",
-  "nc/uge"
-};
-
-static char *ctrl_names[8] = {
-  "<invld>",
-  "flags",
-  "fcw",
-  "refresh",
-  "psapseg",
-  "psapoff",
-  "nspseg",
-  "nspoff"
-};
+static char *codes[16] =
+  {
+    "f",
+    "lt",
+    "le",
+    "ule",
+    "ov/pe",
+    "mi",
+    "eq",
+    "c/ult",
+    "t",
+    "ge",
+    "gt",
+    "ugt",
+    "nov/po",
+    "pl",
+    "ne",
+    "nc/uge"
+  };
+
+static char *ctrl_names[8] =
+  {
+    "<invld>",
+    "flags",
+    "fcw",
+    "refresh",
+    "psapseg",
+    "psapoff",
+    "nspseg",
+    "nspoff"
+  };
 
 static int seg_length;
 static int print_insn_z8k PARAMS ((bfd_vma, disassemble_info *, int));
@@ -159,6 +164,10 @@ print_insn_z8k (addr, info, is_segmented)
     /* Error return.  */
     return -1;
 
+  info->bytes_per_chunk = 2;
+  info->bytes_per_line = 6;
+  info->display_endian = BFD_ENDIAN_BIG;
+
   instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info);
   if (instr_data.tabl_index > 0)
     {
@@ -227,6 +236,8 @@ z8k_lookup_instr (nibbles, info)
 	      if (datum_value != instr_nibl)
 		nibl_matched = 0;
 	      break;
+	    case CLASS_IGNORE:
+	      break;
 	    case CLASS_00II:
 	      if (!((~instr_nibl) & 0x4))
 		nibl_matched = 0;
@@ -265,10 +276,9 @@ z8k_lookup_instr (nibbles, info)
 	      break;
 	    }
 	}
+
       if (nibl_matched)
-	{
-	  return tabl_index;
-	}
+	return tabl_index;
 
       tabl_index++;
     }
@@ -281,24 +291,13 @@ output_instr (instr_data, addr, info)
      unsigned long addr ATTRIBUTE_UNUSED;
      disassemble_info *info;
 {
-  int loop, loop_limit;
-  char tmp_str[20];
+  int num_bytes;
   char out_str[100];
 
-  strcpy (out_str, "\t");
-
-  loop_limit = (z8k_table[instr_data->tabl_index].length + seg_length) * 2;
-  FETCH_DATA (info, loop_limit);
-  for (loop = 0; loop < loop_limit; loop++)
-    {
-      sprintf (tmp_str, "%x", instr_data->nibbles[loop]);
-      strcat (out_str, tmp_str);
-    }
+  out_str[0] = 0;
 
-  while (loop++ < 8)
-    {
-      strcat (out_str, " ");
-    }
+  num_bytes = (z8k_table[instr_data->tabl_index].length + seg_length) * 2;
+  FETCH_DATA (info, num_bytes);
 
   strcat (out_str, instr_data->instr_asmsrc);
 
@@ -320,6 +319,7 @@ unpack_instr (instr_data, is_segmented, info)
   nibl_count = 0;
   loop = 0;
   seg_length = 0;
+
   while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0)
     {
       FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4));
@@ -343,16 +343,13 @@ unpack_instr (instr_data, is_segmented, info)
 	      break;
 	    case ARG_DISP12:
 	      if (instr_word & 0x800)
-		{
-		  /* neg. 12 bit displacement */
-		  instr_data->displacement = instr_data->insn_start + 2
-		    - (signed short) ((instr_word & 0xfff) | 0xf000) * 2;
-		}
+		/* Negative 12 bit displacement.  */
+		instr_data->displacement = instr_data->insn_start + 2
+		  - (signed short) ((instr_word & 0xfff) | 0xf000) * 2;
 	      else
-		{
-		  instr_data->displacement = instr_data->insn_start + 2
-		    - (instr_word & 0x0fff) * 2;
-		}
+		instr_data->displacement = instr_data->insn_start + 2
+		  - (instr_word & 0x0fff) * 2;
+
 	      nibl_count += 2;
 	      break;
 	    default:
@@ -365,8 +362,11 @@ unpack_instr (instr_data, is_segmented, info)
 	    case ARG_IMM4:
 	      instr_data->immediate = instr_nibl;
 	      break;
+	    case ARG_NIM4:
+	      instr_data->immediate = (- instr_nibl) & 0xf;
+	      break;
 	    case ARG_NIM8:
-	      instr_data->immediate = (-instr_byte);
+	      instr_data->immediate = (- instr_byte) & 0xff;
 	      nibl_count += 1;
 	      break;
 	    case ARG_IMM8:
@@ -452,6 +452,7 @@ unpack_instr (instr_data, is_segmented, info)
 	case CLASS_00II:
 	  instr_data->interrupts = instr_nibl & 0x3;
 	  break;
+	case CLASS_IGNORE:
 	case CLASS_BIT:
 	  instr_data->ctrl_code = instr_nibl & 0x7;
 	  break;
@@ -469,6 +470,10 @@ unpack_instr (instr_data, is_segmented, info)
 	    instr_data->insn_start + 2 + (signed char) instr_byte * 2;
 	  nibl_count += 1;
 	  break;
+        case CLASS_BIT_1OR2:
+          instr_data->immediate = ((instr_nibl >> 1) & 0x1) + 1;
+          nibl_count += 1;
+	  break;
 	default:
 	  abort ();
 	  break;
@@ -489,7 +494,7 @@ unparse_instr (instr_data, is_segmented)
   int loop, loop_limit;
   char out_str[80], tmp_str[25];
 
-  sprintf (out_str, "\t%s\t", z8k_table[instr_data->tabl_index].name);
+  sprintf (out_str, "%s\t", z8k_table[instr_data->tabl_index].name);
 
   loop_limit = z8k_table[instr_data->tabl_index].noperands;
   for (loop = 0; loop < loop_limit; loop++)
@@ -504,18 +509,26 @@ unparse_instr (instr_data, is_segmented)
       switch (datum_class)
 	{
 	case CLASS_X:
-	  sprintf (tmp_str, "0x%0lx(R%ld)", instr_data->address,
-		   instr_data->arg_reg[datum_value]);
+          sprintf (tmp_str, "0x%0lx(r%ld)", instr_data->address,
+                   instr_data->arg_reg[datum_value]);
 	  strcat (out_str, tmp_str);
 	  break;
 	case CLASS_BA:
-	  sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value],
-		   instr_data->immediate);
+          if (is_segmented)
+            sprintf (tmp_str, "rr%ld(#%lx)", instr_data->arg_reg[datum_value],
+                     instr_data->immediate);
+          else
+            sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value],
+                     instr_data->immediate);
 	  strcat (out_str, tmp_str);
 	  break;
 	case CLASS_BX:
-	  sprintf (tmp_str, "r%ld(R%ld)", instr_data->arg_reg[datum_value],
-		   instr_data->arg_reg[ARG_RX]);
+          if (is_segmented)
+            sprintf (tmp_str, "rr%ld(r%ld)", instr_data->arg_reg[datum_value],
+                     instr_data->arg_reg[ARG_RX]);
+          else
+            sprintf (tmp_str, "r%ld(r%ld)", instr_data->arg_reg[datum_value],
+                     instr_data->arg_reg[ARG_RX]);
 	  strcat (out_str, tmp_str);
 	  break;
 	case CLASS_DISP:
diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h
index c62867c..025cfab 100644
--- a/opcodes/z8k-opc.h
+++ b/opcodes/z8k-opc.h
@@ -21,6 +21,7 @@
 #define ARG_IMM2 0x0a
 #define ARG_IMM1OR2 0x0b
 #define ARG_DISP12 0x0b
+#define ARG_NIM4 0x0c
 #define ARG_DISP8 0x0c
 #define ARG_IMM4M1 0x0d
 #define CLASS_MASK 0x1fff0
@@ -32,6 +33,7 @@
 #define CLASS_IMM 0x60
 #define CLASS_CC 0x70
 #define CLASS_CTRL 0x80
+#define CLASS_IGNORE 0x90
 #define CLASS_ADDRESS 0xd0
 #define CLASS_0CCC 0xe0
 #define CLASS_1CCC 0xf0
@@ -2419,64 +2421,64 @@ opcode_entry_type z8k_table[] = {
 	{CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,215},
 
 
-/* 0001 1100 ddN0 1001 0000 ssss 0000 nminus1 *** ldm @rd,rs,n */
+/* 0001 1100 ddN0 1001 0000 ssss 0000 imm4m1 *** ldm @rd,rs,n */
 {
 #ifdef NICENAMES
 "ldm @rd,rs,n",16,11,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,216},
+"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,216},
 
 
-/* 0101 1100 ddN0 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst(rd),rs,n */
+/* 0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst(rd),rs,n */
 {
 #ifdef NICENAMES
 "ldm address_dst(rd),rs,n",16,15,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,217},
+"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,217},
 
 
-/* 0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst,rs,n */
+/* 0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst,rs,n */
 {
 #ifdef NICENAMES
 "ldm address_dst,rs,n",16,14,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,218},
+"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,218},
 
 
-/* 0001 1100 ssN0 0001 0000 dddd 0000 nminus1 *** ldm rd,@rs,n */
+/* 0001 1100 ssN0 0001 0000 dddd 0000 imm4m1 *** ldm rd,@rs,n */
 {
 #ifdef NICENAMES
 "ldm rd,@rs,n",16,11,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,219},
+"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,219},
 
 
-/* 0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src(rs),n */
+/* 0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src(rs),n */
 {
 #ifdef NICENAMES
 "ldm rd,address_src(rs),n",16,15,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,220},
+"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,220},
 
 
-/* 0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src,n */
+/* 0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src,n */
 {
 #ifdef NICENAMES
 "ldm rd,address_src,n",16,14,
 0x00,
 #endif
-"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMMN),},
-	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,221},
+"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMM4M1),},
+	{CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,221},
 
 
 /* 0011 1001 ssN0 0000 *** ldps @rs */
@@ -3729,14 +3731,14 @@ opcode_entry_type z8k_table[] = {
 	{CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,346},
 
 
-/* 1011 0010 dddd 1001  0000 0000 imm8 *** slab rbd,imm8 */
+/* 1011 0010 dddd 1001 iiii iiii 0000 imm4 *** slab rbd,imm4 */
 {
 #ifdef NICENAMES
-"slab rbd,imm8",8,13,
+"slab rbd,imm4",8,13,
 0x3c,
 #endif
-"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
-	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,347},
+"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
+	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,347},
 
 
 /* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */
@@ -3759,14 +3761,14 @@ opcode_entry_type z8k_table[] = {
 	{CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,349},
 
 
-/* 1011 0010 dddd 0001  0000 0000 imm8 *** sllb rbd,imm8 */
+/* 1011 0010 dddd 0001 iiii iiii 0000 imm4 *** sllb rbd,imm4 */
 {
 #ifdef NICENAMES
-"sllb rbd,imm8",8,13,
+"sllb rbd,imm4",8,13,
 0x38,
 #endif
-"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
-	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,350},
+"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
+	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,350},
 
 
 /* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */
@@ -3849,14 +3851,14 @@ opcode_entry_type z8k_table[] = {
 	{CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,358},
 
 
-/* 1011 0010 dddd 1001 0000 0000 nim8 *** srab rbd,imm8 */
+/* 1011 0010 dddd 1001 iiii iiii 1111 nim4 *** srab rbd,imm4 */
 {
 #ifdef NICENAMES
-"srab rbd,imm8",8,13,
+"srab rbd,imm4",8,13,
 0x3c,
 #endif
-"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
-	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,359},
+"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
+	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,359},
 
 
 /* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */
@@ -3879,14 +3881,14 @@ opcode_entry_type z8k_table[] = {
 	{CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,361},
 
 
-/* 1011 0010 dddd 0001 0000 0000 nim8 *** srlb rbd,imm8 */
+/* 1011 0010 dddd 0001 iiii iiii 1111 nim4 *** srlb rbd,imm4 */
 {
 #ifdef NICENAMES
-"srlb rbd,imm8",8,13,
+"srlb rbd,imm4",8,13,
 0x3c,
 #endif
-"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
-	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,362},
+"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),},
+	{CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,362},
 
 
 /* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */
diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c
index f171724..fa85059 100644
--- a/opcodes/z8kgen.c
+++ b/opcodes/z8kgen.c
@@ -1,23 +1,23 @@
-/*
-  Copyright 2001 Free Software Foundation, Inc.
+/* Copyright 2001, 2002 Free Software Foundation, Inc.
 
-  This file is part of GNU Binutils.
+   This file is part of GNU Binutils.
 
-  This program is free software; you can redistribute it and/or modify
-  it under the terms of the GNU General Public License as published by
-  the Free Software Foundation; either version 2 of the License, or
-  (at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-  This program is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-  You should have received a copy of the GNU General Public License
-  along with this program; if not, write to the Free Software
-  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+   USA.  */
 
-/* This program generates z8k-opc.h */
+/* This program generates z8k-opc.h.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -285,12 +285,12 @@ struct op opt[] =
 
   "------", 5, 16, "1011 1101 dddd imm4", "ldk rd,imm4", 0,
 
-  "------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 nminus1", "ldm @rd,rs,n", 0,
-  "------", 15, 16, "0101 1100 ddN0 1001 0000 ssss 0000 nminus1 address_dst", "ldm address_dst(rd),rs,n", 0,
-  "------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst", "ldm address_dst,rs,n", 0,
-  "------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 nminus1", "ldm rd,@rs,n", 0,
-  "------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src(rs),n", 0,
-  "------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src,n", 0,
+  "------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 imm4m1", "ldm @rd,rs,n", 0,
+  "------", 15, 16, "0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst(rd),rs,n", 0,
+  "------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst,rs,n", 0,
+  "------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 imm4m1", "ldm rd,@rs,n", 0,
+  "------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src(rs),n", 0,
+  "------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src,n", 0,
 
   "CZSVDH", 12, 16, "0011 1001 ssN0 0000", "ldps @rs", 0,
   "CZSVDH", 16, 16, "0111 1001 0000 0000 address_src", "ldps address_src", 0,
@@ -434,11 +434,11 @@ struct op opt[] =
   "------", 0, 16, "0011 1010 ssN0 0001 0000 aaaa ddN0 0000", "sinibr @rd,@rs,ra", 0,
 
   "CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0,
-  "CZSV--", 13, 8, "1011 0010 dddd 1001  0000 0000 imm8", "slab rbd,imm8", 0,
+  "CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 0000 imm4", "slab rbd,imm4", 0,
   "CZSV--", 13, 32, "1011 0011 dddd 1101 0000 0000 imm8", "slal rrd,imm8", 0,
 
   "CZS---", 13, 16, "1011 0011 dddd 0001 0000 0000 imm8", "sll rd,imm8", 0,
-  "CZS---", 13, 8, "1011 0010 dddd 0001  0000 0000 imm8", "sllb rbd,imm8", 0,
+  "CZS---", 13, 8, "1011 0010 dddd 0001 iiii iiii 0000 imm4", "sllb rbd,imm4", 0,
   "CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0,
 
   "------", 0, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0,
@@ -449,11 +449,11 @@ struct op opt[] =
   "------", 0, 16, "0011 1010 ssN0 0011 0000 aaaa ddN0 0000", "soutibr @rd,@rs,ra", 0,
 
   "CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0,
-  "CZSV--", 13, 8, "1011 0010 dddd 1001 0000 0000 nim8", "srab rbd,imm8", 0,
+  "CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 1111 nim4", "srab rbd,imm4", 0,
   "CZSV--", 13, 32, "1011 0011 dddd 1101 1111 1111 nim8", "sral rrd,imm8", 0,
 
   "CZSV--", 13, 16, "1011 0011 dddd 0001 1111 1111 nim8", "srl rd,imm8", 0,
-  "CZSV--", 13, 8, "1011 0010 dddd 0001 0000 0000 nim8", "srlb rbd,imm8", 0,
+  "CZSV--", 13, 8, "1011 0010 dddd 0001 iiii iiii 1111 nim4", "srlb rbd,imm4", 0,
   "CZSV--", 13, 32, "1011 0011 dddd 0101 1111 1111 nim8", "srll rrd,imm8", 0,
 
   "CZSV--", 7, 16, "0000 0011 ssN0 dddd", "sub rd,@rs", 0,
@@ -595,7 +595,7 @@ struct tok_struct args[] =
   {"imm32", "CLASS_IMM+(ARG_IMM32)",},
   {"imm4m1", "CLASS_IMM +(ARG_IMM4M1)",},
   {"imm4", "CLASS_IMM +(ARG_IMM4)",},
-  {"n", "CLASS_IMM + (ARG_IMMN)",},
+  {"n", "CLASS_IMM + (ARG_IMM4M1)",},
   {"ctrl", "CLASS_CTRL",},
   {"rba", "CLASS_REG_BYTE+(ARG_RA)",},
   {"rbb", "CLASS_REG_BYTE+(ARG_RB)",},
@@ -695,6 +695,7 @@ struct tok_struct toks[] =
   "imm8", "CLASS_IMM+(ARG_IMM8)", 2,
   "imm16", "CLASS_IMM+(ARG_IMM16)", 4,
   "imm32", "CLASS_IMM+(ARG_IMM32)", 8,
+  "nim4", "CLASS_IMM+(ARG_NIM4)", 2,
   "nim8", "CLASS_IMM+(ARG_NIM8)", 2,
   "0ccc", "CLASS_0CCC", 1,
   "1ccc", "CLASS_1CCC", 1,
@@ -703,6 +704,8 @@ struct tok_struct toks[] =
   "1disp7", "CLASS_1DISP7", 2,
   "01ii", "CLASS_01II", 1,
   "00ii", "CLASS_00II", 1,
+
+  "iiii", "CLASS_IGNORE", 1,
   0, 0
 };
 
@@ -992,6 +995,7 @@ gas ()
   printf ("#define ARG_IMM1OR2 0x0b\n");
 
   printf ("#define ARG_DISP12 0x0b\n");
+  printf ("#define ARG_NIM4 0x0c\n");
   printf ("#define ARG_DISP8 0x0c\n");
   printf ("#define ARG_IMM4M1 0x0d\n");
   printf ("#define CLASS_MASK 0x1fff0\n");
@@ -1003,6 +1007,7 @@ gas ()
   printf ("#define CLASS_IMM 0x60\n");
   printf ("#define CLASS_CC 0x70\n");
   printf ("#define CLASS_CTRL 0x80\n");
+  printf ("#define CLASS_IGNORE 0x90\n");
   printf ("#define CLASS_ADDRESS 0xd0\n");
   printf ("#define CLASS_0CCC 0xe0\n");
   printf ("#define CLASS_1CCC 0xf0\n");