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| author | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 12:48:26 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-01-17 12:33:08 +0800 |
| commit | 1d458f0843141734b73f3a895dee73626fd85cb3 (patch) | |
| tree | 781ded2aca13f648dafc100081f9463448aad15e /opcodes | |
| parent | ef0802cd1f9bab26b45c370da65c5b4bd6bf580d (diff) | |
| download | gdb-1d458f0843141734b73f3a895dee73626fd85cb3.zip gdb-1d458f0843141734b73f3a895dee73626fd85cb3.tar.gz gdb-1d458f0843141734b73f3a895dee73626fd85cb3.tar.bz2 | |
RISC-V: Support ssctr/smctr extensions with version 1.0.
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
The privileged spec v1.10 already removed the sfence.vm instruction, and the
encoding of sfence.vm instruction is overlapped with the sctrclr instruction
of ssctr/smctr. But since the privileged spec v1.10 already removed the
sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we
had to remove the sfence.vm.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr.
(riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0.
(riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr.
(riscv_multi_subset_supports_ext): Likewise.
gas/
* config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address):
Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR.
(riscv_is_priv_insn): Removed SFENCE_VM check.
* testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no
longer supported since privileged spec v1.10.
* testsuite/gas/riscv/attribute-14.s: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr.s: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr.
* testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction.
* testsuite/gas/riscv/smctr-ssctr.s: Likewise.
include/
* opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed
encoding macro for sfence.vm since encoding conflict. Added CSR
numbers for ssctr/smctr CSRs.
* opcode/riscv.h (enum riscv_insn_class): Added
INSN_CLASS_SMCTR_OR_SSCTR for sctrclr.
opcodes/
* riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm
since encoding conflict.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5680f6f..31f96ab 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2244,13 +2244,14 @@ const struct riscv_opcode riscv_opcodes[] = {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, -{"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, -{"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, {"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, {"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS }, {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, +/* Smctr/Ssctr instruction. */ +{"sctrclr", 0, INSN_CLASS_SMCTR_OR_SSCTR, "", MATCH_SCTRCLR, MASK_SCTRCLR, match_opcode, 0 }, + /* Svinval instructions. */ {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, |