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| author | Jan Beulich <jbeulich@suse.com> | 2023-07-21 08:57:24 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-07-21 08:57:24 +0200 |
| commit | 178e197078e105ba4fc1b40a0bb6d7384098128e (patch) | |
| tree | 396bdbd85ef02e8a680bade165d65ffd3e0cc25c /opcodes | |
| parent | c54748b2fae98907b3f86fd2a3b6b46249759ceb (diff) | |
| download | gdb-178e197078e105ba4fc1b40a0bb6d7384098128e.zip gdb-178e197078e105ba4fc1b40a0bb6d7384098128e.tar.gz gdb-178e197078e105ba4fc1b40a0bb6d7384098128e.tar.bz2 | |
x86: adjust disassembly of insns operating on selector values
Bring disassembly back in line with what the assembler accepts, thus
also making it self-consistent (with, in particular selector load/store
insns). While there further add D to all affected insns except ARPL
(where S is used, matching LAR/LSL), to also behave correctly in suffix-
always mode.
While there also hook up the Intel variant of the LKGS test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-dis.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 179612f..beabe4a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -2625,10 +2625,10 @@ static const struct dis386 reg_table[][8] = { { { "sldtD", { Sv }, 0 }, { "strD", { Sv }, 0 }, - { "lldt", { Ew }, 0 }, - { "ltr", { Ew }, 0 }, - { "verr", { Ew }, 0 }, - { "verw", { Ew }, 0 }, + { "lldtD", { Sv }, 0 }, + { "ltrD", { Sv }, 0 }, + { "verrD", { Sv }, 0 }, + { "verwD", { Sv }, 0 }, { X86_64_TABLE (X86_64_0F00_REG_6) }, { Bad_Opcode }, }, @@ -2875,7 +2875,7 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "lkgs", { Ew }, 0 }, + { "lkgsD", { Sv }, 0 }, }, /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ @@ -4017,7 +4017,7 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_63 */ { - { "arpl", { Ew, Gw }, 0 }, + { "arplS", { Sv, Gv }, 0 }, { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 }, }, |