Add support for 64-bit ARM architecture: aarch64

10 files changed, 174 insertions, 86 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3a0c3b1..7388834 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,32 @@
+2012-08-16  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* Makefile.am: Add AArch64.
+	* Makefile.in: Regenerate.
+	* aarch64-asm.c: New file.
+	* aarch64-asm.h: New file.
+	* aarch64-dis.c: New file.
+	* aarch64-dis.h: New file.
+	* aarch64-gen.c: New file.
+	* aarch64-opc.c: New file.
+	* aarch64-opc.h: New file.
+	* aarch64-tbl.h: New file.
+	* configure.in: Add AArch64.
+	* configure: Regenerate.
+	* disassemble.c: Add AArch64.
+	* aarch64-asm-2.c: New file (automatically generated).
+	* aarch64-dis-2.c: New file (automatically generated).
+	* aarch64-opc-2.c: New file (automatically generated).
+	* po/POTFILES.in: Regenerate.
+
 2012-08-09  Nick Clifton  <nickc@redhat.com>
 
 	* po/vi.po: Updated Vietnamese translation.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index a43aa0d..ef455f1 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -41,6 +41,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
 
 # Header files.
 HFILES = \
+	aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
 	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
 	frv-desc.h frv-opc.h \
@@ -73,6 +74,12 @@ HFILES = \
 # C source files that correspond to .o's ending up in libopcodes
 # for all machines.
 TARGET_LIBOPCODES_CFILES = \
+	aarch64-asm.c \
+	aarch64-asm-2.c \
+	aarch64-dis.c \
+	aarch64-dis-2.c \
+	aarch64-opc.c \
+	aarch64-opc-2.c \
 	alpha-dis.c \
 	alpha-opc.c \
 	arc-dis.c \
@@ -249,6 +256,7 @@ LIBOPCODES_CFILES = \
 # C source files that correspond to .o's.
 CFILES = \
 	$(LIBOPCODES_CFILES) \
+	aarch64-gen.c \
 	i386-gen.c \
 	ia64-asmtab.c \
 	ia64-gen.c \
@@ -480,15 +488,30 @@ stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
 	$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
 		archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
 
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
-	s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
-	opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+	ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+	z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
 
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+	$(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
 	$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
 	$(srcdir)/rl78-decode.c \
 	$(srcdir)/rx-decode.c
 
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+	$(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+	$(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+	$(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
 i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
 	$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
 
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index f5035ea..d295533 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -310,6 +310,7 @@ BFD_H = ../bfd/bfd.h
 
 # Header files.
 HFILES = \
+	aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
 	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
 	frv-desc.h frv-opc.h \
@@ -343,6 +344,12 @@ HFILES = \
 # C source files that correspond to .o's ending up in libopcodes
 # for all machines.
 TARGET_LIBOPCODES_CFILES = \
+	aarch64-asm.c \
+	aarch64-asm-2.c \
+	aarch64-dis.c \
+	aarch64-dis-2.c \
+	aarch64-opc.c \
+	aarch64-opc-2.c \
 	alpha-dis.c \
 	alpha-opc.c \
 	arc-dis.c \
@@ -521,6 +528,7 @@ LIBOPCODES_CFILES = \
 # C source files that correspond to .o's.
 CFILES = \
 	$(LIBOPCODES_CFILES) \
+	aarch64-gen.c \
 	i386-gen.c \
 	ia64-asmtab.c \
 	ia64-gen.c \
@@ -603,11 +611,12 @@ CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x x
 @CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
 @CGEN_MAINT_FALSE@XSTORMY16_DEPS = 
 @CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
-MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \
-	s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
-	opc2c$(EXEEXT_FOR_BUILD)
+MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
+	ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \
+	z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD)
 
-MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
+MAINTAINERCLEANFILES = $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2.c \
+	$(srcdir)/aarch64-opc-2.c $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
 	$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
 	$(srcdir)/rl78-decode.c \
 	$(srcdir)/rx-decode.c
@@ -728,6 +737,12 @@ mostlyclean-compile:
 distclean-compile:
 	-rm -f *.tab.c
 
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc-2.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aarch64-opc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-dis.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alpha-opc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@
@@ -1343,6 +1358,20 @@ stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
 	$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
 		archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
 
+aarch64-gen$(EXEEXT_FOR_BUILD): aarch64-gen.o $(BUILD_LIB_DEPS)
+	$(LINK_FOR_BUILD) aarch64-gen.o $(BUILD_LIBS)
+
+aarch64-gen.o: aarch64-gen.c $(BFD_H) $(INCDIR)/getopt.h $(INCDIR)/libiberty.h\
+	$(INCDIR)/opcode/aarch64.h config.h aarch64-opc.h aarch64-tbl.h
+	$(COMPILE_FOR_BUILD) -c $(srcdir)/aarch64-gen.c
+
+$(srcdir)/aarch64-asm-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-asm > $@
+$(srcdir)/aarch64-dis-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-dis > $@
+$(srcdir)/aarch64-opc-2.c: @MAINT@ aarch64-gen$(exeext_for_build)
+	./aarch64-gen$(exeext_for_build) --gen-opc > $@
+
 i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
 	$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
 
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e10240a..c3e3a4d 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -41,7 +41,6 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
   const aarch64_field *field;
   enum aarch64_field_kind kind;
   va_list va;
-
   va_start (va, mask);
   num = va_arg (va, uint32_t);
   assert (num <= 5);
@@ -58,19 +57,19 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
 /* Operand inserters.  */
 
 /* Insert register number.  */
-const char *
+const char*
 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   insert_field (self->fields[0], code, info->reg.regno, 0);
-  return NULL;
+  return 0;
 }
 
 /* Insert register number, index and/or other data for SIMD register element
    operand, e.g. the last source operand in
      SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
-const char *
+const char*
 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
 		     aarch64_insn *code, const aarch64_inst *inst)
 {
@@ -123,11 +122,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
 	  assert (0);
 	}
     }
-  return NULL;
+  return 0;
 }
 
 /* Insert regno and len field of a register list operand, e.g. Vn in TBL.  */
-const char *
+const char*
 aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
 		     aarch64_insn *code,
 		     const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -136,12 +135,12 @@ aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
   insert_field (self->fields[0], code, info->reglist.first_regno, 0);
   /* len */
   insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
-  return NULL;
+  return 0;
 }
 
 /* Insert Rt and opcode fields for a register list operand, e.g. Vt
    in AdvSIMD load/store instructions.  */
-const char *
+const char*
 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			  const aarch64_opnd_info *info, aarch64_insn *code,
 			  const aarch64_inst *inst)
@@ -179,12 +178,12 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
     }
   insert_field (FLD_opcode, code, value, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
    single structure to all lanes instructions.  */
-const char *
+const char*
 aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst)
@@ -204,12 +203,12 @@ aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
     value = (aarch64_insn) 1;
   insert_field (FLD_S, code, value, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
    operand e.g. Vt in AdvSIMD load/store single element instructions.  */
-const char *
+const char*
 aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			   const aarch64_opnd_info *info, aarch64_insn *code,
 			   const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -252,13 +251,13 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
   gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
   insert_field_2 (&field, code, opcodeh2, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Insert fields immh:immb and/or Q for e.g. the shift immediate in
    SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
    or SSHR <V><d>, <V><n>, #<shift>.  */
-const char *
+const char*
 aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			       const aarch64_opnd_info *info,
 			       aarch64_insn *code, const aarch64_inst *inst)
@@ -307,12 +306,12 @@ aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
     imm = info->imm.value + (8 << (unsigned)val);
   insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
 
-  return NULL;
+  return 0;
 }
 
 /* Insert fields for e.g. the immediate operands in
    BFM <Wd>, <Wn>, #<immr>, #<imms>.  */
-const char *
+const char*
 aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		 aarch64_insn *code,
 		 const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -329,12 +328,12 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
   else
     /* e.g. TBZ b5:b40.  */
     insert_fields (code, imm, 0, 2, self->fields[1], self->fields[0]);
-  return NULL;
+  return 0;
 }
 
 /* Insert immediate and its shift amount for e.g. the last operand in
      MOVZ <Wd>, #<imm16>{, LSL #<shift>}.  */
-const char *
+const char*
 aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
 		      aarch64_insn *code,
 		      const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -343,12 +342,12 @@ aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info
   aarch64_ins_imm (self, info, code, inst);
   /* hw */
   insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
-  return NULL;
+  return 0;
 }
 
 /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
      MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}.  */
-const char *
+const char*
 aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
 				  const aarch64_opnd_info *info,
 				  aarch64_insn *code,
@@ -375,7 +374,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
   insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
 
   if (kind == AARCH64_MOD_NONE)
-    return NULL;
+    return 0;
 
   /* shift amount partially in cmode */
   assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
@@ -398,23 +397,23 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
     }
   insert_field_2 (&field, code, amount, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
    e.g.  SCVTF <Dd>, <Wn>, #<fbits>.  */
-const char *
+const char*
 aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   insert_field (self->fields[0], code, 64 - info->imm.value, 0);
-  return NULL;
+  return 0;
 }
 
 /* Insert arithmetic immediate for e.g. the last operand in
      SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}.  */
-const char *
+const char*
 aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		  aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
@@ -423,12 +422,12 @@ aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
   insert_field (self->fields[0], code, value, 0);
   /* imm12 (unsigned) */
   insert_field (self->fields[1], code, info->imm.value, 0);
-  return NULL;
+  return 0;
 }
 
 /* Insert logical/bitmask immediate for e.g. the last operand in
      ORR <Wd|WSP>, <Wn>, #<imm>.  */
-const char *
+const char*
 aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		  aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
@@ -444,12 +443,12 @@ aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
 
   insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
 		 self->fields[0]);
-  return NULL;
+  return 0;
 }
 
 /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
    or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>.  */
-const char *
+const char*
 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
 		aarch64_insn *code, const aarch64_inst *inst)
 {
@@ -481,23 +480,23 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
       insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
     }
 
-  return NULL;
+  return 0;
 }
 
 /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}].  */
-const char *
+const char*
 aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   /* Rn */
   insert_field (FLD_Rn, code, info->addr.base_regno, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the address operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
-const char *
+const char*
 aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -525,11 +524,11 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
     S = info->shifter.operator_present && info->shifter.amount_present;
   insert_field (FLD_S, code, S, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!.  */
-const char *
+const char*
 aarch64_ins_addr_simm (const aarch64_operand *self,
 		       const aarch64_opnd_info *info,
 		       aarch64_insn *code, const aarch64_inst *inst)
@@ -556,28 +555,27 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
 	insert_field (self->fields[1], code, 1, 0);
     }
 
-  return NULL;
+  return 0;
 }
 
 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}].  */
-const char *
+const char*
 aarch64_ins_addr_uimm12 (const aarch64_operand *self,
 			 const aarch64_opnd_info *info,
 			 aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
-
   /* Rn */
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   /* uimm12 */
   insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the address operand for e.g.
      LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>.  */
-const char *
+const char*
 aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -589,22 +587,22 @@ aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
     insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
   else
     insert_field (FLD_Rm, code, 0x1f, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>.  */
-const char *
+const char*
 aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		  const aarch64_opnd_info *info, aarch64_insn *code,
 		  const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   /* cond */
   insert_field (FLD_cond, code, info->cond->value, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>.  */
-const char *
+const char*
 aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		    const aarch64_opnd_info *info, aarch64_insn *code,
 		    const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -612,11 +610,11 @@ aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* op0:op1:CRn:CRm:op2 */
   insert_fields (code, info->sysreg, inst->opcode->mask, 5,
 		 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>.  */
-const char *
+const char*
 aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -624,11 +622,11 @@ aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* op1:op2 */
   insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
 		 FLD_op2, FLD_op1);
-  return NULL;
+  return 0;
 }
 
 /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>.  */
-const char *
+const char*
 aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		       const aarch64_opnd_info *info, aarch64_insn *code,
 		       const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -636,37 +634,37 @@ aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* op1:CRn:CRm:op2 */
   insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
 		 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
-  return NULL;
+  return 0;
 }
 
 /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>.  */
 
-const char *
+const char*
 aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		     const aarch64_opnd_info *info, aarch64_insn *code,
 		     const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   /* CRm */
   insert_field (FLD_CRm, code, info->barrier->value, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the prefetch operation option operand for e.g.
      PRFM <prfop>, [<Xn|SP>{, #<pimm>}].  */
 
-const char *
+const char*
 aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		   const aarch64_opnd_info *info, aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
   /* prfop in Rt */
   insert_field (FLD_Rt, code, info->prfop->value, 0);
-  return NULL;
+  return 0;
 }
 
 /* Encode the extended register operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
-const char *
+const char*
 aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			  const aarch64_opnd_info *info, aarch64_insn *code,
 			  const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -684,12 +682,12 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* imm3 */
   insert_field (FLD_imm3, code, info->shifter.amount, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Encode the shifted register operand for e.g.
      SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}.  */
-const char *
+const char*
 aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
@@ -702,7 +700,7 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* imm6 */
   insert_field (FLD_imm6, code, info->shifter.amount, 0);
 
-  return NULL;
+  return 0;
 }
 
 /* Miscellaneous encoding functions.  */
@@ -984,7 +982,6 @@ static void
 convert_bfx_to_bfm (aarch64_inst *inst)
 {
   int64_t lsb, width;
-
   /* Convert the operand.  */
   lsb = inst->operands[2].imm.value;
   width = inst->operands[3].imm.value;
@@ -1001,7 +998,6 @@ static void
 convert_bfi_to_bfm (aarch64_inst *inst)
 {
   int64_t lsb, width;
-
   /* Convert the operand.  */
   lsb = inst->operands[2].imm.value;
   width = inst->operands[3].imm.value;
@@ -1026,7 +1022,6 @@ static void
 convert_lsl_to_ubfm (aarch64_inst *inst)
 {
   int64_t shift = inst->operands[2].imm.value;
-
   if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
     {
       inst->operands[2].imm.value = (32 - shift) & 0x1f;
@@ -1117,7 +1112,6 @@ static void
 convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
 {
   const aarch64_opcode *alias = inst->opcode;
-
   if ((alias->flags & F_CONV) == 0)
     goto convert_to_real_return;
 
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 84b7b0a..d6bfc9d 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -135,7 +135,6 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...)
   const aarch64_field *field;
   enum aarch64_field_kind kind;
   va_list va;
-
   va_start (va, mask);
   num = va_arg (va, uint32_t);
   assert (num <= 5);
@@ -155,7 +154,6 @@ static inline int32_t
 sign_extend (aarch64_insn value, unsigned i)
 {
   uint32_t ret = value;
-
   assert (i < 32);
   if ((value >> i) & 0x1)
     {
@@ -183,7 +181,6 @@ static inline enum aarch64_opnd_qualifier
 get_vreg_qualifier_from_value (aarch64_insn value)
 {
   enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
-
   assert (value <= 0x8
 	  && aarch64_get_qualifier_standard_value (qualifier) == value);
   return qualifier;
@@ -194,7 +191,6 @@ static inline enum aarch64_opnd_qualifier
 get_sreg_qualifier_from_value (aarch64_insn value)
 {
   enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
-
   assert (value <= 0x4
 	  && aarch64_get_qualifier_standard_value (qualifier) == value);
   return qualifier;
@@ -257,7 +253,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
   info->reglane.regno = extract_field (self->fields[0], code,
 				       inst->opcode->mask);
 
-  /* Index and/or type.  */
+  /* index and/or type */
   if (inst->opcode->iclass == asisdone
     || inst->opcode->iclass == asimdins)
     {
@@ -294,7 +290,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
     }
   else
     {
-      /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
+      /* index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
          or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
 
       /* Need information in other operand(s) to help decoding.  */
@@ -719,7 +715,7 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
     return 0;
 
   /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
-     (in other words, right rotated by R), then replicated.  */
+     (in other words, right rotated by R), then replicated. */
   if (N != 0)
     {
       simd_size = 64;
@@ -2074,7 +2070,7 @@ print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
 	 suffix.  */
       char name[8], *ptr;
       size_t len;
-
+      
       ptr = strchr (inst->opcode->name, '.');
       assert (ptr && inst->cond);
       len = ptr - inst->opcode->name;
@@ -2133,7 +2129,7 @@ print_insn_aarch64_word (bfd_vma pc,
 
   if (((word >> 21) & 0x3ff) == 1)
     {
-      /* RESERVED for ALES.  */
+      /* RESERVED for ALES. */
       assert (ret != ERR_OK);
       ret = ERR_NYI;
     }
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index 95bd016..b087236 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -351,7 +351,7 @@ divide_table_1_finish:
 
 /* Call divide_table_1 to divide the all the opcodes and thus create the
    decoding decision tree.  */
-static struct bittree *
+static struct bittree*
 divide_table (void)
 {
   struct bittree *bittree = new_bittree_node ();
@@ -361,7 +361,7 @@ divide_table (void)
 
 /* Read in all of the tables, create the decoding decision tree and return
    the tree root.  */
-static struct bittree *
+static struct bittree*
 initialize_decoder_tree (void)
 {
   int i;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 2d66a25..68572f8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -206,7 +206,7 @@ aarch64_get_operand_class (enum aarch64_opnd type)
   return aarch64_operands[type].op_class;
 }
 
-const char *
+const char*
 aarch64_get_operand_name (enum aarch64_opnd type)
 {
   return aarch64_operands[type].name;
@@ -214,7 +214,7 @@ aarch64_get_operand_name (enum aarch64_opnd type)
 
 /* Get operand description string.
    This is usually for the diagnosis purpose.  */
-const char *
+const char*
 aarch64_get_operand_desc (enum aarch64_opnd type)
 {
   return aarch64_operands[type].desc;
@@ -241,14 +241,14 @@ const aarch64_cond aarch64_conds[16] =
   {{"nv"}, 0xf},
 };
 
-const aarch64_cond *
+const aarch64_cond*
 get_cond_from_value (aarch64_insn value)
 {
   assert (value < 16);
   return &aarch64_conds[(unsigned int) value];
 }
 
-const aarch64_cond *
+const aarch64_cond*
 get_inverted_cond (const aarch64_cond *cond)
 {
   return &aarch64_conds[cond->value ^ 0x1];
@@ -1061,7 +1061,7 @@ aarch64_logical_immediate_p (uint64_t value, int is32, aarch64_insn *encoding)
   if (is32)
     {
       /* Allow all zeros or all ones in top 32-bits, so that
-	 constant expressions like ~1 are permitted.  */
+	 constant expressions like ~1 are permitted. */
       if (value >> 32 != 0 && value >> 32 != 0xffffffff)
 	return 0xffffffff;
       /* Replicate the 32 lower bits to the 32 upper bits.  */
@@ -1578,7 +1578,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 		{
 		case OP_MOV_IMM_WIDEN:
 		  imm = ~imm;
-		  /* Fall through...  */
+		  /* Fall through... */
 		case OP_MOV_IMM_WIDE:
 		  if (!aarch64_wide_constant_p (imm, is32, NULL))
 		    {
diff --git a/opcodes/configure b/opcodes/configure
index dbfca48..c7e80b1 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12440,6 +12440,7 @@ if test x${all_targets} = xfalse ; then
 	ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
 	archdefs="$archdefs -DARCH_$ad"
 	case "$arch" in
+	bfd_aarch64_arch)	ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
 	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index dadfe4a..c91cf80 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -229,6 +229,7 @@ if test x${all_targets} = xfalse ; then
 	ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g`
 	archdefs="$archdefs -DARCH_$ad"
 	case "$arch" in
+	bfd_aarch64_arch)	ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
 	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 3dad64b..c5887b0 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -24,6 +24,7 @@
 #include "dis-asm.h"
 
 #ifdef ARCH_all
+#define ARCH_aarch64
 #define ARCH_alpha
 #define ARCH_arc
 #define ARCH_arm
@@ -113,6 +114,11 @@ disassembler (abfd)
     {
       /* If you add a case to this table, also add it to the
 	 ARCH_all definition right above this function.  */
+#ifdef ARCH_aarch64
+    case bfd_arch_aarch64:
+      disassemble = print_insn_aarch64;
+      break;
+#endif
 #ifdef ARCH_alpha
     case bfd_arch_alpha:
       disassemble = print_insn_alpha;
@@ -516,6 +522,9 @@ void
 disassembler_usage (stream)
      FILE * stream ATTRIBUTE_UNUSED;
 {
+#ifdef ARCH_aarch64
+  print_aarch64_disassembler_options (stream);
+#endif
 #ifdef ARCH_arm
   print_arm_disassembler_options (stream);
 #endif
@@ -543,6 +552,12 @@ disassemble_init_for_target (struct disassemble_info * info)
 
   switch (info->arch)
     {
+#ifdef ARCH_aarch64
+    case bfd_arch_aarch64:
+      info->symbol_is_valid = aarch64_symbol_is_valid;
+      info->disassembler_needs_relocs = TRUE;
+      break;
+#endif
 #ifdef ARCH_arm
     case bfd_arch_arm:
       info->symbol_is_valid = arm_symbol_is_valid;