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authorTristan Gingold <gingold@adacore.com>2012-09-04 14:38:06 +0000
committerTristan Gingold <gingold@adacore.com>2012-09-04 14:38:06 +0000
commitca3c507e0cbc563b516418e7bbe805010fba8b4e (patch)
tree9fb16a472d7cdd5f5bc488755772e10b2a746259 /opcodes
parent14f89945d7c6d19e0fc76cda7dc694274499ab42 (diff)
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bfd/
2012-08-09 Maciej W. Rozycki <macro@codesourcery.com> * elfxx-mips.c (LA25_LUI_MICROMIPS_1, LA25_LUI_MICROMIPS_2): Remove macros, folding them into... (LA25_LUI_MICROMIPS): ... this new macro. (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise into... (LA25_J_MICROMIPS): ... this new macro. (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise into... (LA25_ADDIU_MICROMIPS): ... this new macro. (bfd_put_micromips_32, bfd_get_micromips_32): New functions. (mips_elf_create_la25_stub): Use them. (check_br32_dslot, check_br32, check_relocated_bzc): Likewise. (_bfd_mips_elf_relax_section): Likewise. gas/ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros. (is_opcode_valid): Remove coprocessor instruction exclusions. Replace OPCODE_IS_MEMBER with opcode_is_member. (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with opcode_is_member. (macro): Remove coprocessor instruction exclusions. gas/ * gas/mips/mips.exp: Set has_newabi for all Linux targets. * gas/mips/cfi-n64-1.d: Adjust for targets that do not infer the ISA from the ABI. * gas/mips/elf-rel-got-n32.d: Likewise. * gas/mips/elf-rel-got-n64.d: Likewise. * gas/mips/elf-rel-xgot-n32.d: Likewise. * gas/mips/elf-rel-xgot-n64.d: Likewise. * gas/mips/elf-rel18.d: Likewise. * gas/mips/elf-rel28-n32.d: Likewise. * gas/mips/elf-rel28-n64.d: Likewise. * gas/mips/jal-newabi.d: Likewise. * gas/mips/ldstla-n64-shared.d: Likewise. * gas/mips/ldstla-n64-sym32.d: Likewise. * gas/mips/ldstla-n64.d: Likewise. * gas/mips/macro-warn-1-n32.d: Likewise. * gas/mips/macro-warn-2-n32.d: Likewise. * gas/mips/n32-consec.d: Likewise. include/ 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (mips_opcode): Add the exclusions field. (OPCODE_IS_MEMBER): Remove macro. (cpu_is_member): New inline function. (opcode_is_member): Likewise. ld/ * emulparams/elf32bmip.sh: Make _gp hidden. * emulparams/elf32bmipn32-defs.sh: Likewise. * emulparams/elf32mipswindiss.sh: Likewise. * scripttempl/mips.sc: Likewise. ld/ 2012-08-28 Maciej W. Rozycki <macro@codesourcery.com> * ld-elf/export-class.sd: New test. * ld-elf/export-class.vd: New test. * ld-elf/export-class-def.s: New test source. * ld-elf/export-class-dep.s: New test source. * ld-elf/export-class-lib.s: New test source. * ld-elf/export-class-ref.s: New test source. * ld-elf/export-class-lib.ver: New test version script. * ld-elf/export-class.exp: New test script. * ld-arm/arm-export-class.rd: New test. * ld-arm/arm-export-class.xd: New test. * ld-arm/export-class.exp: New test script. * ld-i386/i386-export-class.rd: New test. * ld-i386/i386-export-class.xd: New test. * ld-i386/export-class.exp: New test script. * ld-mips-elf/mips-32-export-class.rd: New test. * ld-mips-elf/mips-32-export-class.xd: New test. * ld-mips-elf/mips-64-export-class.rd: New test. * ld-mips-elf/mips-64-export-class.xd: New test. * ld-mips-elf/export-class.exp: New test script. * ld-powerpc/powerpc-32-export-class.rd: New test. * ld-powerpc/powerpc-32-export-class.xd: New test. * ld-powerpc/powerpc-64-export-class.rd: New test. * ld-powerpc/powerpc-64-export-class.xd: New test. * ld-powerpc/export-class.exp: New test script. * ld-x86-64/x86-64-64-export-class.rd: New test. * ld-x86-64/x86-64-x32-export-class.rd: New test. * ld-x86-64/export-class.exp: New test script. opcodes/ 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com> * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses, update the type of the variable used to hold the instruction word. (print_insn_mips, print_mips16_insn_arg): Likewise. (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use local variables for info struct member accesses. (print_insn_micromips): Add GET_OP_S local macro. (_print_insn_mips): Update the type of the variable used to hold the instruction word.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog32
-rw-r--r--opcodes/Makefile.am10
-rw-r--r--opcodes/Makefile.in11
-rw-r--r--opcodes/aclocal.m41
-rwxr-xr-xopcodes/configure50
-rw-r--r--opcodes/configure.in2
-rw-r--r--opcodes/micromips-opc.c2
-rw-r--r--opcodes/mips-dis.c572
-rw-r--r--opcodes/mips-opc.c182
9 files changed, 428 insertions, 434 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0a45bd1..384de9b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,35 @@
+2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
+ macros, use local variables for info struct member accesses,
+ update the type of the variable used to hold the instruction
+ word.
+ (print_insn_mips, print_mips16_insn_arg): Likewise.
+ (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
+ local variables for info struct member accesses.
+ (print_insn_micromips): Add GET_OP_S local macro.
+ (_print_insn_mips): Update the type of the variable used to hold
+ the instruction word.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Update comment.
+ * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
+ instructions for IOCT as appropriate.
+ * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
+ the result of a check for the -Wno-missing-field-initializers
+ GCC option.
+ * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
+ (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
+ compilation.
+ (mips16-opc.lo): Likewise.
+ (micromips-opc.lo): Likewise.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * Makefile.in: Regenerate.
+
2012-08-01 Alan Modra <amodra@gmail.com>
* h8300-dis.c: Fix printf arg warnings.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index ef455f1..3e6ceeb 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -11,6 +11,7 @@ BFDDIR = $(srcdir)/../bfd
WARN_CFLAGS = @WARN_CFLAGS@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
AM_CFLAGS = $(WARN_CFLAGS)
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \
@@ -551,6 +552,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index d295533..56d4734 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -54,6 +54,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/override.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
+ $(top_srcdir)/../config/warnings.m4 \
$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.in
@@ -195,6 +196,7 @@ MSGMERGE = @MSGMERGE@
NM = @NM@
NMEDIT = @NMEDIT@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
@@ -1406,6 +1408,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4
index df10cc0..0f36783 100644
--- a/opcodes/aclocal.m4
+++ b/opcodes/aclocal.m4
@@ -978,6 +978,7 @@ m4_include([../config/nls.m4])
m4_include([../config/override.m4])
m4_include([../config/po.m4])
m4_include([../config/progtest.m4])
+m4_include([../config/warnings.m4])
m4_include([../libtool.m4])
m4_include([../ltoptions.m4])
m4_include([../ltsugar.m4])
diff --git a/opcodes/configure b/opcodes/configure
index f3382bd..0f0073d 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -640,6 +640,7 @@ INSTALL_LIBBFD_TRUE
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
+NO_WMISSING_FIELD_INITIALIZERS
NO_WERROR
WARN_CFLAGS
OTOOL64
@@ -11134,7 +11135,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11137 "configure"
+#line 11138 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11240,7 +11241,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11243 "configure"
+#line 11244 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -11561,6 +11562,51 @@ fi
+NO_WMISSING_FIELD_INITIALIZERS=
+save_CFLAGS="$CFLAGS"
+for real_option in -Wno-missing-field-initializers; do
+ # Do the check with the no- prefix removed since gcc silently
+ # accepts any -Wno-* option on purpose
+ case $real_option in
+ -Wno-*) option=-W`expr x$real_option : 'x-Wno-\(.*\)'` ;;
+ *) option=$real_option ;;
+ esac
+ as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh`
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5
+$as_echo_n "checking whether $CC supports $option... " >&6; }
+if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ CFLAGS="$option"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ eval "$as_acx_Woption=yes"
+else
+ eval "$as_acx_Woption=no"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+eval ac_res=\$$as_acx_Woption
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+ if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then :
+ NO_WMISSING_FIELD_INITIALIZERS="$NO_WMISSING_FIELD_INITIALIZERS${NO_WMISSING_FIELD_INITIALIZERS:+ }$real_option"
+fi
+ done
+CFLAGS="$save_CFLAGS"
+
ac_config_headers="$ac_config_headers config.h:config.in"
diff --git a/opcodes/configure.in b/opcodes/configure.in
index ee7813f..cb5a048 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -42,6 +42,8 @@ AC_ARG_ENABLE(targets,
esac])dnl
AM_BINUTILS_WARNINGS
+ACX_PROG_CC_WARNING_OPTS([-Wno-missing-field-initializers],
+ [NO_WMISSING_FIELD_INITIALIZERS])
AC_CONFIG_HEADERS(config.h:config.in)
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index a15982d..b4982cc 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -115,7 +115,7 @@ const struct mips_opcode micromips_opcodes[] =
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 8f8a5d7..f4a10ee 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -930,16 +930,23 @@ lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
static void
print_insn_args (const char *d,
- register unsigned long int l,
+ int l,
bfd_vma pc,
struct disassemble_info *info,
const struct mips_opcode *opp)
{
- int op, delta;
+ const fprintf_ftype infprintf = info->fprintf_func;
unsigned int lsb, msb, msbd;
+ void *is = info->stream;
+ int op;
lsb = 0;
+#define GET_OP(insn, field) \
+ (((insn) >> OP_SH_##field) & OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
+ - ((OP_MASK_##field >> 1) + 1))
for (; *d != '\0'; d++)
{
switch (*d)
@@ -949,7 +956,7 @@ print_insn_args (const char *d,
case ')':
case '[':
case ']':
- (*info->fprintf_func) (info->stream, "%c", *d);
+ infprintf (is, "%c", *d);
break;
case '+':
@@ -959,44 +966,41 @@ print_insn_args (const char *d,
{
case '\0':
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, incomplete extension sequence (+)"));
+ infprintf (is,
+ _("# internal error, "
+ "incomplete extension sequence (+)"));
return;
case 'A':
- lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT);
+ infprintf (is, "0x%x", lsb);
break;
case 'B':
- msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB);
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI1) & OP_MASK_UDI1);
+ infprintf (is, "0x%x", GET_OP (l, UDI1));
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI2) & OP_MASK_UDI2);
+ infprintf (is, "0x%x", GET_OP (l, UDI2));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI3) & OP_MASK_UDI3);
+ infprintf (is, "0x%x", GET_OP (l, UDI3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI4) & OP_MASK_UDI4);
+ infprintf (is, "0x%x", GET_OP (l, UDI4));
break;
case 'C':
case 'H':
- msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD);
+ infprintf (is, "0x%x", msbd + 1);
break;
case 'D':
@@ -1004,8 +1008,8 @@ print_insn_args (const char *d,
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RD);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mtcN (et al.), to be
printed textually if known. If not known, print both
@@ -1015,31 +1019,29 @@ print_insn_args (const char *d,
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'E':
- lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT) + 32;
+ infprintf (is, "0x%x", lsb);
break;
case 'F':
- msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB) + 32;
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case 'G':
- msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD) + 32;
+ infprintf (is, "0x%x", msbd + 1);
break;
case 't': /* Coprocessor 0 reg name */
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RT) &
- OP_MASK_RT]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
break;
case 'T': /* Coprocessor 0 reg name */
@@ -1047,8 +1049,8 @@ print_insn_args (const char *d,
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RT);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mftc0, to be
printed textually if known. If not known, print both
@@ -1058,228 +1060,173 @@ print_insn_args (const char *d,
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'x': /* bbit bit index */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
+ infprintf (is, "0x%x", GET_OP (l, BBITIND));
break;
case 'p': /* cins, cins32, exts and exts32 position */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
+ infprintf (is, "0x%x", GET_OP (l, CINSPOS));
break;
case 's': /* cins and exts length-minus-one */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'S': /* cins32 and exts32 length-minus-one field */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'Q': /* seqi/snei immediate field */
- op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
- /* Sign-extend it. */
- op = (op ^ 512) - 512;
- (*info->fprintf_func) (info->stream, "%d", op);
+ infprintf (is, "%d", GET_OP_S (l, SEQI));
break;
case 'a': /* 8-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_A;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
break;
case 'b': /* 8-bit signed offset in bit 3 */
- delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_B;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
break;
case 'c': /* 9-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
- if (delta & 0x100)
- delta |= ~OP_MASK_OFFSET_C;
/* Left shift 4 bits to print the real offset. */
- (*info->fprintf_func) (info->stream, "%d", delta << 4);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined extension sequence (+%c)"),
- *d);
+ infprintf (is,
+ _("# internal error, "
+ "undefined extension sequence (+%c)"),
+ *d);
return;
}
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BP) & OP_MASK_BP);
+ infprintf (is, "0x%x", GET_OP (l, BP));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA3) & OP_MASK_SA3);
+ infprintf (is, "0x%x", GET_OP (l, SA3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA4) & OP_MASK_SA4);
+ infprintf (is, "0x%x", GET_OP (l, SA4));
break;
case '5':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMM8) & OP_MASK_IMM8);
+ infprintf (is, "0x%x", GET_OP (l, IMM8));
break;
case '6':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RS) & OP_MASK_RS);
+ infprintf (is, "0x%x", GET_OP (l, RS));
break;
case '7':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC));
break;
case '8':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
+ infprintf (is, "0x%x", GET_OP (l, WRDSP));
break;
case '9':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
break;
case '0': /* dsp 6-bit signed immediate in bit 20 */
- delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
- if (delta & 0x20) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT));
break;
case ':': /* dsp 7-bit signed immediate in bit 19 */
- delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
- if (delta & 0x40) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT_7;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
break;
case '~':
- delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
- if (delta & 0x800)
- delta |= ~0x7ff;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET12));
break;
case '\\':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
+ infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
break;
case '\'':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
+ infprintf (is, "0x%x", GET_OP (l, RDDSP));
break;
case '@': /* dsp 10-bit signed immediate in bit 16 */
- delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
- if (delta & 0x200) /* test sign bit */
- delta |= ~OP_MASK_IMM10;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, IMM10));
break;
case '!':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ infprintf (is, "%d", GET_OP (l, MT_U));
break;
case '$':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ infprintf (is, "%d", GET_OP (l, MT_H));
break;
case '*':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
break;
case '&':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
break;
case 'g':
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 's':
case 'b':
case 'r':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
break;
case 't':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
break;
case 'i':
case 'u':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
+ infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
break;
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- (*info->fprintf_func) (info->stream, "%d",
- delta);
+ infprintf (is, "%d", GET_OP_S (l, DELTA));
break;
case 'h':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_PREFX)
- & OP_MASK_PREFX));
+ infprintf (is, "0x%x", GET_OP (l, PREFX));
break;
case 'k':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_CACHE)
- & OP_MASK_CACHE));
+ infprintf (is, "0x%x", GET_OP (l, CACHE));
break;
case 'a':
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
- | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
+ | (GET_OP (l, TARGET) << 2));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (opp->name, "jalx") == 0)
@@ -1289,97 +1236,80 @@ print_insn_args (const char *d,
case 'p':
/* Sign extend the displacement. */
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- info->target = (delta << 2) + pc + INSNLEN;
+ info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
(*info->print_address_func) (info->target, info);
break;
case 'd':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
break;
case 'U':
{
/* First check for both rd and rt being equal. */
- unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
- if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ unsigned int reg = GET_OP (l, RD);
+ if (reg == GET_OP (l, RT))
+ infprintf (is, "%s", mips_gpr_names[reg]);
else
{
/* If one is zero use the other. */
if (reg == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
+ else if (GET_OP (l, RT) == 0)
+ infprintf (is, "%s", mips_gpr_names[reg]);
else /* Bogus, result depends on processor. */
- (*info->fprintf_func) (info->stream, "%s or %s",
- mips_gpr_names[reg],
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s or %s",
+ mips_gpr_names[reg],
+ mips_gpr_names[GET_OP (l, RT)]);
}
}
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case '<':
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
+ infprintf (is, "0x%x", GET_OP (l, SHAMT));
break;
case 'c':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE) & OP_MASK_CODE);
+ infprintf (is, "0x%x", GET_OP (l, CODE));
break;
case 'q':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE2) & OP_MASK_CODE2);
+ infprintf (is, "0x%x", GET_OP (l, CODE2));
break;
case 'C':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_COPZ) & OP_MASK_COPZ);
+ infprintf (is, "0x%x", GET_OP (l, COPZ));
break;
case 'B':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ infprintf (is, "0x%x", GET_OP (l, CODE20));
break;
case 'J':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE19) & OP_MASK_CODE19);
+ infprintf (is, "0x%x", GET_OP (l, CODE19));
break;
case 'S':
case 'V':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
break;
case 'T':
case 'W':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
break;
case 'D':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
break;
case 'E':
@@ -1390,8 +1320,7 @@ print_insn_args (const char *d,
'T' format. Therefore, until we gain understanding of
cp2 register names, we can simply print the register
numbers. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RT) & OP_MASK_RT);
+ infprintf (is, "$%d", GET_OP (l, RT));
break;
case 'G':
@@ -1399,60 +1328,50 @@ print_insn_args (const char *d,
that FPU (cp1) instructions disassemble this field using
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3. */
- op = (l >> OP_SH_OP) & OP_MASK_OP;
+ op = GET_OP (l, OP);
if (op == OP_OP_COP0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]);
else
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 'K':
- (*info->fprintf_func) (info->stream, "%s",
- mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
break;
case 'N':
- (*info->fprintf_func) (info->stream,
- ((opp->pinfo & (FP_D | FP_S)) != 0
- ? "$fcc%ld" : "$cc%ld"),
- (l >> OP_SH_BCC) & OP_MASK_BCC);
+ infprintf (is,
+ (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
+ GET_OP (l, BCC));
break;
case 'M':
- (*info->fprintf_func) (info->stream, "$fcc%ld",
- (l >> OP_SH_CCC) & OP_MASK_CCC);
+ infprintf (is, "$fcc%d", GET_OP (l, CCC));
break;
case 'P':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
+ infprintf (is, "%d", GET_OP (l, PERFREG));
break;
case 'e':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
+ infprintf (is, "%d", GET_OP (l, VECBYTE));
break;
case '%':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
+ infprintf (is, "%d", GET_OP (l, VECALIGN));
break;
case 'H':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_SEL) & OP_MASK_SEL);
+ infprintf (is, "%d", GET_OP (l, SEL));
break;
case 'O':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_ALN) & OP_MASK_ALN);
+ infprintf (is, "%d", GET_OP (l, ALN));
break;
case 'Q':
{
- unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+ unsigned int vsel = GET_OP (l, VSEL);
if ((vsel & 0x10) == 0)
{
@@ -1462,43 +1381,34 @@ print_insn_args (const char *d,
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
- (*info->fprintf_func) (info->stream, "$v%ld[%d]",
- (l >> OP_SH_FT) & OP_MASK_FT,
- vsel >> 1);
+ infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
}
else if ((vsel & 0x08) == 0)
{
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
}
else
{
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "0x%x", GET_OP (l, FT));
}
}
break;
case 'X':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FD) & OP_MASK_FD);
+ infprintf (is, "$v%d", GET_OP (l, FD));
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FS) & OP_MASK_FS);
+ infprintf (is, "$v%d", GET_OP (l, FS));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined modifier (%c)"),
- *d);
+ infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
return;
}
}
@@ -1511,12 +1421,14 @@ print_insn_args (const char *d,
static int
print_insn_mips (bfd_vma memaddr,
- unsigned long int word,
+ int word,
struct disassemble_info *info)
{
+ static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op;
static bfd_boolean init = 0;
- static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ void *is = info->stream;
/* Build a hash table to shorten the search time. */
if (! init)
@@ -1530,7 +1442,7 @@ print_insn_mips (bfd_vma memaddr,
if (op->pinfo == INSN_MACRO
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
- if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
+ if (i == GET_OP (op->match, OP))
{
mips_hash[i] = op;
break;
@@ -1550,7 +1462,7 @@ print_insn_mips (bfd_vma memaddr,
info->target = 0;
info->target2 = 0;
- op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
+ op = mips_hash[GET_OP (word, OP)];
if (op != NULL)
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
@@ -1562,7 +1474,7 @@ print_insn_mips (bfd_vma memaddr,
const char *d;
/* We always allow to disassemble the jalx instruction. */
- if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
+ if (!opcode_is_member (op, mips_isa, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
@@ -1589,12 +1501,12 @@ print_insn_mips (bfd_vma memaddr,
| INSN_LOAD_MEMORY_DELAY)) != 0)
info->insn_type = dis_dref;
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
d = op->args;
if (d != NULL && *d != '\0')
{
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
print_insn_args (d, word, memaddr, info, op);
}
@@ -1602,10 +1514,12 @@ print_insn_mips (bfd_vma memaddr,
}
}
}
+#undef GET_OP_S
+#undef GET_OP
/* Handle undefined instructions. */
info->insn_type = dis_noninsn;
- (*info->fprintf_func) (info->stream, "0x%lx", word);
+ infprintf (is, "0x%x", word);
return INSNLEN;
}
@@ -1620,65 +1534,62 @@ print_mips16_insn_arg (char type,
bfd_vma memaddr,
struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
+
+#define GET_OP(insn, field) \
+ (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
+ - ((MIPS16OP_MASK_##field >> 1) + 1))
switch (type)
{
case ',':
case '(':
case ')':
- (*info->fprintf_func) (info->stream, "%c", type);
+ infprintf (is, "%c", type);
break;
case 'y':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RY)
- & MIPS16OP_MASK_RY)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
break;
case 'x':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RX)
- & MIPS16OP_MASK_RX)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RZ)
- & MIPS16OP_MASK_RZ)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
- & MIPS16OP_MASK_MOVE32Z)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
break;
case '0':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case 'S':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
+ infprintf (is, "%s", mips_gpr_names[29]);
break;
case 'P':
- (*info->fprintf_func) (info->stream, "$pc");
+ infprintf (is, "$pc");
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
+ infprintf (is, "%s", mips_gpr_names[31]);
break;
case 'X':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
- & MIPS16OP_MASK_REGR32)]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
+ infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
break;
case '<':
@@ -1716,51 +1627,51 @@ print_mips16_insn_arg (char type,
{
case '<':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 5;
extu = 1;
break;
case '>':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 5;
extu = 1;
break;
case '[':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 6;
extu = 1;
break;
case ']':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 6;
extu = 1;
break;
case '4':
nbits = 4;
- immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
+ immed = GET_OP (l, IMM4);
signedp = 1;
extbits = 15;
break;
case '5':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 1;
break;
case 'H':
nbits = 5;
shift = 1;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 2;
break;
case 'W':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
&& (op->pinfo & MIPS16_INSN_READ_SP) == 0)
{
@@ -1771,27 +1682,27 @@ print_mips16_insn_arg (char type,
case 'D':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'j':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
signedp = 1;
break;
case '6':
nbits = 6;
- immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ immed = GET_OP (l, IMM6);
break;
case '8':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
break;
case 'V':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
/* FIXME: This might be lw, or it might be addiu to $sp or
$pc. We assume it's load. */
info->insn_type = dis_dref;
@@ -1800,36 +1711,36 @@ print_mips16_insn_arg (char type,
case 'C':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'U':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
extu = 1;
break;
case 'k':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'K':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'p':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
pcrel = 1;
branch = 1;
break;
case 'q':
nbits = 11;
- immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
+ immed = GET_OP (l, IMM11);
signedp = 1;
pcrel = 1;
branch = 1;
@@ -1837,7 +1748,7 @@ print_mips16_insn_arg (char type,
case 'A':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
pcrel = 1;
/* FIXME: This can be lw or la. We assume it is lw. */
info->insn_type = dis_dref;
@@ -1846,7 +1757,7 @@ print_mips16_insn_arg (char type,
case 'B':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
info->insn_type = dis_dref;
info->data_size = 8;
@@ -1854,7 +1765,7 @@ print_mips16_insn_arg (char type,
case 'E':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
break;
default:
@@ -1884,7 +1795,7 @@ print_mips16_insn_arg (char type,
}
if (! pcrel)
- (*info->fprintf_func) (info->stream, "%d", immed);
+ infprintf (is, "%d", immed);
else
{
bfd_vma baseaddr;
@@ -1962,51 +1873,43 @@ print_mips16_insn_arg (char type,
need_comma = 0;
- l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ l = GET_OP (l, IMM6);
amask = (l >> 3) & 7;
if (amask > 0 && amask < 5)
{
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (amask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[amask + 3]);
+ infprintf (is, "-%s", mips_gpr_names[amask + 3]);
need_comma = 1;
}
smask = (l >> 1) & 3;
if (smask == 3)
{
- (*info->fprintf_func) (info->stream, "%s??",
- need_comma ? "," : "");
+ infprintf (is, "%s??", need_comma ? "," : "");
need_comma = 1;
}
else if (smask > 0)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[16]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
if (smask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[smask + 15]);
+ infprintf (is, "-%s", mips_gpr_names[smask + 15]);
need_comma = 1;
}
if (l & 1)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[31]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
need_comma = 1;
}
if (amask == 5 || amask == 6)
{
- (*info->fprintf_func) (info->stream, "%s$f0",
- need_comma ? "," : "");
+ infprintf (is, "%s$f0", need_comma ? "," : "");
if (amask == 6)
- (*info->fprintf_func) (info->stream, "-$f1");
+ infprintf (is, "-$f1");
}
}
break;
@@ -2043,10 +1946,9 @@ print_mips16_insn_arg (char type,
}
if (args > 0) {
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (args > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[4 + args - 1]);
+ infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
need_comma = 1;
}
@@ -2054,12 +1956,10 @@ print_mips16_insn_arg (char type,
if (framesz == 0 && !use_extend)
framesz = 128;
- (*info->fprintf_func) (info->stream, "%s%d",
- need_comma ? "," : "",
- framesz);
+ infprintf (is, "%s%d", need_comma ? "," : "", framesz);
if (l & 0x40) /* $ra */
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
+ infprintf (is, ",%s", mips_gpr_names[31]);
nsreg = (l >> 24) & 0x7;
smask = 0;
@@ -2075,34 +1975,32 @@ print_mips16_insn_arg (char type,
{
if (smask & (1 << i))
{
- (*info->fprintf_func) (info->stream, ",%s",
- mips_gpr_names[i == 8 ? 30 : (16 + i)]);
+ infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
/* Skip over string of set bits. */
for (j = i; smask & (2 << j); j++)
continue;
if (j > i)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[j == 8 ? 30 : (16 + j)]);
+ infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
i = j + 1;
}
}
/* Statics $ax - $a3. */
if (statics == 1)
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
+ infprintf (is, ",%s", mips_gpr_names[7]);
else if (statics > 0)
- (*info->fprintf_func) (info->stream, ",%s-%s",
- mips_gpr_names[7 - statics + 1],
- mips_gpr_names[7]);
+ infprintf (is, ",%s-%s",
+ mips_gpr_names[7 - statics + 1],
+ mips_gpr_names[7]);
}
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func)
- (info->stream,
- _("# internal disassembler error, unrecognised modifier (%c)"),
- type);
+ infprintf (is,
+ _("# internal disassembler error, "
+ "unrecognised modifier (%c)"),
+ type);
abort ();
}
}
@@ -2112,6 +2010,7 @@ print_mips16_insn_arg (char type,
static int
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
int status;
bfd_byte buffer[2];
int length;
@@ -2119,6 +2018,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
bfd_boolean use_extend;
int extend = 0;
const struct mips_opcode *op, *opend;
+ void *is = info->stream;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
@@ -2155,8 +2055,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
@@ -2169,8 +2068,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length;
}
@@ -2193,8 +2091,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
if (use_extend)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length - 2;
}
@@ -2216,16 +2113,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
}
}
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
if (op->args[0] != '\0')
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
for (s = op->args; *s != '\0'; s++)
{
if (*s == ','
&& s[1] == 'w'
- && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
- == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
+ && GET_OP (insn, RX) == GET_OP (insn, RY))
{
/* Skip the register and the comma. */
++s;
@@ -2233,8 +2129,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
}
if (*s == ','
&& s[1] == 'v'
- && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
- == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
+ && GET_OP (insn, RZ) == GET_OP (insn, RX))
{
/* Skip the register and the comma. */
++s;
@@ -2261,10 +2156,12 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
return length;
}
}
+#undef GET_OP_S
+#undef GET_OP
if (use_extend)
- (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
- (*info->fprintf_func) (info->stream, "0x%x", insn);
+ infprintf (is, "0x%x", extend | 0xf000);
+ infprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
@@ -2375,6 +2272,9 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
#define GET_OP(insn, field) \
(((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
+ - ((MICROMIPSOP_MASK_##field >> 1) + 1))
opend = micromips_opcodes + bfd_micromips_num_opcodes;
for (op = micromips_opcodes; op < opend; op++)
{
@@ -2401,10 +2301,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
break;
case '.':
- delta = GET_OP (insn, OFFSET10);
- if (delta & 0x200)
- delta |= ~0x3ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
break;
case '1':
@@ -2461,10 +2358,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
break;
case '~':
- delta = GET_OP (insn, OFFSET12);
- if (delta & 0x800)
- delta |= ~0x7ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
break;
case 'a':
@@ -2473,7 +2367,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
| (GET_OP (insn, TARGET) << 2));
else
info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
- | ((GET_OP (insn, TARGET)) << 1));
+ | (GET_OP (insn, TARGET) << 1));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (op->name, "jalx") == 0)
@@ -2507,8 +2401,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, DELTA));
break;
case 'k':
@@ -2550,7 +2443,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'p':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ delta = GET_OP_S (insn, DELTA);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
@@ -2824,7 +2717,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'A':
/* Sign-extend the immediate. */
- immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
+ immed = GET_OP_S (insn, IMMA) << 2;
infprintf (is, "%d", immed);
break;
@@ -2840,14 +2733,14 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'D':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
+ delta = GET_OP_S (insn, IMMD);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'E':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
+ delta = GET_OP_S (insn, IMME);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
@@ -2915,8 +2808,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'Q':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
- immed <<= 2;
+ immed = GET_OP_S (insn, IMMQ) << 2;
infprintf (is, "%d", immed);
break;
@@ -2932,16 +2824,15 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
case 'X':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
+ immed = GET_OP_S (insn, IMMX);
infprintf (is, "%d", immed);
break;
case 'Y':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
- if (immed >= -2 && immed <= 1)
- immed ^= 0x100;
- immed = immed << 2;
+ immed = GET_OP_S (insn, IMMY) << 2;
+ if ((unsigned int) (immed + 8) < 16)
+ immed ^= 0x400;
infprintf (is, "%d", immed);
break;
@@ -2992,6 +2883,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
return length;
}
}
+#undef GET_OP_S
#undef GET_OP
infprintf (is, "0x%x", insn);
@@ -3073,12 +2965,12 @@ _print_insn_mips (bfd_vma memaddr,
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
if (status == 0)
{
- unsigned long insn;
+ int insn;
if (endianness == BFD_ENDIAN_BIG)
- insn = (unsigned long) bfd_getb32 (buffer);
+ insn = bfd_getb32 (buffer);
else
- insn = (unsigned long) bfd_getl32 (buffer);
+ insn = bfd_getl32 (buffer);
return print_insn_mips (memaddr, insn, info);
}
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 93238d4..44cfad2 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -197,7 +197,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 },
@@ -593,27 +593,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, IOCT|IOCTP|IOCT2 },
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
/* cfc2 is at the bottom of the table. */
/* cfc3 is at the bottom of the table. */
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
-{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
/* ctc2 is at the bottom of the table. */
/* ctc3 is at the bottom of the table. */
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
-{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
+{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
@@ -658,8 +658,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
@@ -694,14 +694,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
-{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
-{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
-{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
+{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
-{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
-{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
+{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
+{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
@@ -773,8 +773,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
@@ -858,10 +858,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
@@ -884,18 +884,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
+{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
@@ -958,20 +958,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
-{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
-{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
-{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
-{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
+{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
+{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
@@ -1050,9 +1050,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
-{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
-{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
+{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
+{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
@@ -1078,14 +1078,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
-{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
-{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
@@ -1303,10 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
@@ -1428,18 +1428,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
@@ -1618,47 +1618,47 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
-{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
-{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
-{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
-{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
+{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
@@ -1945,10 +1945,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
@@ -2108,14 +2108,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
-{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
+{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
-{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
-{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
-{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
+{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }
+{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
};
#define MIPS_NUM_OPCODES \
generated by cgit v1.1 at 2024-11-22 00:56:25 +0000