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author | Max Filippov <jcmvbkbc@gmail.com> | 2021-04-23 02:03:36 -0700 |
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committer | Max Filippov <jcmvbkbc@gmail.com> | 2021-04-23 03:29:39 -0700 |
commit | b3ea76397a07f5ec99432ed3df9ca848a6aab115 (patch) | |
tree | a2fbfc2fdfff73566082d54454d0d9336ec13282 /opcodes/xtensa-dis.c | |
parent | c1cbb7d8a18374a815b0be38d41ee31748c54d70 (diff) | |
download | gdb-b3ea76397a07f5ec99432ed3df9ca848a6aab115.zip gdb-b3ea76397a07f5ec99432ed3df9ca848a6aab115.tar.gz gdb-b3ea76397a07f5ec99432ed3df9ca848a6aab115.tar.bz2 |
opcodes: xtensa: display loaded literal value
Display literal value loaded with l32r opcode as a part of disassembly.
This significantly simplifies reading of disassembly output.
2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
opcodes/
* xtensa-dis.c (print_xtensa_operand): For PC-relative operand
of l32r fetch and display referenced literal value.
Diffstat (limited to 'opcodes/xtensa-dis.c')
-rw-r--r-- | opcodes/xtensa-dis.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/opcodes/xtensa-dis.c b/opcodes/xtensa-dis.c index e38fc39..cfa058f 100644 --- a/opcodes/xtensa-dis.c +++ b/opcodes/xtensa-dis.c @@ -194,7 +194,8 @@ print_xtensa_operand (bfd_vma memaddr, unsigned operand_val) { xtensa_isa isa = xtensa_default_isa; - int signed_operand_val; + int signed_operand_val, status; + bfd_byte litbuf[4]; if (show_raw_fields) { @@ -216,6 +217,23 @@ print_xtensa_operand (bfd_vma memaddr, &operand_val, memaddr); info->target = operand_val; (*info->print_address_func) (info->target, info); + /* Also display value loaded by L32R (but not if reloc exists, + those tend to be wrong): */ + if ((info->flags & INSN_HAS_RELOC) == 0 + && !strcmp ("l32r", xtensa_opcode_name (isa, opc))) + status = (*info->read_memory_func) (operand_val, litbuf, 4, info); + else + status = -1; + + if (status == 0) + { + unsigned literal = bfd_get_bits (litbuf, 32, + info->endian == BFD_ENDIAN_BIG); + + (*info->fprintf_func) (info->stream, " ("); + (*info->print_address_func) (literal, info); + (*info->fprintf_func) (info->stream, ")"); + } } else { |