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authorAlan Modra <amodra@gmail.com>2019-12-11 16:45:14 +1030
committerAlan Modra <amodra@gmail.com>2019-12-11 21:14:19 +1030
commit1d61b032265e69317f42e8019e072506f11890c5 (patch)
tree226c023afd93046735bb928dc67d6490f8466e97 /opcodes/visium-dis.c
parent13c9c48599ebc8ad2f3a1fb9f672740219cd3841 (diff)
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Remove more shifts for sign/zero extension
cpu/ * epiphany.cpu (f-sdisp11): Don't sign extend with shifts. * lm32.cpu (f-branch, f-vall): Likewise. * m32.cpu (f-lab-8-16): Likewise. opcodes/ * arc-dis.c (BITS): Don't truncate high bits with shifts. * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts. * tic54x-dis.c (print_instruction): Likewise. * tilegx-opc.c (parse_insn_tilegx): Likewise. * tilepro-opc.c (parse_insn_tilepro): Likewise. * visium-dis.c (disassem_class0): Likewise. * pdp11-dis.c (sign_extend): Likewise. (SIGN_BITS): Delete. * epiphany-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate.
Diffstat (limited to 'opcodes/visium-dis.c')
-rw-r--r--opcodes/visium-dis.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/visium-dis.c b/opcodes/visium-dis.c
index c71f8cf..41943ad 100644
--- a/opcodes/visium-dis.c
+++ b/opcodes/visium-dis.c
@@ -94,7 +94,7 @@ disassem_class0 (disassemble_info *info, unsigned int ins)
/* BRR instruction. */
{
unsigned cbf = (ins >> 27) & 0x000f;
- int displacement = ((int) (ins << 16)) >> 16;
+ int displacement = ((ins & 0xffff) ^ 0x8000) - 0x8000;
if (ins == 0)
(*info->fprintf_func) (info->stream, "nop");