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| author | Jeff Law <law@redhat.com> | 1996-08-23 15:41:30 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-08-23 15:41:30 +0000 |
| commit | 4be84c49517144c93dcce13ef5489984b7ea0dad (patch) | |
| tree | 87bea275c4b63f0d59d2936d82bfe590b82030dc /opcodes/v850-opc.c | |
| parent | 26b3dc44a5445fbb7e3b2a0677a43d08c91cfa0d (diff) | |
| download | gdb-4be84c49517144c93dcce13ef5489984b7ea0dad.zip gdb-4be84c49517144c93dcce13ef5489984b7ea0dad.tar.gz gdb-4be84c49517144c93dcce13ef5489984b7ea0dad.tar.bz2 | |
* v850-opc.c (v850_operands): D6 -> DS7. References changed.
Add D8 for 8-bit unsigned field in short load/store insns.
(IF4A, IF4D): These both need two registers.
(IF4C, IF4D): Define. Use 8-bit unsigned field.
(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
for "ldsr" and "stsr".
* v850-opc.c (v850_operands): 3-bit immediate for bit insns
is unsigned.
Fixing up the parser again.
Diffstat (limited to 'opcodes/v850-opc.c')
| -rw-r--r-- | opcodes/v850-opc.c | 35 |
1 files changed, 21 insertions, 14 deletions
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index cf6f6cf..8c3d45e 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -44,12 +44,12 @@ const struct v850_operand v850_operands[] = { #define I16 (I5U+1) { 16, 0, 0, 0, 0 }, -/* The DISP6 field in a format 4 insn. */ -#define D6 (I16+1) - { 6, 1, 0, 0, 0 }, +/* The signed DISP7 field in a format 4 insn. */ +#define D7S (I16+1) + { 7, 0, 0, 0, V850_OPERAND_SIGNED }, /* The DISP9 field in a format 3 insn. */ -#define D9 (D6+1) +#define D9 (D7S+1) { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED }, /* The DISP16 field in a format 6 insn. */ @@ -66,7 +66,12 @@ const struct v850_operand v850_operands[] = { #define CCCC (B3+1) /* The 4 bit condition code in a setf instruction */ - { 4, 0, 0, 0, V850_OPERAND_CC } + { 4, 0, 0, 0, V850_OPERAND_CC }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define D8 (CCCC+1) + { 8, 0, 0, 0, 0 }, + } ; @@ -80,8 +85,10 @@ const struct v850_operand v850_operands[] = { #define IF3 {D9} /* 16-bit load/store instruction (Format IV) */ -#define IF4A {D6, R2} -#define IF4B {R2, D6} +#define IF4A {D7S, R1, R2} +#define IF4B {R2, D7S, R1} +#define IF4C {D8, R1, R2} +#define IF4D {R2, D8, R1} /* Jump instruction (Format V) */ #define IF5 {D22} @@ -117,11 +124,11 @@ const struct v850_operand v850_operands[] = { const struct v850_opcode v850_opcodes[] = { /* load/store instructions */ { "sld.b", OP(0x00), OP_MASK, IF4A }, -{ "sld.h", OP(0x00), OP_MASK, IF4A }, -{ "sld.w", OP(0x00), OP_MASK, IF4A }, +{ "sld.h", OP(0x00), OP_MASK, IF4C }, +{ "sld.w", OP(0x00), OP_MASK, IF4C }, { "sst.b", OP(0x00), OP_MASK, IF4B }, -{ "sst.h", OP(0x00), OP_MASK, IF4B }, -{ "sst.w", OP(0x00), OP_MASK, IF4B }, +{ "sst.h", OP(0x00), OP_MASK, IF4D }, +{ "sst.w", OP(0x00), OP_MASK, IF4D }, { "ld.b", OP(0x00), OP_MASK, IF7A }, { "ld.h", OP(0x00), OP_MASK, IF7A }, @@ -212,9 +219,9 @@ const struct v850_opcode v850_opcodes[] = { { "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} }, { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} }, { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} }, -{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} }, -{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} }, -{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} }, +{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), I5U }, +{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), IF1 }, +{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), IF1 }, { "nop", one(0x00), one(0xff), {0} }, } ; |